TW201314842A - Semiconductor processing method of capacitor structure - Google Patents

Abstract

A semiconductor processing method of a capacitor structure is disclosed, which forms an insulation layer on the top of a substrate and then a stack structure formed on the insulation layer, wherein the stack structure comprises at least a first borophosphosilicate glass layer and at least a second borophosphosilicate glass layer with different doping concentrations of born and phosphorus by gradient doping concentration of born, phosphorus and silicon in the stacking process. At least one opening communicated with the substrate is formed on the stack structure. After that, etching is performed at one side wall of the opening by a dry/wet etching process. A concave-convex surface is formed on the side wall corresponding to the first borophosphosilicate glass layer and the second borophosphosilicate glass layer due to the different etching rates from the different doping concentrations of born, phosphorus and silicon. The capacitor process is completed after a bottom electrode, a dielectric layer and an upper electrode are installed. The induction area of the capacitors can be increased and the charge storage amount of the capacitors can also be increased by the convex-concaved surface formed after etching with the stack structure with different doping concentrations of born, phosphorus and silicon in this invention.

Description

Capacitor structure semiconductor process method

The invention relates to a semiconductor manufacturing method, in particular to a semiconductor manufacturing method of a capacitor structure.

The ability of a capacitor to store charge depends on the magnitude of the dielectric constant, the distance between the two conductive plates, and the area of the conductive plate. However, in the case where the material having a higher dielectric constant and the distance of the conductive plate have not been found to be shortened, the only way to increase the stored charge is to increase the area of the conductive plate. However, in today's process technology requirements, and the size of the components is constantly reduced, the increase in the area of the conductive plate must increase the component size, which does not meet the requirements of today's circuit components.

Thus, as disclosed in the Patent Publication No. I341009 of the Republic of China, a "metal-insulating layer-metal capacitor and a method of manufacturing the same" is disclosed in which a plurality of insulating layers of different materials are stacked on a substrate, and a connection is provided on the insulating layer. The opening of the substrate is then laterally etched by using an etching solution having different etching rates for the insulating layers of different materials, so that the sidewalls of the opening form a plurality of grooves, thereby forming a crown-shaped structure, and finally performing on the sidewall surface. Capacitor process to increase the capacitive sensing area and increase the charge storage capacity. However, the insulating layers of different materials are complicated in the production process, and need to be repeated in the process of changing the material type in the process, and it is necessary to avoid the problem of mixing materials of different insulating layers, which needs to be improved.

In addition, as disclosed in the Patent Publication No. I284390 of the Republic of China, a "method for manufacturing a stored charge element" is disclosed, which also produces a capacitor for the purpose of fabricating a crown-shaped structure, but the stacked insulating layer is composed of a plurality of layers of a graded material. The material of the stacked insulating layer disclosed in the specification is yttrium oxide, tantalum nitride, hafnium oxide or yttrium zirconium oxide, etc., by changing the germanium content in the material to form a graded stacked insulating layer, but Such materials are more expensive and less suitable for use.

The main object of the present invention is to solve the problem that the manufacturing process of the insulating layers of different materials is complicated, and it is easy to mix when converting materials. Another object of the present invention is to reduce the material cost of the insulating layer of the multilayer stack structure.

To achieve the above objective, the present invention provides a semiconductor manufacturing method for a capacitor structure, comprising the steps of: S1: providing a substrate; S2: forming a stacked structure on a surface of the substrate, the stacked structure including at least one first stacked on each other a borophosphonium silicate glass layer and at least one second borophosphonium silicate glass layer, wherein the first borophosphon glass layer has a boron doping concentration that is not equal to a boron doping concentration of the second borophosphon glass layer; S3: on the stack Forming at least one opening connecting the substrate, and the opening has a sidewall; S4: performing an etching process on the sidewall of the opening, the sidewall corresponding to the first borophosphon glass layer and the second borophosphon glass layer Forming a concave-convex surface; S5: forming a lower electrode on the sidewall and the surface of the substrate; S6: forming a dielectric layer on the surface of the lower electrode away from the sidewall and the substrate; S7: leaving the dielectric layer away from the lower electrode The surface forms an upper electrode.

It can be seen from the above description that the first borophosphon glass layer and the second borophosphorus glass layer doped with different concentrations form the stacked structure, and only need to be controlled in a single layer stacking process during the process. The doping concentration difference of phosphonium can have the effect of multi-layer stacking process, and has the advantages of simple process, easy control of process conditions and low material cost.

The detailed description and technical contents of the present invention will now be described as follows:

Please refer to FIG. 1 and FIG. 2A to FIG. 2G. The present invention is a semiconductor manufacturing method for a capacitor structure, which comprises the following steps:

S1: A substrate 10 is provided. In the present invention, a dynamic random access memory is used as an embodiment. Please refer to "FIG. 2A" and "FIG. 2B". The substrate 10 includes at least one transistor structure 11. And the transistor structure 11 is connected with a word line (not shown) and a bit line (not shown) for use as a dynamic access material, and the transistor structure 11 can be a vertical transistor structure 11, To reduce the area occupied by the electronic components on the substrate 10. The substrate 10 further includes at least one electrical contact 12 connected to the transistor structure 11, and the electrical contact 12 is provided with an insulating layer 13 to eliminate the possibility of leakage conduction.

S2: forming a stacked structure 20 on the surface of the substrate 10. Referring to FIG. 2C, the stacked structure 20 includes at least one first borophosphon glass layer 21 and at least one second borophosphonium layer stacked on each other. The glass layer 22, the boron doping concentration of the first borophosphon glass layer 21 is not equal to the boron doping concentration of the second borophosphon glass layer 22, wherein the first borophosphon glass layer 21 and the second The borophosphonium silicate glass layer 22 is formed by chemical vapor deposition using a boron precursor, a phosphorus precursor and a ruthenium precursor, and the boron precursor may be Triethyl Borate (TEB). The precursor may be Triethyl phosphate (TEP), and the precursor of the ruthenium may be Tetraethoxysilane (TEOS). Please refer to "Fig. 3A" for the first borophosphorus glass layer. 21 and the second borophosphonium silicate glass layer 22 can be formed in the following steps: S2A: forming the first borophosphonium silicate glass layer 21, placing the substrate 10 in a reaction chamber, and passing the boron precursor, Phosphorus precursor and the gas of the ruthenium precursor, and setting the ruthenium precursor as a first stream 31, the boron precursor is a second flow rate 32, the phosphorus precursor is a third flow rate 33, and the first borophosphon glass layer 21 is formed on the substrate 10 by vapor deposition; S2B: buffer period Maintaining the flow rate of the ruthenium precursor and stopping the second flow rate 32 and the third flow rate 33 at an interval time t1, thereby eliminating the possibility that the first borophosphonium silicate glass layer 21 affects subsequent processes, except for maintaining In addition to the flow rate of the ruthenium precursor, as shown in FIG. 3B, the flow rate of the ruthenium precursor is changed to the sixth flow rate 36 during the buffer period, and the sixth flow rate 36 is not equal to the first flow rate 31. As shown in FIG. 3B, it is larger or smaller than the first flow rate 31; S2C: forming the second borophosphon glass layer 22, continuing to maintain the ruthenium precursor at the first flow rate 31, and setting the boron precursor to a fourth flow rate 34, the phosphorus precursor is a fifth flow rate 35, forming the second borophosphorus glass layer 22, the fourth flow rate 34 is not equal to the second flow rate 32, and the fifth flow rate 35 is not equal to the first a third flow rate 33, the second flow rate 32, the third flow rate 33, the fourth flow rate 34, and the fifth flow The amount 35 is smaller than the first flow rate 31. In the embodiment, the fourth flow rate 34 is greater than the second flow rate 32. The fifth flow rate 35 is greater than the third flow rate 33, that is, the second borophosphorus glass. The concentration of boron phosphorus in the layer 22 is greater than the concentration of boron and phosphorus in the first borophosphon glass layer 21, and the precursor of the tantalum may be adjusted to be a first flow rate 31, and the first flow rate may be adjusted to a seventh flow rate 37. The seventh flow rate 37 is not equal to the first flow rate 31, and thus is greater or smaller than the first flow rate 31 as shown in FIG. 3B. Specifically, the second flow rate 32 and the third flow rate are specifically illustrated. 33. The fourth flow rate 34 and the fifth flow rate 35 must be smaller than the first flow rate 31, the sixth flow rate 36, and the seventh flow rate 37.

S2D: Repetition process, repeating steps S2A, S2B, and step S2C, please repeat the process to form the first borophosphorus glass layer 21 and the second stacked alternately as shown in FIG. 2D. Boron phosphorus glass layer 22.

Please continue to refer to FIG. 2E. Before proceeding to step S3, in order to further strengthen the softening degree and structural strengthening on the stacked structure 20, the following steps are further included: A1: forming a softening layer 41 on the stacked structure. The surface of the soft layer 41 is made of yttrium oxide in the form of a plasma; and A2: a support layer 42 is formed on the surface of the soft layer 41, and the material of the support layer 42 is tantalum nitride, since the support layer 42 The hardness is greater than the other layers and can be used as a support structure to avoid structural damage during subsequent etching.

After completing the above process, proceed to the following steps:

S3: The opening 50 is provided. Referring to FIG. 2F, an opening 50 is formed in the direction of the substrate 10 from the supporting layer 42. In the embodiment where the supporting layer 42 and the softening layer 41 are not disposed, Forming at least one opening 50 communicating with the substrate 10 directly on the stack structure 20, and the opening 50 has a side wall 51 having a plurality of openings 50 spaced apart from each other, wherein the insulating layer 13 has a plurality of A through hole that communicates with the opening 50.

S4: etching the sidewall 51 of the opening 50, as shown in FIG. 2G, so that the sidewall 51 corresponds to the first borophosphon glass layer 21 and the second borophosphon glass layer 22 to form an uneven surface. The stacked structure 20 is thus formed into a plurality of columns.

Next, the settings of the capacitor upper electrode 63, the lower electrode 61, and the dielectric layer 62 are performed as follows:

S5: forming the lower electrode 61, as shown in FIG. 4A, forming the lower electrode 61 on the sidewall 51 and the surface of the substrate 10. The lower electrode 61 is connected to the transistor structure 11 through a plurality of through holes. .

S6: forming a dielectric layer 62, as shown in FIG. 4B, forming the dielectric layer 62 on the surface of the lower electrode 61 away from the sidewall 51 and the substrate 10; S7: forming an upper electrode 63, please Referring to FIG. 4C, an upper electrode 63 is formed on the surface of the dielectric layer 62 away from the lower electrode 61. By the above steps, the preparation of the capacitor is completed.

In summary, since the present invention utilizes chemical vapor deposition to control the flow rate of the carrier gas of the boron precursor and the phosphorus precursor in the reaction chamber, the same mixed material can be used to prepare the doping at different concentrations. The boron phosphide glass layer 21 and the second borophosphon glass layer 22 form the stacked structure 20, and only need to control the doping concentration difference of the borophosphonium in the single-layer stacking process to have a multi-layer stacking process. The effect of the process, and the material cost and preparation cost of the borophosphorus bismuth glass are lower than the process method for controlling the ruthenium concentration. Therefore, the invention has the advantages of simple process, easy control of process conditions and low material cost. Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

10. . . Base

11. . . Crystal structure

12. . . Electrical contact

13. . . Insulation

20. . . Stack structure

twenty one. . . First borophosphonium glass layer

twenty two. . . Second borophosphonium glass layer

31. . . First flow

32. . . Second flow

33. . . Third flow

34. . . Fourth flow

35. . . Fifth flow

36. . . Sixth flow

37. . . Seventh flow

T1. . . Intervals

41. . . Softening layer

42. . . Support layer

50. . . Opening

51. . . Side wall

61. . . Lower electrode

62. . . Dielectric layer

63. . . Upper electrode

FIG. 1 is a schematic diagram of a process step of a preferred embodiment of the present invention.

2A-2G are schematic diagrams showing a manufacturing process of a preferred embodiment of the present invention.

3A is a schematic view of gas flow in a reaction chamber according to a preferred embodiment of the present invention.

3B is a schematic view of gas flow in a reaction chamber according to another preferred embodiment of the present invention.

4A-4C are schematic views showing the preparation of a capacitor according to a preferred embodiment of the present invention.

S1 ~ S7, S2A ~ S2D, A1, A2. . . step

Claims (11)

A semiconductor manufacturing method for a capacitor structure, comprising the steps of: S1: providing a substrate; S2: forming a stacked structure on a surface of the substrate, the stacked structure comprising at least one first borophosphon glass layer and at least one layer stacked on each other a second borophosphonium glass layer, the boron doping concentration of the first borophosphon glass layer is not equal to the boron doping concentration of the second borophosphon glass layer; S3: forming at least one connected to the substrate on the stacked structure Opening, and the opening has a sidewall; S4: etching the sidewall of the opening to form a concave-convex surface corresponding to the first borophosphon glass layer and the second borophosphon glass layer; S5: The sidewall and the surface of the substrate form a lower electrode; S6: a dielectric layer is formed on the surface of the lower electrode away from the sidewall and the substrate; and S7: an upper electrode is formed on the surface of the dielectric layer away from the lower electrode. The semiconductor manufacturing method of the capacitor structure according to claim 1, wherein the first borophosphonium glass layer and the second borophosphorus glass layer are a boron precursor, a phosphorus precursor, and a precursor The substance is formed by chemical vapor deposition. The semiconductor process method of the capacitor structure according to claim 2, wherein the boron precursor is triethyl borate, the phosphorus precursor is triethyl phosphate, and the hafnium precursor is tetraethyl citrate. ester. The semiconductor manufacturing method of the capacitor structure according to claim 2, wherein the step S2 includes the following steps: S2A: disposing the substrate in a reaction chamber, and passing the boron precursor, the phosphorus precursor And the gas of the ruthenium precursor, and the ruthenium precursor is set to a first flow rate, the boron precursor is a second flow rate, and the phosphorus precursor is a third flow rate to form the first borophosphorus glass layer; S2B: continuing to inject the gas of the ruthenium precursor into the reaction chamber, and stopping the passage of the second flow rate and the third flow rate; S2C: continuing to infuse the gas of the ruthenium precursor in the reaction chamber, and adjusting the The boron precursor is at a fourth flow rate, the phosphorus precursor is a fifth flow rate, forming the second borophosphorus glass layer, the fourth flow rate is not equal to the second flow rate, and the fifth flow rate is not equal to the third flow rate The second flow rate, the third flow rate, the fourth flow rate, and the fifth flow rate are all smaller than the first flow rate. The semiconductor process method of the capacitor structure of claim 4, wherein in step S2B, the ruthenium precursor is adjusted to a sixth flow rate, the sixth flow rate is not equal to the first flow rate, and is greater than the second The flow rate, the third flow rate, the fourth flow rate, and the fifth flow rate. The semiconductor process method of the capacitor structure of claim 4, wherein in step S2C, the ruthenium precursor is adjusted to a seventh flow rate, the seventh flow rate is not equal to the first flow rate, and is greater than the second The flow rate, the third flow rate, the fourth flow rate, and the fifth flow rate. The semiconductor manufacturing method of the capacitor structure according to claim 4, wherein there is further a step S2D: repeating steps S2A, S2B and step S2C to form a plurality of first borophosphorus glass layers and interdigitated stacks thereof A glass layer of diboron phosphide. The semiconductor manufacturing method of the capacitor structure according to claim 1, wherein the opening has a plurality of openings spaced apart from each other, and the substrate comprises at least one transistor structure connected to the lower electrode layer. The semiconductor manufacturing method of the capacitor structure of claim 8, wherein the substrate and the lower electrode layer further have an insulating layer, and the insulating layer has a plurality of through holes for the lower electrode layer to pass through. Connected to the transistor structure. The semiconductor manufacturing method of the capacitor structure of claim 1, wherein the step S2 and the step S3 further comprise the following steps: A1: forming a softening layer on the surface of the stacked structure; and A2: forming a A support layer is on the surface of the softening layer. The semiconductor manufacturing method of the capacitor structure according to claim 10, wherein the softening layer is made of yttrium oxide in the form of a plasma, and the material of the supporting layer is tantalum nitride, and the opening formed in step S3. Passing through the support layer and the softening layer.