TW201310611A - Electrostatic discharge (ESD) protection element and ESD circuit thereof - Google Patents

Abstract

An ESD protection circuit connected between an I/O pad and an internal circuit is disclosed. The ESD protection circuit includes a P type ESD protection element which has a first P type doped region, a first isolation structure and a first N type doped region. The first isolation structure is disposed inside the first P type doped region, and the first N type doped region is disposed to encompass said first P type doped region. During an ESD event, the first P type doped region of the P type ESD protection element receives an ESD current and drains it away, and the parasitical capacitance of the P type ESD protection element decreases based on the area of the first P type doped region.

Description

Electrostatic discharge protection component and circuit thereof

The present invention relates to an electrostatic discharge (ESD) protection component, and more particularly to an electrostatic discharge protection component for an electrostatic discharge protection circuit that has a relatively low parasitic capacitance and a relatively high ESD capability.

In an integrated circuit, in order to prevent a large amount of electric charge from being transmitted to the integrated circuit through the I/O pin of the integrated circuit in a very short time, the internal circuit of the integrated circuit is destroyed, usually inside. An electrostatic discharge protection circuit is provided between the circuit and the I/O pin. When an excessive transient voltage or current is generated, the ESD protection circuit can react instantaneously to direct excess transient voltage or current to the voltage source to avoid damage caused by transient voltage or current flowing into the core circuit.

Please refer to the first figure, which is a schematic diagram of a conventional electrostatic discharge protection circuit (ESD protection circuit). As shown in the first figure, the ESD protection circuit 13 is connected between the input/output pad (I/O pad) 11 and the internal circuit 15 to prevent the internal circuit 15 from being damaged by ESD. The ESD protection circuit 13 includes two diodes 131, 133 which are connected in series and reverse biased, one connected to the voltage source Vs and the input/output pad 11, and the other connected to the ground potential and the input/output pad 11. When the voltage at the input/output pad 11 exceeds the breakdown voltage of the reverse biasing diodes 131, 133, the reverse biasing diodes 131, 133 enter a collapse mode to quickly remove current.

Please refer to FIGS. 2A and 2B for a schematic diagram of a diode used in an electrostatic discharge protection circuit. In order to improve the ESD capability, the junction area of the diodes 131, 133 is usually increased to withstand a larger transient voltage or current. However, if the junction area of the diodes 131 and 133 is increased, the parasitic capacitance effect of the diodes 131 and 133 is increased, especially at a high speed transmission, thereby affecting the accuracy of each function of the high-speed signal and the circuit.

The industry is still in high demand for ESD circuits that are more sensitive and have high HBM (Human Body Mode) ESD capability. Therefore, it is urgent to propose a novel ESD protection component layout design structure and its circuit, which has a higher HBM ESD capability to release a larger transient voltage or current, and can reduce the parasitic discharge of the electrostatic discharge protection diode. Capacitance effect.

In view of the above, one of the objects of the embodiments of the present invention is to provide a layout design structure of an ESD protection component and a circuit thereof, which can reduce the parasitic capacitance value without reducing the area of the electrostatic discharge protection diode as a whole, and provide an original or even more High HBM (Human Body Mode) ESD capability to release transient voltage or current, thus contributing to high-speed signal output input design.

The present invention discloses an electrostatic discharge (ESD) protection element for deriving an electrostatic discharge current of an electrostatic discharge protection circuit. The ESD protection device includes a first conductive type doped region, a first insulating structure, a second conductive type doped region, and a second insulating structure. The first insulating structure is disposed in the first conductive type doped region. The second conductive type doped region surrounds the first conductive type doped region. The second insulating structure is disposed between the first conductive type doped region and the second conductive type doped region. Wherein, when an ESD event occurs, the first conductive type doped region receives the electrostatic discharge current and leads it out, and the parasitic capacitance value of the electrostatic discharge protection element decreases according to the area of the first conductive type doped region.

The invention further discloses an electrostatic discharge (ESD) protection circuit connected between an input/output pad (I/O pad) and an internal circuit. The ESD protection circuit includes a P-type ESD protection component including a first P-type doped region, a first insulating structure, and a first N-type doped region. The first insulating structure is disposed in the first P-type doped region, and the first N-type doped region surrounds the first P-type doped region. Wherein, when an ESD event occurs, the first P-type doped region of the P-type ESD protection component receives an ESD current and is derived, and the parasitic capacitance value of the P-type ESD protection component is according to the first P-type The area of the doped region is reduced.

First, please refer to the third figure, which is a circuit diagram of an electrostatic discharge (ESD) protection circuit 33 according to an embodiment of the present invention. As shown in the third figure, the ESD protection circuit 33 is connected between an input/output pad (I/O pad) 31 and an internal circuit 35 to prevent the internal circuit 35 from being damaged by ESD. The electrostatic discharge protection circuit 33 includes a P-type electrostatic discharge protection element 331, an N-type electrostatic discharge protection element 333, and a resistor R. The P-type ESD protection component 331 is coupled between the input/output pad 31 and a voltage source Vs. The N-type ESD protection component 333 is coupled between the input/output pad 31 and a ground terminal, wherein the N-type electrostatic discharge The protection element 333 is connected in series to the P-type electrostatic discharge protection element 331. The resistor R is coupled between the input/output pad 31 and the internal circuit 35.

Specifically, the internal circuit 35 is a single chip, a timing controller, or a driving circuit. The P-type electrostatic discharge protection element 331 is a P-type diode, and the N-type electrostatic discharge protection element 333 is an N-type diode. Referring to the fourth figure, the P-type electrostatic discharge protection component 331 is taken as an example, and the diode layout includes a first N-type doping region 3331, a first P-type doping region 3333, and a first insulation. The structure 3337 and a second insulating structure 3335. The cover shape of the first P-type doped region 3333 is a cavity square, and the first insulating structure 3337 is disposed in the first P-type doped region 3333, that is, the first P-type doped region 3333. Part of the cavity. The first N-type doping region 3331 surrounds the first P-type doping region 3333. The second insulating structure 3335 is disposed between the first N-type doped region 3331 and the first P-type doped region 3333. In one embodiment, the first insulating structure 3337 and the second insulating structure 3335 comprise a shallow A trench isolation layer (STI), wherein the outer line connecting the second insulating structure 3335 to the first N-type doped region 3331 may form a square, a polygon or a circle, but is not limited to the disclosure.

When the user touches the input/output pad 31 to generate an ESD current (an ESD event occurs), the first P-type doping region 3333 of the P-type ESD protection element 331 receives the ESD current and Since the area of the first P-type doped region 3333 is reduced, the parasitic capacitance value of the P-type ESD protection element 331 is lowered.

Specifically, the parasitic capacitance value of the electrostatic discharge protection element is lowered according to the area ratio of the first P-type doping region 3333. For example, the area of the first P-type doped region 3333 of the conventional P-type electrostatic discharge protection element 331 is 215 um ² , and the first P-type doping of the P-type ESD protection element 331 of the first insulating structure 3337 of the present invention is proposed. The area of the miscellaneous area 3333 is 104 um ² . Through the verification of CMOS process test component (Testkey), the hollow ESD protection diode proposed by the present invention can be reduced by nearly 50% (104um ² / compared with the conventional ESD protection diode structure) while providing the same HBM ESD capability. Parasitic capacitance effect of 215um ² ).

Similarly, the inside of the N-type electrostatic discharge protection element 333 is an N-type doped region (second N-type doped region), and the inside thereof is also burred to provide an insulating structure. When an ESD event occurs when the user touches the input/output pad 31, since the area of the N-type doping region of the N-type ESD protection element 333 is reduced, the parasitic capacitance value of the N-type ESD protection element 333 is also lowered.

In another embodiment of the present invention, the shape of the doped region inside the electrostatic discharge protection element (N-type or P-type) may also be a cavity circle or a cavity polygon. As shown in Figures 5A and 5B. Specifically, the hollow polygon has at least eight sides and is bilaterally symmetrical. Due to the hollow circular or hollow polygonal structure of the inner doped region, when the doped region of the electrostatic discharge protection element receives the electrostatic discharge current, it can be uniformly led out.

According to the above embodiment, the ESD protection circuit proposed by the present invention changes the layout design of the ESD protection component, and the parasitic capacitance effect can be reduced without reducing the area of the electrostatic discharge protection diode as a whole. In addition, the present invention can evenly derive the transient voltage or current from the input/output pad 31, and provide an original or even higher HBM ESD capability to release the transient voltage or current, thereby contributing to the circuit design of the high-speed signal. .

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

Conventional knowledge

11. . . Input and output pad

13. . . ESD protection circuit

15. . . Internal circuit

Vs. . . power source

R. . . resistance

131, 133. . . Dipole

this invention

31. . . Input and output pad

33. . . ESD protection circuit

35. . . Internal circuit

Vs. . . power source

R. . . resistance

331. . . P type electrostatic discharge protection component

333. . . N type electrostatic discharge protection element

3331. . . First N-doped region

3333. . . First P-doped region

3335. . . Second insulating structure

3337. . . First insulating structure

The first figure is a schematic diagram of a conventional electrostatic discharge protection circuit.
The second A and B diagrams are schematic diagrams of conventional diodes for electrostatic discharge protection circuits.
The third figure is a circuit diagram of an electrostatic discharge protection circuit according to an embodiment of the present invention.
The fourth figure is a schematic view of an electrostatic discharge protection element according to an embodiment of the present invention.
5A and 5B are schematic views of an electrostatic discharge protection element according to another embodiment of the present invention.

3331. . . First N-doped region

3333. . . First P-doped region

3335. . . Second insulating structure

3337. . . First insulating structure

Claims (17)

An electrostatic discharge (ESD) protection component is used to derive an electrostatic discharge current of an electrostatic discharge protection circuit, the electrostatic discharge protection component comprising:
a first conductive type doped region;
a first insulating structure disposed in the first conductive type doped region;
a second conductive type doped region surrounding the first conductive type doped region; and a second insulating structure disposed between the first conductive type doped region and the second conductive type doped region;
Wherein, when an ESD event occurs, the first conductive type doped region receives the electrostatic discharge current and leads it out, and the parasitic capacitance value of the electrostatic discharge protection element is determined according to the area of the first conductive type doped region. reduce.

The electrostatic discharge protection device of claim 1, wherein the first conductive type doped region is a P-type doped region, and the second conductive type doped region is an N-type doped region.

The electrostatic discharge protection device of claim 1, wherein the first conductive type doped region is an N-type doped region, and the second conductive type doped region is a P-type doped region.

The electrostatic discharge protection device of claim 1, wherein the electrostatic discharge protection circuit is connected between an input/output pad (I/O pad) and an internal circuit when contacting the input and output. The ESD event occurs when the pad generates the electrostatic discharge current.

The electrostatic discharge protection device of claim 4, wherein the internal circuit is a single chip, a timing controller or a driving circuit.

The electrostatic discharge protection device of claim 1, wherein the first insulating structure and the second insulating structure comprise a shallow trench isolation layer (STI), wherein the second insulating structure The external lines connected to the second conductive type doped region are formed in a square, a polygon or a circle.

The electrostatic discharge protection device of claim 1, wherein the first conductive type doped region covers a cavity circle or a cavity polygon.

The electrostatic discharge protection element of claim 7, wherein the hollow polygon has at least eight sides and is bilaterally symmetrical.

An electrostatic discharge (ESD) protection circuit is connected between an input/output pad (I/O pad) and an internal circuit, and the electrostatic discharge protection circuit includes:
A P-type ESD protection component is coupled between the input and output pads and a voltage source, and includes:
a first P-type doped region;
a first insulating structure disposed in the first P-type doped region; and a first N-type doped region surrounding the first P-type doped region;
Wherein, when an ESD event occurs, the first P-type doped region of the P-type ESD protection component receives an ESD current and leads it out, and the parasitic capacitance value of the P-type ESD protection component is according to the The area of the first P-type doped region is reduced.

The electrostatic discharge protection circuit as described in claim 9 further includes:
An N-type ESD protection component is coupled between the input/output pad and a ground end, wherein the N-type ESD protection component is serially connected to the P-type ESD protection component, and includes:
a second N-type doped region;
a second insulating structure disposed in the second N-type doped region; and a second P-type doped region surrounding the second N-type doped region; and a resistor coupled to the input and output Between the pad and the internal circuit;
Wherein, when the ESD event occurs, the second N-type doped region of the N-type ESD protection component receives the ESD current and leads it out, and the parasitic capacitance value of the N-type ESD protection component is according to the The area of the second N-type doped region is reduced.

The electrostatic discharge protection circuit of claim 10, wherein the P-type electrostatic discharge protection component and the N-type electrostatic discharge protection component further comprise a third insulating structure, and the first P-type doped region is respectively disposed And between the first N-type doped region and the second N-type doped region and the second P-type doped region.

The electrostatic discharge protection circuit of claim 11, wherein the first insulation structure, the second insulation structure, and the third insulation structure comprise a shallow trench isolation layer (STI), The external line connecting the third insulating structure to the first N-type doping region or the second P-type doping region forms a square, a polygon or a circle.

The electrostatic discharge protection circuit according to claim 11, wherein the P-type electrostatic discharge protection element is a P-type diode, and the N-type electrostatic discharge protection element is an N-type diode.

The electrostatic discharge protection circuit of claim 10, wherein the ESD event occurs when the input/output pad is contacted to generate the electrostatic discharge current.

The electrostatic discharge protection circuit of claim 9, wherein the internal circuit is a single chip, a timing controller or a driving circuit.

The electrostatic discharge protection circuit of claim 9, wherein the first P-type doped region and the second N-type doped region are covered by a cavity circle or a hollow polygon. (cavity polygon).

The electrostatic discharge protection circuit of claim 16, wherein the hollow polygon has at least eight sides and is bilaterally symmetrical.