經濟部智慧財產局員工消費合作社印製 565928 6790twf. doc/006 B7 五、發明說明（ί ) 本發明是有關於一種電子電路，且特別是有關於一種 半導體靜電放電（electrostatic discharge，ESD)保護電路。 在一種積體電路(1C)的製作中，靜電放電(ESD)是造成 1C損害的主要因素之一，靜電放電通常會在工作場合中出 現’比如當有人走在放有半導體晶圓的地毯上，假如相對 溼度高，約有幾百伏特的靜電電壓會存在人體與晶圓上， 假如溼度低的話，靜電電壓甚至會高達幾千伏特。假如有 一個導電的物件偶然的碰觸到這些晶圓，就會產生一個很 強的靜電放電，並損害晶圓上的1C，在製作複合式金氧半 導體(CMOS)元件時靜電放電是一個特別嚴重的問題。 爲了保護晶圓不受靜電放電的損害，有許多用以解決 靜電放電問題的方法被提出來，最常見的一個傳統方法就 是在晶片上的輸入/輸出(I/O)墊與內部電路之間放置一個靜 電放電保護電路，將其設計爲開始導通或用來承受崩潰， 藉以提供一個接地的導電路徑。因爲崩潰機制被設計成無 破壞性的，電路提供了一個正常的開放通路，此通路只有 在輸入或輸出端出現高電壓時才會關閉，透過連接此通路 終端可以進行無害的放電。而近來，正在進行一種尖端放 電靜電放電保護結構的硏究。 在上面的敘述中，尖端放電靜電放電現象會發生在導 電物件的尖銳端上，因爲在尖端的電場非常的強，雖然在 尖銳觸的S?電表面會蓄積電何’靜電表面加速的充電效果 會更容易使放電發生。 當元件的尺寸由次微米縮小到深次微米時，爲了有效 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 565928 6790twf. Doc / 006 B7 V. Description of the invention (ί) The invention relates to an electronic circuit, and in particular to a semiconductor electrostatic discharge (ESD) protection circuit . In the manufacture of a integrated circuit (1C), electrostatic discharge (ESD) is one of the main factors causing 1C damage. Electrostatic discharge usually occurs in the workplace 'for example when someone walks on a carpet with a semiconductor wafer If the relative humidity is high, about a few hundred volts of electrostatic voltage will be stored on the human body and the wafer. If the humidity is low, the electrostatic voltage may even reach several thousand volts. If a conductive object accidentally touches these wafers, a strong electrostatic discharge will be generated and the 1C on the wafer will be damaged. Electrostatic discharge is a special problem when manufacturing composite metal-oxide-semiconductor (CMOS) devices. serious problem. In order to protect the wafer from electrostatic discharge, many methods have been proposed to solve the problem of electrostatic discharge. The most common traditional method is between the input / output (I / O) pad on the wafer and the internal circuit. Place an ESD protection circuit that is designed to start conducting or to withstand a crash to provide a conductive path to ground. Because the crash mechanism is designed to be non-destructive, the circuit provides a normal open path. This path will only be closed when a high voltage is present at the input or output. The terminals can be harmlessly discharged by connecting to this path. Recently, researches on a protection structure of a tip discharge electrostatic discharge are being conducted. In the above description, the tip discharge electrostatic discharge phenomenon will occur on the sharp end of the conductive object, because the electric field at the tip is very strong, although the sharply touching S? Electric surface will accumulate electricity, and the electrostatic surface accelerates the charging effect. It will be easier for the discharge to occur. When the size of the component is reduced from sub-micron to deep sub-micron, in order to be effective 3 paper sizes apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------- --- (Please read the precautions on the back before filling this page)
La· .線 ¾齊即智慧財產局員工消費合作杜印製 565928 67 90twf .doc/0 06 jsj B7 五、發明說明（1) 的增加1C的積集度，縮小尺寸來使覆蓋在矽上的表面積 縮小是可預期的，傳統的靜電放電保護元件通常連接在1/〇 墊與內部電路之間，會佔用晶圓一些表面積，因此會使1C 的積集度受到限制。舉例來說，對一個次微米CMOS製程， 佔據15μιηχ116μηι(1，740μιη2的矽面積)來說，一般的靜電放 電保護電路元件(ΝΡΝ電晶體）具有一個約爲3.6-3.9KV的 靜電放電臨限，理論上最理想的是設計不在晶圓上佔據任 何額外的區域的一種靜電放電保護電路元件，藉以增加1C 的積集度。 第1圖繪示爲一種傳統的靜電放電保護電路。參照第 1圖，經過焊墊150輸入的靜電放電電流，會透過一個PMOS 電晶體放電，而導到一個接地電壓Vss，因此可以保護內 部的電路180,因爲傳統靜電放電保護電路元件中的NM0S 電晶體160與PM0S電晶體170係位在焊墊的外部，因此 會佔據晶圓較多的表面。 有鑑於此，本發明提供一種靜電放電保護電路元件， 係放置於半導體元件的焊墊下方，並提供其製作方法，以 符合空間利用的需求，藉以有效的增加1C的積集度。本 發明提供之靜電放電保護電路元件不會佔用晶圓任何額外 的表面區域，因此可同時提高積體電路的積集度。 根據一較佳實施例，本發明提供一種靜電放電保護電 路元件的結構，以及其製作方法。首先，提供一個基底且 有一個P井與一個N井形成在基底中，此P井與N井有 一個井的定義界面，在基底中選定一個跨越此界面的預定 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ---------------裝—— (請先閱讀背面之注意事項再填寫本頁) 訂·· A7 B7 經濟部智慧財產局員工消費合作社印製 565928 679〇twf. doc/006 i、發明說明（多） 區域（焊墊接觸窗），將第一淺溝渠隔離結構、第二淺溝渠 隔離結構與第三淺溝渠隔離結構形成在基底的此焊墊接觸 窗中，其中第一淺溝渠隔離結構位於界面上，第二淺溝渠 隔離結構位於爲P井中’而第三淺溝渠隔離結構位於N井 中，第二淺溝渠隔離結構圍繞一個第一內部區域，與一個 第一外部區域分隔開，而第三淺溝渠隔離結構圍繞一個第 二內部區域，與一個第二外部區域分隔開。在P井的第 一內部區域與N井的第二內部區域中分別形成一個η型摻 雜區，而在Ρ井的第一外部區域與Ν井的第二外部區域中 分別形成一個第一 Ρ型摻雜區，並在Ρ井的第一內部區域 與Ν井的第二外部區域中分別形成一第二ρ型摻雜區。Ρ 井的第二Ρ型摻雜區係形成在一個η型摻雜區的下方，與 Ρ井中的η型摻雜區作電性接觸，而形成一個基納二極體， Ν井的第二ρ型摻雜區係形成在η型摻雜區下方，與Ν井 的η型摻雜區作電性接觸，而形成另一個基納二極體。 Ν井中的η型摻雜區與電源VDD電性連接，Ρ井的η型 摻雜區與Ν井的ρ型摻雜區係電性連接到焊墊上，而Ρ井 的Ρ型摻雜區則連接一個接地電壓Vss。 由上面的敘述可以了解本發明可以利用包括使用位於 焊墊下方的基納二極體之靜電放電保護電路元件，來保護 半導體的內部電路不受靜電放電的影響，因爲基納二極體 是位於焊墊下方，此靜電放電保護電路元件不會佔晶圓額 外的表面區域，因此可以同時提高積體電路的積集度。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 5 (請先閱讀背面之注意事項再填寫本頁)La · .line is the consumer cooperation of Intellectual Property Bureau Du printed 565928 67 90twf .doc / 0 06 jsj B7 V. Description of the invention (1) Increase the accumulation degree of 1C and reduce the size to cover the silicon The reduction in surface area is to be expected. Traditional electrostatic discharge protection components are usually connected between the 1/0 pad and the internal circuit, which will occupy some surface area of the wafer, so the 1C accumulation degree will be limited. For example, for a sub-micron CMOS process that occupies 15 μm × 116 μm (1,740 μm 2 silicon area), the general electrostatic discharge protection circuit element (NPN transistor) has an electrostatic discharge threshold of about 3.6-3.9KV. Theoretically the most ideal is to design an electrostatic discharge protection circuit element that does not occupy any extra area on the wafer, thereby increasing the 1C accumulation. Figure 1 shows a conventional electrostatic discharge protection circuit. Referring to Figure 1, the electrostatic discharge current input through the pad 150 will be discharged through a PMOS transistor, and will lead to a ground voltage Vss, so it can protect the internal circuit 180, because the NM0S electricity in the traditional electrostatic discharge protection circuit components The crystal 160 and the PMOS transistor 170 are located on the outside of the bonding pad, and therefore occupy more surface of the wafer. In view of this, the present invention provides an electrostatic discharge protection circuit element, which is placed under a pad of a semiconductor element and provides a manufacturing method thereof to meet the requirements of space utilization, thereby effectively increasing the accumulation degree of 1C. The electrostatic discharge protection circuit element provided by the present invention does not occupy any additional surface area of the wafer, and therefore, the accumulation degree of the integrated circuit can be improved at the same time. According to a preferred embodiment, the present invention provides a structure of an electrostatic discharge protection circuit element and a manufacturing method thereof. First, a base is provided and a P well and an N well are formed in the base. The P well and the N well have a well-defined interface. A predetermined spanning this interface is selected in the base. 4 This paper standard is applicable to Chinese national standards. (CNS) A4 specification (210 X 297 mm) --------------- Packing-(Please read the notes on the back before filling this page) Order ·· A7 B7 Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative 565928 679twf.doc / 006 i. Description of the invention (multiple) area (pad contact window), the first shallow trench isolation structure, the second shallow trench isolation structure and the third shallow trench An isolation structure is formed in this pad contact window of the base, wherein the first shallow trench isolation structure is located on the interface, the second shallow trench isolation structure is located in well P ', the third shallow trench isolation structure is located in well N, and the second shallow trench The isolation structure surrounds a first inner region and is separated from a first outer region, and the third shallow trench isolation structure surrounds a second inner region and is separated from a second outer region. An n-type doped region is formed in the first inner region of the P well and the second inner region of the N well, respectively, and a first P is formed in the first outer region of the P well and the second outer region of the N well. And a second p-type doped region is formed in the first inner region of the P-well and the second outer region of the N-well, respectively. The second P-type doped region of the P-well is formed below an n-type doped region, and is in electrical contact with the n-type doped region in the P-well, thereby forming a kina diode, and the second of the N-well The p-type doped region is formed below the n-type doped region, and is in electrical contact with the n-type doped region of the N-well, thereby forming another quina diode. The n-type doped region in the N well is electrically connected to the power source VDD, the n-type doped region in the P well and the p-type doped region in the N well are electrically connected to the pad, and the P-type doped region in the P well is Connect a ground voltage Vss. It can be understood from the above description that the present invention can use an electrostatic discharge protection circuit element including a kina diode located under a solder pad to protect an internal circuit of a semiconductor from an electrostatic discharge because the kina diode is located Below the bonding pad, the electrostatic discharge protection circuit component will not occupy the extra surface area of the wafer, so the integration degree of the integrated circuit can be improved at the same time. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, 5 (Please read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 瘦齊郎智慧財產局員工消費合作社印製 565928 6790twf.doc/006 A7 B7 五、發明說明（Lf ) 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 下： 圖式之簡單說明： 第1圖繪示爲習知的一種靜電放電保護電路之電路 圖； 第2圖繪示爲依照本發明的一種靜電放電保護電路之 電路圖； 第3A至3D圖繪示爲根據本發明一較佳實施例的靜電 放電保護電路結構的製作流程剖面圖，係沿著第4圖的I-I 線之切面繪示；以及 第4圖繪示爲依照本發明一較佳實施例的一種靜電放 電保護電路元件結構的上視圖。 圖示標記說明： 150, 350 焊墊 160 NMOS 170 PMOS 180,380 內部電路 Vss 接地電壓 VDD 電源電壓 360, 370 基納二極體300 基底 302 P 井 304 N 井 306 界面 308 焊墊接觸窗 310, 320, 330 淺溝渠隔離結構 324, 334 η型摻雜區 322, 322a, 332, 332a p 型摻雜區 321, 331 外部區域 323, 333 內部區每 實施例 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裝--- (請先閱讀背面之注意事項再填寫本頁) · 線· 565928 67 90twf. doc/006 A7 B7 經齊部智慧財產局員工消費合作社印製 五、發明說明（f ) 以下將參考圖示詳細說明本發明之較佳實施例’在圖 示與敘述中將會使用相同的標號來代表相同或相似的部 分。 第2圖繪示爲依照本發明的一種靜電放電保護電路之 電路圖。參照第2圖，透過一個導到接地電壓Vss的基納 二極體370，釋放由焊墊350輸入的靜電放電電流’藉此 保護內部電路380，基納二極體360與370係位於焊墊下 方，因此此靜電放電保護電路元件不會佔據晶圓額外的區 域，且藉此可以提高半導體元件的積集度。 第4圖繪示爲依照本發明一較佳實施例的一種靜電放 電保護電路元件結構的上視圖。 在第4圖中，靜電放電保護電路元件的上視圖顯示在 半導體基底300中有一個P井302與一個N井304，舉例 來說，P井302可以利用植入低濃度的摻質，像是硼，來 形成，而N井304可以利用植入低濃度的摻質，像是磷， 來形成。P井302與N井304有一個井的定義界面306 ; 在基底300中選定一個跨越此界面306的預定區域308(焊 墊接觸窗），將第一淺溝渠隔離結構310、第二淺溝渠隔離 結構320與第三淺溝渠隔離結構330形成在基底300的此 焊墊接觸窗308中。其中第一淺溝渠隔離結構310位於P 井302與N井304之間的界面306上，第二淺溝渠隔離結 構320位於爲P井302中’而第三淺溝渠隔離結構位於N 井304中。第二淺溝渠隔離結構320圍繞一個第一內部區 域324，將其與一個第一外部區域322分隔開，而第三淺 7 本紙張尺度適用中國國家標準（CNS)A4規袼（210 x 297公釐） ------------- · I I I (請先閱讀背面之注意事項再填寫本頁) 訂---------線 565928 67 90twf. doc/0 06 A7 B7 ^齊grfcp曰慧材轰局員X消費合作fi印裂 五、發明說明（6) 溝渠隔離結構330圍繞一個第二內部區域334將其，與一 個第二外部區域分隔開332。在區域324與334中植入η 型摻質以形成η型摻雜區，η型摻雜區域324與334比如 利用植入濃度高於Ν井304的磷來形成；在區域322與332 中植入Ρ型摻質以形成第一 ρ型摻雜區，第一 Ρ型摻雜區 322與332比如利用植入濃度高於Ρ井302的硼來達成， 並在η型摻雜區324與334下方分別利用高能量的ρ型摻 質來形成第二Ρ型摻雜區322a與332a，第二ρ型摻雜區322a 與332a比如用濃度稍低於第一 ρ型摻雜區之磷來植入形 成，其中第二ρ型摻雜區322a係形成在η型摻雜區324下 方，並與Ρ井302中的η型摻雜區324作電性接觸，而在 Ρ井302中形成一個第二基納二極體370，而第二ρ型摻 雜區332a係形成在η型摻雜區334下方，與Ν井304的η 型慘雜區334作電性接觸’而在Ν井304中形成一^個第一k 基納二極體360。 第3A至3D圖繪示爲根據本發明一較佳實施例的靜電 放電保護電路結構的製作流程剖面圖，係沿著第4圖的I-I 線之切面繪示圖。 在第3A圖中，製程步驟包括提供一個半導體基底3〇〇， 在半導體基底300中形成一個P井302與一個N井304，P 井302與N井304之間存在有一個井的定義界面306，P 井302比如利用植入像是硼的低濃度ρ型摻質來形成，而 N井304則比如利用植入像是磷的低濃度η型摻質來形成。 在弟3Β圖中’在基底300中選擇一個預定區域308(如 8 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------裳--- (請先閱讀背面之注意事項再填寫本頁) · •線· 經濟部智慧財產局員工消費合作社印製 565928 6790twf.doc/006 pj B7 五、發明說明（Ί) 第4圖中繪示的焊墊接觸窗308)橫跨過界面306，此焊墊 接觸窗308最後會對準形成於半導體元件的I/O焊墊下方。 在基底300的焊墊接觸窗308中形成一第一淺溝渠隔離結 構310、第二淺溝渠隔離結構320與第三淺溝渠隔離結構 330，其中第一淺溝渠隔離結構310係跨越Ρ井302與Ν 井304之間的界面306，第二淺溝渠隔離結構320位於Ρ 井302中，而第三淺溝渠隔離結構330則位於Ν井304中。 第二淺溝渠隔離結構320圍繞著一個第一內部區域323, 將其與一個第一外部區域321分隔開，而第三淺溝渠隔離 結構330則圍繞著一個第二內部區域333，將其與一個第 二外部區域331分隔開。由於第3Β圖中所示的結構係沿 著第4圖I-Ι線段呈現的一個剖面圖，因此在第3Β圖中 看到的Ρ井302中的兩個第二淺溝渠隔離結構320其實是 繪示於第4圖的單一淺溝渠320，同樣的，在Ν井304中 的第三淺溝渠隔離結構結構330也是一個單一淺溝渠330， 如第4圖所示。 在第3C圖中，將η型摻質植入到區域323與333中， 以形成η型摻雜區324與334，形成方法比如將濃度高於 Ν井304的磷植入第一內部區域區域323與第二內部區域 333中；將Ρ型摻質植入到第一外部區域321與第二外部 區域331中，以形成第一 ρ型摻雜區322與332，形成方 法比如將濃度高於Ρ井302的硼植入到區域322與332中。 用高能量在η型摻雜區324與334的下方植入ρ型摻質， 已分別形成一個第二ρ型摻雜區322a與332a，其形成方 9 ^本紙張尺度適用中國國家標準(CNS)A4規格（210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) —裝--------訂------ ·線 0. 565928 6790twf.doc/006 A7 ___B7 _ 五、發明說明（ί ) 式比如將濃度稍低於第一 P型摻雜區322與332的硼植入， 其中第二p型摻雜區332a係形成在n型摻雜區334下方， 與Ν井304中的η型摻雜區334作電性連接，以在Ν井304 中形成一個第一基納二極體360，而第二ρ型摻雜區322a 係形成在η型區域324下方，與P井302中的η型摻雜區 324作電性連接，以在Ρ井302中形成一個第二基納二極 體370。第3 Β圖是第4圖的剖面圖，因此顯示在第3Β圖 中的Ρ井302中的ρ型摻雜區322事實上是一個圍繞在η 型摻雜區324周圍的單一個第一 ρ型摻雜區322，由第二 淺溝渠隔離結構320將其分隔開，如第4圖所示；而同樣 的在Ν井304中的ρ型摻雜區332事實上是一個圍繞在η 型摻雜區334周圍的單一個第一 ρ型摻雜區332，由淺溝 渠隔離結構330將其分隔開，如第4圖所示。 在第3D圖中，Ν井304中的η型摻雜區域334係電性 連接到一個電源電壓VDD，在Ρ井302中的η型摻雜區324 與Ν井304中的ρ型摻雜區332係電性連接到焊墊上，而 在Ρ井302中的ρ型摻雜區322則電性連接到一個接地電 壓 Vss。 在一個靜電放電的操作中，由焊墊350輸入的靜電放 電電流會藉由接地的基納二極體370釋放掉，因此可以保 護內部電路380，因爲基納二極體360與370均位於焊墊 下方，因此此靜電放電保護元件不會佔用晶圓任何額外的 空間，藉此得以增加積體電路的積集度。 總而言之，本發明提供了一種位在焊墊下方的靜電放 10 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝 --線· 竣齊邨智慧財產局員工消費合作社印製 565928 6790twf.doc/006 A7 _B7_ 五、發明說明（1 ) 電保護電路，不會佔用晶圓任何額外的空間，藉此得以增 加積體電路的積集度。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (請先閱讀背面之注意事項再填寫本頁) 裝 --線- 經齊郎智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm). Printed by Shouqilang Intellectual Property Bureau, Consumer Cooperatives. 565928 6790twf.doc / 006 A7 B7 5. Description of Invention (Lf) The preferred embodiment and the accompanying drawings are described in detail as follows: Brief description of the drawings: FIG. 1 shows a conventional circuit diagram of an electrostatic discharge protection circuit; FIG. 2 shows a circuit diagram according to the present invention. Circuit diagrams of the electrostatic discharge protection circuit; FIGS. 3A to 3D are cross-sectional views showing a manufacturing process of the structure of the electrostatic discharge protection circuit according to a preferred embodiment of the present invention, and are shown along the line II in FIG. 4; and FIG. 4 is a top view of a structure of an electrostatic discharge protection circuit element according to a preferred embodiment of the present invention. Description of icons: 150, 350 pads 160 NMOS 170 PMOS 180, 380 internal circuit Vss ground voltage VDD power voltage 360, 370 kina diode 300 base 302 P well 304 N well 306 interface 308 pad contact window 310, 320, 330 Shallow trench isolation structure 324, 334 n-type doped regions 322, 322a, 332, 332a p-type doped regions 321, 331 Outer regions 323, 333 Inner regions per Example 6 This paper scale applies to Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) -------------- Packing --- (Please read the precautions on the back before filling this page) · Line · 565928 67 90twf. Doc / 006 A7 B7 Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of Qibu V. Invention Description (f) The preferred embodiment of the present invention will be described in detail below with reference to the drawings.' The same reference numerals will be used in the illustrations and descriptions to represent the same or Similar parts. Fig. 2 is a circuit diagram of an electrostatic discharge protection circuit according to the present invention. Referring to Fig. 2, through a kinah diode 370 leading to the ground voltage Vss, the electrostatic discharge current inputted by the pad 350 is released to protect the internal circuit 380. The kinah diodes 360 and 370 are located on the pad Underneath, therefore, the electrostatic discharge protection circuit element does not occupy an extra area of the wafer, and thereby the accumulation degree of the semiconductor element can be improved. FIG. 4 is a top view of a structure of an electrostatic discharge protection circuit element according to a preferred embodiment of the present invention. In Figure 4, the top view of the ESD protection circuit element shows that there is a P well 302 and an N well 304 in the semiconductor substrate 300. For example, the P well 302 can be implanted with a low concentration of dopants, such as Boron can be formed, and N well 304 can be formed by implanting a low concentration of a dopant such as phosphorus. P well 302 and N well 304 have a well defining interface 306; a predetermined area 308 (pad contact window) spanning this interface 306 is selected in the substrate 300 to isolate the first shallow trench isolation structure 310 and the second shallow trench The structure 320 and the third shallow trench isolation structure 330 are formed in this pad contact window 308 of the substrate 300. The first shallow trench isolation structure 310 is located on the interface 306 between the P well 302 and the N well 304, the second shallow trench isolation structure 320 is located in the P well 302 ', and the third shallow trench isolation structure is located in the N well 304. The second shallow trench isolation structure 320 surrounds a first inner region 324, separating it from a first outer region 322, and the third shallower 7 This paper size applies Chinese National Standard (CNS) A4 regulations (210 x 297) Mm) ------------- · III (Please read the notes on the back before filling this page) Order --------- Line 565928 67 90twf. Doc / 0 06 A7 B7 ^ Qi grfcp said Hui Xia Bo Xuan X consumer cooperation fi printing 5. Description of the invention (6) The trench isolation structure 330 surrounds a second internal area 334 and separates it 332 from a second external area. N-type dopants are implanted in regions 324 and 334 to form n-type doped regions, n-type doped regions 324 and 334 are formed, for example, by implanting phosphorus with a higher concentration than N well 304; and implanted in regions 322 and 332. A P-type dopant is introduced to form a first p-type doped region. The first P-type doped regions 322 and 332 are achieved, for example, by implanting boron with a higher concentration than the P well 302, and in the n-type doped regions 324 and 334. The second p-type doped regions 322a and 332a are formed below using high-energy p-type dopants, respectively. The second p-type doped regions 322a and 332a are planted with phosphorous that is slightly lower in concentration than the first p-type doped region, respectively. The second p-type doped region 322a is formed below the n-type doped region 324, and is in electrical contact with the n-type doped region 324 in the P-well 302, and a first Two-kina diode 370, and the second p-type doped region 332a is formed under the n-type doped region 334, and is in electrical contact with the n-type miscellaneous region 334 of the N-well 304, and in the N-well 304 A first k-kina diode 360 is formed. 3A to 3D are cross-sectional views showing a manufacturing process of an electrostatic discharge protection circuit structure according to a preferred embodiment of the present invention, and are drawn along the line I-I in FIG. 4. In FIG. 3A, the process steps include providing a semiconductor substrate 300, and forming a P well 302 and an N well 304 in the semiconductor substrate 300. There is a well definition interface 306 between the P well 302 and the N well 304. The P well 302 is formed using, for example, a low-concentration p-type dopant implanted like boron, and the N well 304 is formed using, for example, a low-concentration n-type dopant implanted like phosphorus. In the 3B picture, 'select a predetermined area 308 in the base 300 (such as 8 paper sizes applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- -Shang --- (Please read the notes on the back before filling out this page) · • Line · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 565928 6790twf.doc / 006 pj B7 V. Description of the Invention (Ί) Figure 4 The pad contact window 308 shown in the figure crosses the interface 306, and the pad contact window 308 is finally aligned under the I / O pad of the semiconductor device. A first shallow trench isolation structure 310, a second shallow trench isolation structure 320, and a third shallow trench isolation structure 330 are formed in the pad contact window 308 of the substrate 300. The first shallow trench isolation structure 310 crosses the P-well 302 and The interface 306 between the N wells 304, the second shallow trench isolation structure 320 is located in the P well 302, and the third shallow trench isolation structure 330 is located in the N well 304. The second shallow trench isolation structure 320 surrounds a first inner region 323, separating it from a first outer region 321, and the third shallow trench isolation structure 330 surrounds a second inner region 333, separating it from A second outer region 331 is separated. Because the structure shown in FIG. 3B is a cross-sectional view taken along the line 1-1 of FIG. 4, the two second shallow trench isolation structures 320 in the well P 302 seen in FIG. 3B are actually A single shallow trench 320 is shown in FIG. 4. Similarly, the third shallow trench isolation structure 330 in the N well 304 is also a single shallow trench 330, as shown in FIG. 4. In FIG. 3C, n-type dopants are implanted into the regions 323 and 333 to form n-type doped regions 324 and 334. The forming method is, for example, implanting phosphorus with a concentration higher than that of the N well 304 into the first inner region region. 323 and the second inner region 333; P-type dopants are implanted into the first outer region 321 and the second outer region 331 to form the first p-type doped regions 322 and 332. Boron of the P-well 302 is implanted into the regions 322 and 332. A high-energy implantation of p-type dopants under the n-type doped regions 324 and 334 has formed a second p-type doped region 322a and 332a, respectively. ) A4 size (210 x 297 mm) (Please read the precautions on the back before filling out this page) —install -------- order ------ · line 0 565928 6790twf.doc / 006 A7 ___B7 _ 5. Explanation of the invention (ί) Formula such as implanting boron with a slightly lower concentration than the first P-type doped regions 322 and 332, wherein the second p-type doped region 332a is formed in the n-type doped region 334 Below, it is electrically connected to the n-type doped region 334 in the N-well 304 to form a first kina diode 360 in the N-well 304, and the second p-type doped region 322a is formed in the n-type Below the region 324, an electrical connection is made with the n-type doped region 324 in the P-well 302 to form a second kina diode 370 in the P-well 302. Figure 3B is a sectional view of Figure 4, so the p-type doped region 322 shown in P well 302 in Figure 3B is actually a single first p around the n-type doped region 324 Type doped region 322, which is separated by a second shallow trench isolation structure 320, as shown in FIG. 4; and the same p-type doped region 332 in the N-well 304 is actually a n-type doped region. A single first p-type doped region 332 around the doped region 334 is separated by the shallow trench isolation structure 330 as shown in FIG. 4. In FIG. 3D, the n-type doped region 334 in the N-well 304 is electrically connected to a power supply voltage VDD, the n-type doped region 324 in the P-well 302 and the p-type doped region in the N-well 304. The 332 series is electrically connected to the bonding pad, and the p-type doped region 322 in the P-well 302 is electrically connected to a ground voltage Vss. In an electrostatic discharge operation, the electrostatic discharge current inputted by the bonding pad 350 will be released through the grounded Kina diode 370, so the internal circuit 380 can be protected because the Kina diodes 360 and 370 are located in the solder Under the pad, so this electrostatic discharge protection element will not occupy any extra space on the wafer, thereby increasing the accumulation of the integrated circuit. All in all, the present invention provides an electrostatic discharge 10 under the solder pad. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). -Line · Printed by the Consumer Cooperative of the Intellectual Property Bureau of Junqi Village, printed 565928 6790twf.doc / 006 A7 _B7_ V. Description of the invention (1) The electrical protection circuit will not take up any extra space on the wafer, thereby increasing the accumulation. The degree of accumulation of the circuit. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling out this page.) Packing-Line-Printed by the Consumers' Cooperative of Qilang Intellectual Property Bureau This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)