TW201308301A - Display driver integrated circuit having zigzag spreading output driving scheme, display device including the same and method of driving the display device - Google Patents

Abstract

In one embodiment, the method includes storing data corresponding to each of the N data lines in response to a control signal; adjusting output timings of data corresponding to the respective N data lines in a zigzag spreading pattern; and outputting output signals based on the data to the N data lines according to the adjusted output timings.

Description

Display driver integrated circuit with sawtooth extended output drive architecture, display device therewith and method of driving the same

The present invention is directed to a display device and, more particularly, to a display driver integrated circuit (IC) for driving a plurality of data lines, a method thereof, and/or a display device including the same.

The present application claims priority to Korean Patent Application No. 10-2011-0051674, filed on May 30, 2011, which is hereby incorporated by reference. The way to incorporate.

In place of heavy and large cathode ray tube (CRT) display devices, flat display devices such as organic electroluminescent display (OLED) devices, plasma display panel (PDP) devices, and liquid crystal display (LCD) devices have received attention.

The PDP device uses plasma generated by gas discharge to display text or images. OLED devices use electroluminescence of a particular organic material or polymer to display text or images. The LCD device displays an image by applying an electric field to a liquid crystal layer between the two substrates and controls the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer.

Such flat display devices include a panel that displays an image. The panel includes a plurality of pixels. The pixels are driven according to grayscale data provided by a display driver IC (DDI) so that the panel displays an image.

Conventionally, a DDI includes a gray scale voltage generating circuit that generates a plurality of (eg, 64, 128, or 256) gray scale voltages and is configured to generate gray scale voltages from gray scale voltage generating circuits. Transfer to a channel drive The channel driver selects one of the gray scale voltages according to the digital image data and outputs the selected gray scale voltage to a corresponding data line. Such conventional DDIs have a peak current that occurs when an output current is rapidly increased by the output timing of a data output driver because the data signals are simultaneously output.

High peak currents cause electromagnetic interference (EMI). The EMI increases as the size of a display device increases, due to the increased number of output channels and the load of a data driver. The high peak current also causes an increase in power consumption and can affect a display panel, causing a data driver to malfunction.

In accordance with certain embodiments of the inventive concept, a method of driving N data lines in a display device is provided, wherein N is 2 or greater than one integer. The method includes: storing data corresponding to each of the N data lines in response to a control signal; and adjusting an output timing of data corresponding to the respective N data lines according to a sawtooth extension pattern; Output signals based on the data are respectively output to the N data lines according to the adjusted output timings.

Adjusting the output timings may include: causing an output timing of one of the first one of the N data lines to lag behind one of the kth data lines of the N data lines; and causing the N data One of the second one of the lines has an output timing that is ahead of the output timing of the kth data line.

Here, a difference between one of the N data lines and the latest output timing may be within a desired (or alternatively, a predetermined) time period.

The operation of adjusting the output timings may further include repeating the change in the output timing to adjust the output timings of the N data lines in accordance with the sawtooth pattern.

According to other embodiments of the inventive concept, a display driver integrated circuit is provided, comprising: a data storage block configured to store data corresponding to each of N data lines in a display device Wherein N is 2 or an integer greater than 2; an extended adjustment block configured to adjust an output timing of data corresponding to the respective N data lines in a zigzag extension; and an output mode a set configured to output an output signal based on the data to the N data lines in accordance with the adjusted output timing.

The data storage block can include N registers to receive and store the data in response to a control signal. The extension adjustment block can include an array of extended delay cells configured to adjust output timing of the registers in accordance with the sawtooth pattern.

According to another embodiment of the present invention, a display device includes: a display panel including N data lines, a plurality of gate lines, and the N data lines and the respective gate lines a plurality of pixels, wherein N is 2 or greater than 2 integer; an output driver configured to drive the N data lines; a gate driver configured to gate the plurality of gates And a control circuit configured to control the output driver and the gate driver.

The output driver can include: a data storage block configured to store data corresponding to each of the N data lines; an extended adjustment block configured to extend in a zigzag pattern Sample adjustment corresponds to the respective N An output timing of the data of the data line; and an output module configured to output an output signal based on the data to the N data lines according to the adjusted output timing.

According to another embodiment of the present invention, a display device includes: a display panel including N data lines, a plurality of gate lines, and the N data lines and the respective gate lines. a plurality of pixels, wherein N is 2 or greater than 2 integer; an output driver configured to drive the N data lines; a gate driver configured to gate the plurality of gates And a control circuit configured to control the output driver and the gate driver.

The output driver includes: a data storage block configured to receive and store data corresponding to each of the N data lines; an extended adjustment block configured to extend in a zigzag manner The type adjustment corresponds to an output timing of the data of the respective N data lines; and an output module configured to output an output signal based on the data to the N according to the adjusted output timings Information line.

The display device can be a liquid crystal display (LCD) device or an organic light emitting diode (OLED) device.

According to another embodiment of the present invention, a display device includes: a display panel including N data lines, a plurality of X scan lines, a plurality of Y scan lines, and connected to the N data lines, and the like a plurality of pixels between the respective X scan lines and the respective Y scan lines, wherein N is 2 or greater than 2 integer; an output driver configured to drive the N data lines; an X scan a drive configured to scan the plurality of X-scans a Y scan driver configured to scan the plurality of Y scan lines; and a control circuit configured to control the output driver, the X scan driver, and the Y scan driver.

The output driver includes: a data storage block configured to store data corresponding to each of the N data lines; and an extended adjustment block configured to extend in a zigzag pattern Adjusting an output timing of data corresponding to the respective N data lines; and an output module configured to output an output signal based on the data corresponding to the N data lines according to the adjusted output timings .

The display device can be a plasma display device.

According to still further embodiments of the inventive concept, an output driver includes: a data storage block configured to store data from a data line in the output driver; and an extended adjustment block grouped The state adjusts the output timing of the data corresponding to the data lines in a zigzag pattern.

The data storage block according to this embodiment may include one of a plurality of scratchpad registers.

The zigzag pattern of this embodiment can be defined by a lag time L*td and a lead time M*td, where L and M are natural numbers, L-M is greater than or equal to 1 and td is a unit time interval.

The extended block can be an extended delay cell array and the extended delay cell array can include a unit delay element in parallel with the fuse, and the fuses can be initially in a disconnected state and configured to be applied by A current is connected. The extended delay unit array may further comprise a single parallel with the switch Bit delay element.

The above features and other features and advantages of the present invention will become more apparent from the embodiments of the invention.

The inventive concept will now be described more fully hereinafter with reference to the accompanying claims The inventive concept may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, the embodiments are provided so that this disclosure will be thorough, and will be In the drawings, the size and relative size of layers and regions may be exaggerated for clarity. Throughout the specification, like numbers refer to like elements.

It will be understood that when an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or the intervening element can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, the intervening element is absent. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items, and may be abbreviated as "/".

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are only used to distinguish one element from another. For example, a first signal may be referred to as a second signal, and similarly, a second signal may be referred to as a first signal, without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments. It is not intended to limit the inventive concept. As used herein, the singular forms " It will be further understood that the terms "including" or "comprising", when used in the specification, are intended to mean the presence of the features, regions, integers, steps, operations, components and/or components, but do not exclude one or more other The presence or addition of features, regions, integers, steps, operations, components, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning It will be further understood that the terms (such as those defined in commonly used dictionaries) should be interpreted as having the same meaning as in the context of the related art and/or application, unless explicitly defined herein. One meaning, and will not be explained by an idealized or overly formalized meaning.

1A is a block diagram of a display device 10 in accordance with some embodiments of the inventive concept. 1B is a circuit diagram of a pixel when the display panel 11 is a thin film transistor liquid crystal display (TFT-LCD) panel as illustrated in FIG. 1A. 1C is a circuit diagram of a pixel when the display panel 11 illustrated in FIG. 1A is an organic light emitting diode (OLED) panel.

Referring to FIG. 1A, the display device 10 includes a display panel 11, a control circuit 14, a gate driver 13, and a source driver 12.

The display panel 11 includes: a plurality of source lines S ₁ to S _N , wherein "N" is a natural number; a plurality of gate lines G ₁ to G _g , wherein "g" is a natural number and g = N or g ≠N; and a plurality of pixels including a unit pixel unit. Each of the pixels is connected between one of the source lines S ₁ to S _N and one of the gate lines G ₁ to G _g .

The display panel 11 can be a flat display panel such as a TFT-LCD panel, a plasma display panel (PDP), a light emitting diode (LED) panel, or an OLED panel, but the inventive concept is not limited to the current example.

The unit pixel unit 1 has the structure illustrated in FIG. 1B when the display panel 11 is a TFT-LCD panel and has the structure illustrated in FIG. 1C when the display panel 11 is an OLED panel, but the inventive concept is not limited thereto Current embodiment.

The control circuit 14 generates a plurality of control signals including a first control signal CON1 and a second control signal CON2. For example, the control circuit 14 can generate the first control signal CON1, the second control signal CON2, and the image data DATA based on a horizontal synchronization signal and a vertical synchronization signal.

The gate driver 13 in response to a first control signal CON1 sequentially driving the gate lines G ₁ to _{G g.} A first control signal CON1 may be one of lines ₁ to _{G g} indicator indicating start scanning the gate line G.

The source driver 12 drives the source lines S ₁ to S _N in response to the second control signal CON2 and the digital image data DATA output from the control circuit 14. The source lines S ₁ to S _{N are} also referred to as data lines. One of the drives used to drive a single data line is called a channel driver.

1D is a block diagram of a display device 20 in accordance with some embodiments of the inventive concept. Display device 20 can be a plasma display device.

Referring to FIG. 1D, the display device 20 includes a plasma display panel (PDP) 21, a control circuit 25, an X driver 22, a Y driver 23, and a W driver (an address driver or a data driver) 24. The PDP 21 may include a plurality of data lines W1 to W _w , a plurality of X scan lines (or X electrodes) X1 to X _x , a plurality of Y scan lines (or Y electrodes) Y1 to Y _{y ,} and a plurality of pixels. The plurality of pixels are connected between the N data lines, the respective X scan lines, and the respective Y scan lines. N is 2 or an integer greater than 2.

The PDP 21 discharges light by controlling a voltage applied between a vertical electrode and a horizontal electrode forming one of the cells of one pixel and adjusts the amount of discharged light by changing the length of the discharge time in the cell. The PDP 21 is erased by one of writing a pulse for inputting a digital image signal, scanning a scan pulse, maintaining a sustain pulse for one discharge, and stopping one of the discharges of a cell. The vertical and horizontal electrodes applied to each of the cells drive a unit in the form of a matrix to display an entire image. In other words, a drive pulse from one of the X drivers 22 is applied to a plurality of X electrodes, that is, scan electrodes X1 to _Xx ; data from the W driver 24 is applied to a plurality of data lines (or address electrodes) W1 to W _W; 23 and one common voltage is applied from the Y driver is connected to the Y-electrodes Y1 to the Y _y.

The control circuit 25 generates a plurality of control signals including a first control signal CON1, a second control signal CON2, and a third control signal CON3. For example, the control circuit 25 can generate the first control signal CON1, the second control signal CON2, the third control signal CON3, and the data DATA based on a horizontal synchronization signal and a vertical synchronization signal. Drivers 22, 24, and 23 are driven by first to third control signals CON1, CON2, and CON3, respectively. The field is divided into a plurality of (for example, eight) subfields. These subfields Each of them is divided into a reset period, an address period, and a sustain period. At this time, three discharges occur during the reset period, that is, a full write discharge, a full sustain discharge, and a complete erase discharge.

2 is a block diagram of an output driver 200 in accordance with some embodiments of the inventive concept.

Referring to FIG. 2, the output driver 200 can include a data storage block 210, an extension adjustment block implemented as an extended delay unit array 100, and an output module 220. The data storage block 210 is a functional block that receives and stores data corresponding to each of N (N series 2 or greater than 2 integer) data lines O ₁ to O _N of a display device and It can be implemented by an array of registers including one of a plurality of registers. The extended delay cell array 100 is an exemplary embodiment of an extended adjustment block. A block-based extension to adjust a functional block, which corresponds to the output timing information to the data line O ₁ O _N of extension by a zigzag pattern adjusted. The output module 220 outputs one of the data-based output signals to each of the data lines O ₁ to O _N according to the adjusted output timing.

The output driver 200 can correspond to one of the source drivers 12 illustrated in FIG. 1A or the W driver 24 illustrated in FIG. 1D and can be implemented as an integrated circuit (IC). 3 is a block diagram showing a register array 210 and an extended delay cell array 100, which are illustrated in detail in FIG.

The register array 210 receives the data D ₁ to D _N and stores them in the array register <1> to the register <N> in response to a control signal CON generated by the control circuit 25, respectively. For example, the data D _K corresponding to the kth data line O _K among the N data lines O ₁ to O _{N is} stored in the Kth array register <K>. Here, N is 2 or an integer greater than 2 and K is an integer from 1 to N.

The extended delay cell array 100 is connected to all output lines of the register array 210 and adjusts the output timing of the data stored in the array register <1> to the register <N> in a zigzag pattern. Referring to FIG. 3, the extended delay cell array 100 includes a plurality of delay cells 111, for example, as many delay cells as the number of channels. The delay unit 111 is connected to the data lines O ₁ to O _N and adjusts the output timing thereof. Each of the delay units 111 may include at least one buffer, an inverter, a transistor, and/or a switching element, but the inventive concept is not limited thereto.

4 is a diagram showing one of the examples of one of the delay units 111 illustrated in FIG. The delay unit 111 can be embodied by connecting at least one unit delay element UD having a desired (or another selection, a predetermined) delay time in series with each other. At this time, the output timing of a data line can be adjusted by adjusting the number of unit delay elements UD included in the delay unit 111. The number of unit delay elements UD included in the delay unit 111 may be predetermined.

The operation of the extended delay cell array 100 will be described in detail later with reference to FIGS. 4 through 8D.

The output module 220 outputs the data stored in each array to a corresponding data line according to the adjusted output timing. The output module 220 can include a latch circuit 221, a bit shifter 222, and an output buffer 223.

The latch circuit 221 latches the output signals of the data lines O ₁ to O _N and outputs them to the level shifter 222. The level shifter 222 shifts the level of the latched output signal. The output buffer 223 outputs the shifted output signals to the data lines O ₁ to O _{N , respectively} .

Each of the output signals of the output module 220 may be a level signal corresponding to one of the data lines O ₁ to O _N among the plurality of level signals. In other words, each output signal corresponds to a brightness level (ie, one of the gray levels required for image display) and may correspond to a desired one for displaying one of the entire images (or another selection system, A predetermined time or voltage is divided into one of a plurality of levels to a level signal.

For example, for high definition television (HDTV), 256 gray levels and at least 1280 x 1024 resolution are required and at least 100:1 contrast is required at 200 lux light.

Figure 5 is a block diagram of an output driver 200' in accordance with another embodiment of the inventive concept. 6 is a diagram showing in detail one of the register array 210 and an extended delay cell array 100' illustrated in FIG. Since the embodiments illustrated in Figures 5 and 6 are similar to their embodiments illustrated in Figures 2 and 3, the differences between them will be explained to avoid redundancy.

The output driver 200' illustrated in FIG. 5 further includes a delay controller 112 as compared to the output driver 200 illustrated in FIG. The delay controller 112 generates a delay control signal DCTR for each channel to control one of the delay times of the delay unit 113 included in the extended delay cell array 100'.

The delay time of each delay unit 113 of the extended delay cell array 100' is adjusted in response to the delay control signal DCTR generated by the delay controller 112.

7A-7D are one of the delay units included in the extended delay cell array 100' illustrated in FIG. 6 in accordance with various embodiments of the inventive concept. 113 circuit diagram. In FIGS. 7A to 7D, DIN represents one input signal of the delay unit 113 and DOUT represents one output signal of the delay unit 113.

Referring to FIG. 7A, the delay unit 113 may include one or a plurality of unit delay elements UD connected in series and one or more switches SW1 to SWk connected in parallel with the unit delay elements UD, respectively. The switches SW1 to SWk may be turned on or off in response to the delay control signals DCTR<1> to DCTR<k>, respectively. The number of effective unit delay elements UD is changed in accordance with the closing or opening of the switches SW1 to SWk. The switches SW1 to SWk are initially in an open state. If both of the switches SW1 to SWk are closed in response to the delay control signals DCTR<1> to DCTR<k>, even when the number of unit delay elements UD included in the delay unit 113 is actually L, the effective unit The number of delay elements UD is (L-2). When the number of effective unit delay elements UD is adjusted for each channel, the zigzag extension output is completed.

One of the delay units 113' illustrated in FIG. 7B may include a fuse instead of the switches SW1 to SWk illustrated in FIG. 7A. The delay unit 113' may include one or more unit delay elements UD connected in series and one or more fuses connected in parallel with the unit delay elements UD, respectively. The number of effective unit delay elements UD is changed depending on whether the fuses are connected or not connected. When the number of effective unit delay elements UD is adjusted by cutting the fuse for each channel, the zigzag extension output is completed. The fuses may be initially in a connected state and may be subsequently cut, but the inventive concept is not limited thereto. For example, the fuses may initially be in a disconnected state and may then be connected by conduction of electrical current.

The delay units 113" and 113"' illustrated in Figures 7C and 7D may be packaged Inverters are included, and the inverters change a delay time in response to the delay control signals DCTR<1> to DCTR<k>.

Referring to FIGS. 7C and 7D, when the number of bits having a high level (for example, logic 1) among the delay control signals DCTR<1> to DCTR<k> is increased, the delay time may be lowered. When the number of bits having a low level (for example, logic 0) among the delay control signals DCTR<1> to DCTR<k> increases, the delay time may increase.

As explained above, in one configuration in which the delay unit has a variable delay time, to provide a sawtooth extended output, one channel of one delay unit can be configured to have a desired (or another selection system, A predetermined) fixed delay time or may be set using a delay control signal to have a certain delay time.

FIG. 8A is a diagram for explaining one of the sawtooth extended output drive architectures of one of the output drivers 200 in accordance with certain embodiments of the present inventive concepts.

Referring to FIG. 8A, the output driver 200 may sequentially output the signals Vout ₁ to Vout _N to the data lines O ₁ to O _{N , respectively} . When the output signals Vout ₁ to Vout _{N are} output to the data lines O ₁ to O _N , a parasitic capacitance Cc coupled between the adjacent data lines O _k to O _k+1 is generated. The parasitic capacitance Cc alleviates the voltage of one of the output signals due to a load effect, thereby lowering the level of a peak current.

Where there is a potential (e.g., the respective data lines O and O ₃ of the output signal Vout _{3 4 4} Vout of the high and low, respectively) produced during one extended time of the parasitic capacitance Cc between adjacent data lines. The parasitic capacitance Cc is used to reduce the peak current of the output driver 200. Therefore, electromagnetic interference (EMI) is also reduced. In other words, when the extension time during which the parasitic capacitance Cc is generated increases from a period 1 to a period 2 within a desired (or another selection system, a predetermined range) (for example, td (maximum)), the decrease is made. Peak current and EMI.

Figure 8B shows the output timing of data lines O ₁ through O _N to illustrate a conventional simultaneous switching architecture. Referring to FIG. 8B, the output driver 200 simultaneously outputs the output signals Vout ₁ to Vout _N to the data lines O ₁ to O _N . Therefore, a peak current Ipeak_a is high at an output point, as shown in Figure 9A.

Figure 8C shows the output timing of data lines O ₁ through O _N to illustrate a sequential extended output drive architecture as a comparative example.

Referring to FIG. 8C, the output driver 200 outputs the output signals Vout ₁ to Vout _N to the data lines O ₁ to O _N to extend the output. Here, the output signals Vout ₁ to Vout _N are sequentially output. Thus, as illustrated in Figure 9B, one of the peak currents Ipeak_b appearing in the sequential switching architecture is lower than the peak current Ipeak_a (Figure 9A) that occurs in the simultaneous switching architecture. However, the sequential extended output drive architecture illustrated in Figure 8C allows for an extension time of only one unit interval "td" between adjacent channels, and therefore, there is a limit to the level of decreasing a peak current.

8D shows the output timing of data lines O ₁ through O _N to illustrate a sawtooth extended output drive architecture in accordance with certain embodiments of the present inventive concepts.

As illustrated in Figure 8D, when the extension time is maximized by extending the output to a sawtooth pattern, the slope of an output voltage is slowed due to the loading effect of a parasitic capacitance, and thus, a peak current is further reduced. The level of it. In detail, the zigzag extension output drive architecture has an extension time between adjacent data lines (for example, c*td between O ₁ and O ₂ , (ca)*td and O between O ₂ and O ₃ The (da)*td between ₃ and O ₄ is longer than the extended time between adjacent data lines in the sequential extended output drive architecture, and therefore, the zigzag extended output drive architecture is further reduced compared to the sequential extended output drive architecture. A peak current and an EMI level. Thus, as illustrated in Figure 9C, a peak current Ipeak_c present in the sawtooth extended output drive architecture is lower than the peak current Ipeak_b (Figure 9B) present in the sequential extended output driver architecture.

However, since the maximum extension time for all data lines is limited, it is necessary to maximize an extension time between adjacent channels to optimize the loading effect of parasitic capacitance during the maximum extension time. During this maximum extension time, the slope of an output signal is slowed down and the level of a peak current is reduced to the same extent as the mitigation slope.

Referring to Figures 3 and 8D, each delay unit 111 in the extended delay cell array 100 can include a plurality of buffers to adjust the output timing of an output signal. For example, when it is assumed to output a signal in terms of one interval "td" time spent by a single buffer unit, coupled to the first data line O _1, one delay unit 111 may include a buffer connected to the second The delay unit 111 of the data line O ₂ may include "c" buffers, and the delay unit 111 connected to the third data line O ₃ may include "a" buffers connected to one of the fourth data lines O ₄ The delay unit 111 may include "d" buffers, and the delay unit 111 connected to the fifth data line O ₅ may include "b" buffers, where 0 < a < b < c < d N. The extended delay cell array 100 is implemented as explained above, but the inventive concept is not limited thereto.

10 illustrates an exemplary data line-time graph showing output timing of data lines O ₁ through O _N in a sawtooth extended output architecture in accordance with certain embodiments of the present inventive concepts. The sawtooth extended output architecture illustrated in Figure 10 can be performed by the output driver 200 or 200' illustrated in Figures 2 through 7D. Referring to FIG. 10, the extension time between adjacent data lines (that is, the difference between the output timings of adjacent data lines) has a sawtooth type in which one of the extension times of (+2) td and (-1) td is alternately repeated. kind.

For example, the output timing of the first data line O ₁ is 0*td, the output timing of the second data line O ₂ is 2*td, and the output timing of the third data line O ₃ is 1*td, and the fourth data line The output timing of O ₄ is 3*td and the output timing of the fifth data line O ₅ is 2*td to extend the output to a sawtooth pattern.

In other words, an extension time between the first data line O ₁ and the second data line O ₂ is 2*td, and an extension time between the second data line O ₂ and the third data line O ₃ is 1*td. An extension time between the third data line O ₃ and the fourth data line O ₄ is 2*td and an extension time between the fourth data line O ₄ and the fifth data line O ₅ is 1*td, so as to The output timing of the adjacent data line is delayed by 2*td and then leads by 1*td, and this pattern is repeated.

Thus, between the first data line and the second data line O ₁ O 2 * td (from 0 * td to 2 * td) O ₂ and the third period and the second data line between the data line ₂ O ₃ the 1 * td (from 1 * td to 2 * td) during parasitic capacitance, in the same manner, in the third data line and the fourth data line O ₃ O 2 * td between ₄ (from 3 to 1 * td During *td) and during 1*td (from 2*td to 3*td) between the fourth data line O ₄ and the fifth data line O ₅ , parasitic capacitance is generated to reduce the voltage of the output signal due to load effects The slope. Therefore, the peak current is reduced.

However, since the maximum extension time of all data lines is limited, it is necessary to design the hysteresis and lead of the output timing so that the output timing of one of the earliest output timings (for example, O _{1 in} Figure 5) is the latest. A difference between the output timings of one of the output timings (e.g., O _{N in} Figure 5) is within a desired (or another selection, a predetermined) range.

11 is a data line-time graph showing one of the output timings of data lines O ₁ to O _N in a sawtooth extended output architecture in accordance with other embodiments of the present inventive concepts. The sawtooth extension output method illustrated in FIG. 11 can be performed by the output driver 200 or 200' illustrated in FIGS. 2 through 7D. Referring to Figure 11, the extension time between adjacent data lines (i.e., the difference between the output timings of adjacent data lines) has an extension time in which (+1) td, (+1) td, and (-1) td are repeated. One of the patterns is a zigzag pattern.

For example, the output timing of the first data line O ₁ is 0*td, the output timing of the second data line O ₂ is 1*td, and the output timing of the third data line O ₃ is 2*td, and the fourth data line The output timing of O ₄ is 1*td, the output timing of the fifth data line O ₅ is 2*td, and the output timing of the sixth data line O ₆ is 3*td, so that the output is extended into a zigzag pattern.

In other words, an extension time between the first data line O ₁ and the second data line O ₂ is 1*td, and an extension time between the second data line O ₂ and the third data line O ₃ is 1*td. An extension time between the third data line O ₃ and the fourth data line O ₄ is 1*td and an extension time between the fourth data line O ₄ and the fifth data line O ₅ is 1*td, so as to The output timing of the adjacent data line lags by 1*td, then lags 1*td again and then leads 1*td, and repeats this pattern.

Thus, between the first data line and the second data line O ₁ O 1 * td between ₂ (from 0 * td to 1 * td) and during the second data line and the third data line O ₂ O ₃ the 1 * td (from 1 * td to 2 * td) during parasitic capacitance, and in the same manner, in the third data line and the fourth data line O ₃ O 1 * td between ₄ (from 1 * td to Parasitic capacitance is generated during 2*td) and during 1*td (from 2*td to 3*td) between the fourth data line O ₄ and the fifth data line O ₅ to reduce the output signal due to load effects The slope of the voltage. Therefore, the peak current is reduced.

However, since the maximum extension time of all data lines is limited, it is necessary to design the hysteresis and lead of the output timing so that the output timing of one of the earliest output timings (for example, O _{1 in} Fig. 6) has the latest output timing. A difference between the output timings of one of the output timings (e.g., O _{N in} FIG. 6) is within a desired range (or another selection, a predetermined range).

FIG 12 shows system according to one embodiment of the output timing of one of the other serrated embodiment of the present invention, the concept of extended output architecture to the data line O ₁ O _N lines of data - time diagram. The sawtooth extension output method illustrated in FIG. 12 can be performed by the output driver 200 or 200' illustrated in FIGS. 2 through 7D. Referring to FIG. 12, the extension time between adjacent data lines (that is, the difference between the output timings of adjacent data lines) has a sawtooth type in which one of the extension times of (+3) td and (-2) td is alternately repeated. kind.

For example, the output timing of the first data line O ₁ is 0*td, the output timing of the second data line O ₂ is 3*td, and the output timing of the third data line O ₃ is 1*td, and the fourth data line The output timing of O ₄ is 4*td and the output timing of the fifth data line O ₅ is 2*td to extend the output to a sawtooth pattern.

In other words, an extension time between the first data line O ₁ and the second data line O ₂ is 3*td, and an extension time between the second data line O ₂ and the third data line O ₃ is 2*td. An extension time between the third data line O ₃ and the fourth data line O ₄ is 3*td and an extension time between the fourth data line O ₄ and the fifth data line O ₅ is 2*td, so as to The output timing of the adjacent data line lags by 3*td and then leads 2*td, and this pattern is repeated.

Thus, in a first data line and the second data line O ₁ O 3 * td between ₂ (from 0 * td to 3 * td) period, and the second data line and the third data line O ₂ O ₃ of Parasitic capacitance is generated during 2*td (from 1*td to 3*td), in the same way, 3*td between the third data line O ₃ and the fourth data line O ₄ (from 1*td to Parasitic capacitance is generated during 4*td) and during 2*td (from 2*td to 4*td) between the fourth data line O ₄ and the fifth data line O ₅ to reduce the output signal due to load effects The slope of the voltage. Therefore, the peak current is reduced.

However, since the maximum extension time of all data lines is limited, it is necessary to design the hysteresis and lead of the output timing so that the output timing of one of the earliest output timings (for example, O _{1 in} Fig. 12) has the latest output timing. A difference between the output timings of one of the output timings (e.g., O _{N in} FIG. 12) is within a desired range (or another selection, a predetermined range).

Figure 13 is a graph showing the output timings O ₁ to O _N of the data lines in a sawtooth extended output architecture in accordance with another embodiment of the present inventive concept. The sawtooth extension output method illustrated in FIG. 13 can be performed by the output driver 200 or 200' illustrated in FIGS. 2 through 7D. Referring to Figure 13, the extension time between adjacent data lines (i.e., the difference between the output timings of adjacent data lines) has a zigzag type in which the extension times of (+4) td and (-3) td are alternately repeated. kind.

For example, the output timing of the first data line O ₁ is 0*td, the output timing of the second data line O ₂ is 4*td, and the output timing of the third data line O ₃ is 1*td, and the fourth data line The output timing of O ₄ is 5*td and the output timing of the fifth data line O ₅ is 2*td to extend the output to a sawtooth pattern.

In other words, an extension time between the first data line O ₁ and the second data line O ₂ is 4*td, and an extension time between the second data line O ₂ and the third data line O ₃ is 3*td. An extension time between the third data line O ₃ and the fourth data line O ₄ is 4*td, and an extension time between the fourth data line O ₄ and the fifth data line O ₅ is 3*td, so that The output timing of an adjacent data line lags by 4*td and then leads 3*td, and this pattern is repeated.

Thus, between the first data line and the second data line O ₁ O 4 * td (from 0 * td to 4 * td) O ₂ and the third period and the second data line between the data line ₂ O ₃ the 3 * td (from 1 * td to 4 * td) during parasitic capacitance, and in the same manner, in the third data line and the fourth data line O3 O 4 * td between ₄ (from 5 to 1 * td During *td) and during 3*td (from 2*td to 5*td) between the fourth data line O ₄ and the fifth data line O ₅ , parasitic capacitance is generated to reduce the voltage of the output signal due to load effects The slope. Therefore, the peak current is reduced.

However, since the maximum extension time of all data lines is limited, it is necessary to design the hysteresis and lead of the output timing so that the output timing of one of the earliest output timings (for example, O _{1 in} FIG. 13) has the latest output timing. A difference between the output timings of one of the output timings (e.g., O _{N in} FIG. 13) is within a desired range (or another selection, a predetermined range).

The inventive concept is not limited to the output timing in the embodiments illustrated in Figures 10-13, and may be embodied in various ways depending on the physical or environmental characteristics of a display panel. For example, the output timing of one (k+1)th data line adjacent to one of the kth data lines may be delayed from the output timing unit interval "td" of one of the kth data lines (its Is a positive real number) and One of the (k+2)th data lines adjacent to one of the (k+1)th data lines may have an output timing that is ahead of the output timing unit interval "td" of the (k+1)th data line (its One of the positive real numbers is used to adjust the output timing of a plurality of data lines in a zigzag pattern.

At this time, an output signal of one of the output drivers may correspond to one of the data bits or an analog signal. The digit or analog signal may have a desired (or another selection, a predetermined) voltage or a time range into which one of a plurality of levels (eg, 256 levels) is divided.

In some embodiments in accordance with the inventive concept, a sawtooth extension architecture can be varied depending on a mode. For example, the sawtooth extension architecture illustrated in FIG. 10 can be used in a first mode, and the sawtooth extension architecture illustrated in FIG. 11 can be used in a second mode, and can be used in a third The zigzag extension architecture illustrated in Figure 12 is used in the mode. The jagged extension architecture is changed depending on the mode to select a better architecture that is optimal for the type or resolution of a display panel.

Although one of the functions of selecting one mode is not shown, this function can be performed by the control circuit 25. When the control circuit 25 selects a mode among the plurality of modes, the control circuit 25 may supply the delay control signal DCTR corresponding to the selected mode to the delay controller 112 or provide a control signal CTR to a switch controller 121 (FIG. 15) ).

As set forth above, a sawtooth extended output architecture in accordance with certain embodiments of the present inventive concepts is not one such that the output timing of the signals is sequentially increased or decreased (ie, the output timings are sequentially lagging or leading to each other). And used to increase (hysteresis) and then decrease (lead) in the output timing One type or one of the lower (leading) and then increasing (lag) one type appears at least one of the controls.

14 is a block diagram of an output driver 300 in accordance with another embodiment of the inventive concept.

Referring to FIG. 14, an output driver (ie, a source driver, a W driver, or a data driver) 300 may include a register array 210, a latch circuit 211, an extended delay cell array 110, and an output module 220. In the description, the difference between the output driver 300 and the output driver 200 illustrated in FIG. 2 will be explained for the sake of convenience.

Unlike the extended delay cell array 100 illustrated in FIG. 2, the extended delay cell array 110 is coupled to the output line of the latch circuit 211 to adjust the output timing in a sawtooth pattern. The latch circuit 211 latches the data. Therefore, after the data is latched in response to a clock signal or a special signal, the output timing of the data is adjusted in a zigzag pattern just before the final output data (that is, just before the output module 220).

At this time, the output module 220 outputs the data to the data line according to the adjusted output timing. The output module 220 can include a level shifter 222 and an output buffer 223. The level shifter 222 shifts the level of the output signals O ₁ to O _N whose output timing has been adjusted. The output buffer 223 outputs the shifted output signals O ₁ to O _N to the respective data lines.

15 is a block diagram of an output driver 400 in accordance with another embodiment of the inventive concept.

Referring to FIG. 15, an output driver (ie, a source driver, a W driver, or a data driver) 400 may include a register array 210, an extension The delay-switching circuit 120, a switch controller 121, and an output module 220. In the description, the difference between the output driver 400 and the output driver 200 illustrated in FIG. 2 will be explained for the sake of convenience.

The extension delay-switching circuit 120 is coupled to the output line of the register array 210 to adjust the output timing in a zigzag pattern. Unlike the extended delay cell array 100 illustrated in FIG. 2, the extended delay-switching circuit 120 can include a plurality of (eg, N, that is, the number of data lines) switching elements.

The switch controller 121 generates a control signal CTR for turning the switching elements in the extension delay-switching circuit 120 on or off. At this time, the control signal CTR includes at least one bit and the switch controller 121 can be connected to each of the switching elements, but the inventive concept is not limited to the current embodiment.

The extension delay-switching circuit 120 turns on each of the switching elements respectively connected to the data lines in response to the control signal CTR at a corresponding output timing, thereby adjusting the output timing of the respective data lines in a zigzag pattern.

The output module 220 outputs the data to the data line according to the adjusted output timing. The output module 220 can include a latch circuit 221, a level shifter 222, and an output buffer 223.

16 is a block diagram of an output driver 500 in accordance with another embodiment of the inventive concept.

Referring to FIG. 16, an output driver (ie, a source driver, a W driver, or a data driver) 500 includes a register array 210, a latch circuit 230, a switch controller 130, and an output module 220. In the description, the difference between the output driver 500 and the output driver 200 illustrated in FIG. 2 will be explained for the sake of convenience.

The latch circuit 230 latches the data in response to a control signal CTR other than a clock signal, thereby adjusting the output timing of the data in a zigzag pattern.

The switch controller 130 generates a control signal CTR for controlling the output of the data to the data lines in the latch circuit 230. At this time, the control signal CTR includes at least one bit and can be applied to each of the data lines in the latch circuit 230, but the inventive concept is not limited to the current embodiment.

The latch circuit 230 latches and outputs the data of each data line in response to the control signal CTR, thereby adjusting the output timing of the data of the respective data lines in a zigzag pattern.

The output module 220 outputs the data to the data line according to the adjusted output timing. The output module 220 can include a level shifter 222 and an output buffer 223.

2, 5, 14-16, 8D, and 10-13 show an example of an output driver for implementing a sawtooth extended output drive architecture in accordance with various embodiments of the present inventive concepts. The inventive concept is not limited to the embodiments. For example, the extended delay cell array 100 or the extended delay-switching circuit 120 may be provided at a different location than that shown in FIG. 2, FIG. 5, FIG. 14, FIG. 15, or FIG. In other embodiments, although the extended delay cell array 100 or the extended delay-switching circuit 120 may not be provided, the output buffer 223 or the latch circuit 221 may be configured to have a sawtooth extended output function.

Figure 17 is a flow diagram of one of the methods of driving a display device in accordance with some embodiments of the present inventive concepts.

Referring to FIG. 17, in operation S10, when data is input to an output driver 200, 200', 300, 400 or 500, the output driver 200, 200', 300, 400 or 500 uses a complex number in response to a control signal CON (for example, N) data lines to receive and store data. The output driver 200, 200', 300, 400 or 500 causes an output timing of one of the N data lines to lag behind one of the kth data lines of the N data lines in operation S11 and is in operation In S12, the output timing of the output of the other of the N data lines is ahead of the output timing of the kth data line, thereby reducing the slope of the output voltage of the adjacent data lines. The output driver 200, 200', 300, 400 or 500 adjusts the output timing of the N data lines in a zigzag pattern by repeating the change of the output timing in operation S13, and outputs the output timing in the adjusted output timing in operation S14. Information on N data lines. The output driver 200, 200', 300, 400 or 500 outputs an analogous or one-bit signal having one of a plurality of levels corresponding to each of the data lines in operation S15.

Figure 18 is a flow chart showing one of the methods of driving a display device according to another embodiment of the inventive concept.

Referring to FIG. 18, in operation S20, when data is input to the output driver 200, 200', 300, 400 or 500, the output driver 200, 200', 300, 400 or 500 uses a plurality of responses in response to a control signal CON (for example, N) data lines to receive and store data. The output driver 200, 200', 300, 400 or 500 causes an output timing of one of the N data lines to lag behind one of the N data lines, one output sequence of one of the N data lines, in operation S21. L times the interval and makes N funds in operation S22 The output timing of the other of the feed lines is ahead of the output timing of the kth data line by M times the unit interval, thereby reducing the slope of the output voltage of the adjacent data lines. At this time, when L or M increases, the slope decreases and the level of a peak current also decreases due to the load effect of the parasitic capacitance. However, a difference between the earliest output timing of the N data lines and the latest output timing needs to be within a desired (or another selection, a predetermined) range and may vary depending on the physical and/or environmental characteristics of the display device. change.

The output driver 200, 200', 300, 400 or 500 adjusts the output timing of the N data lines in a zigzag pattern by repeating the change of the output timing in operation S23, and outputs the adjusted output timing in operation S24. Information on N data lines. The output driver 200, 200', 300, 400 or 500 outputs an analogous or one-bit signal having one of a plurality of levels corresponding to each of the data lines in operation S25.

19 is a block diagram of an electronic system 2000 including one of display devices 10 in accordance with certain embodiments of the present inventive concepts. The electronic system 2000 can be a mobile phone, a smart phone, a PDA, a video camera, a car navigation system (CNS) or a portable multimedia player (PMP), but it is not limited thereto. .

Referring to FIG. 19, the electronic system 2000 can include a display device 1000, a power supply 1400, a central processing unit (CPU) 1100, a memory 1200, a user interface 1300, and components 1000, 1400, 1100, 1200, and 1300. One of the system bus bars 1500 is electrically connected to each other. Display device 1000 can be the display device 10 or 20 set forth in the embodiments of the inventive concept set forth above.

The CPU 1100 controls the overall operation of the electronic system 2000. The memory 1200 stores information necessary for the operation of the electronic system 2000. User interface 1300 provides an interface between electronic system 2000 and a user. The power supply 1400 supplies power to other components, that is, the CPU 1100, the memory 1200, the user interface 1300, and the display device 1000.

20 is a block diagram of an electronic system 3000 including one of display devices 10 in accordance with other embodiments of the present inventive concepts. Referring to FIG. 20, electronic system 3000 can be implemented as one of data processing devices that can use or support the Mobile Industry Processor Interface (MIPI), such as a mobile phone, a PDA, a PMP, or a smart phone.

The electronic system 3000 includes an application processor 3010, an image sensor 3040, and a display 3050. Display 3050 can be the display device 10 or 20 set forth in the embodiments of the inventive concepts set forth above.

A camera serial interface (CSI) host 3012 implemented in the application processor 3010 can perform serial communication with one of the CSI devices 3041 included in the image sensor 3040 via CSI. At this time, an optical deserializer and an optical serializer can be implemented in the CSI host 3012 and the CSI device 3041, respectively. A display serial interface (DSI) host 3011 implemented in the application processor 3010 can perform serial communication with one of the DSI devices 3051 included in the display 3050 via DSI. At this time, an optical serializer and an optical deserializer can be implemented in the DSI host 3011 and the DSI device 3051, respectively.

Electronic system 3000 can also include a radio frequency (RF) wafer 3060 in communication with application processor 3010. One physical layer (PHY) 3013 of the application processor 3010 and one of the RF chips 3060 PHY 3061 can be transmitted to each other according to MIPI DigRF data.

The electronic system 3000 can further include a global positioning system (GPS) 3020, a storage 3070, a microphone (MIC) 3080, a dynamic random access memory (DRAM) 3085, and a speaker 3090. The electronic system 3000 can communicate using a global interoperability microwave access (Wimax) 3030, a wireless local area network (WLAN) 3100, and an ultra wide band (UWB) 3110.

21 is a block diagram of an electronic system 4000 including one of display devices 4100 in accordance with some embodiments of the present inventive concepts. The electronic system 4000 includes a display device 4100, a video converter 4200, and a speaker 4300.

The display device 4100 can include a display panel 4130, a power circuit 4110, an image signal processor 4120, and a control unit 4150. Display panel 4130 can be associated with PDP 21 as illustrated in FIG. 1D.

The interface controller 4151 included in the control unit 4150 converts external image data (for example, RGB data) into grayscale image data and transmits the grayscale image data to a data controller 4152. The data controller 4152 outputs the data to an output driver. A driver controller 4153 generates a pulse signal for controlling the output driver, an X driver, and a Y driver.

As set forth above, in accordance with certain embodiments of the inventive concept, an extended drive is utilized in a display device, thereby reducing the level of peak current that occurs when a data signal is simultaneously output. In other words, one of the coupling capacitances generated between adjacent channels is maintained for an increased period of time to relieve one of the output drivers of one of the display driver ICs (DDIs), thereby extending and reducing the peak current. Therefore, the EMI and power consumption caused by the peak current of the data driver can be reduced.

While the present invention has been shown and described with reference to the exemplary embodiments of the present invention, it will be understood by those skilled in the art In the case, various changes are made in form and detail.

10‧‧‧ display device

11‧‧‧ display panel

12‧‧‧Source Driver

13‧‧ ‧ gate driver

14‧‧‧Control circuit

20‧‧‧ display device

21‧‧‧Plastic display panel

22‧‧‧X drive

23‧‧‧Y drive

24‧‧‧W drive/address drive/data drive

25‧‧‧Control circuit

100‧‧‧Extended delay cell array

100'‧‧‧Extended delay cell array

110‧‧‧Extended delay cell array

111‧‧‧Delay unit

112‧‧‧Delay controller

113‧‧‧Delay unit

113'‧‧‧Delay unit

113"‧‧‧Delay unit

113'''‧‧‧Delay unit

120‧‧‧Extension delay-switching circuit

121‧‧‧Switch controller

130‧‧‧Switch controller

200‧‧‧output driver

200'‧‧‧output driver

210‧‧‧Data Storage Block/Storage Array

220‧‧‧Output module

221‧‧‧Latch circuit

222‧‧‧ position shifter

223‧‧‧Output buffer

230‧‧‧Latch circuit

300‧‧‧output driver

400‧‧‧output driver

500‧‧‧output driver

1000‧‧‧Display devices/components

1100‧‧‧Central Processing Unit/Element

1200‧‧‧ memory/component

1300‧‧ User Interface/Component

1400‧‧‧Power supply/component

1500‧‧‧System Bus

2000‧‧‧Electronic system

3000‧‧‧Electronic system

3010‧‧‧Application Processor

3011‧‧‧Display serial interface host

3012‧‧‧Camera Serial Interface Host

3013‧‧‧ physical layer

3020‧‧‧Global Positioning System

3030‧‧‧World Interoperability for Microwave Access

3040‧‧‧Image Sensor

3041‧‧‧Camera serial interface device

3050‧‧‧ display

3051‧‧‧Display serial interface device

3060‧‧‧RF chip

3061‧‧‧ physical layer

3070‧‧‧Storage

3080‧‧‧Microphone

3085‧‧‧ Dynamic Random Access Memory

3090‧‧‧Speakers

3100‧‧‧Wireless Local Area Network

3110‧‧‧Ultra wide band

4000‧‧‧Electronic system

4100‧‧‧ display device

4110‧‧‧Power Circuit

4120‧‧‧Image Signal Processor

4130‧‧‧ display panel

4150‧‧‧Control unit

4151‧‧‧Interface controller

4152‧‧‧ Data Controller

4153‧‧‧Drive Controller

4200‧‧‧Video Converter

4300‧‧‧ Speaker

1‧‧ cycle

2‧‧‧ cycle

Cc‧‧‧ parasitic capacitance

CON‧‧‧ control signal

CON1‧‧‧ first control signal

CON2‧‧‧second control signal

CON3‧‧‧ third control signal

D ₁ ‧‧‧Information

D ₂ ‧‧‧Information

D ₃ ‧‧‧Information

DATA‧‧‧ image data

DCTR‧‧‧ Delay Control Signal

DCTR<1>‧‧‧delay control signal

DCTR<2>‧‧‧delay control signal

DCTR<k>‧‧‧delay control signal

DIN‧‧‧ input signal

D _N ‧‧‧Information

D _N-1 ‧‧‧Information

D _N-2 ‧‧‧Information

DOUT‧‧‧ output signal

Fuse‧‧‧Fuse

G ₁ ‧‧ ‧ gate line

G _g ‧‧‧ gate line

Ipeak_a‧‧‧peak current

Ipeak_b‧‧‧peak current

Ipeak_c‧‧‧peak current

O ₁ ‧‧‧ data line

O ₂ ‧‧‧ data line

O ₃ ‧‧‧ data line

OLED‧‧ Organic Light Emitting Diode

O _N ‧‧‧ data line

O _N-1 ‧‧‧ data line

O _N-2 ‧‧‧ data line

S ₁ ‧‧‧Source line/data line

S ₂ ‧‧‧Source line/data line

S _N ‧‧‧Source line/data line

S _N-1 ‧‧‧Source line/data line

SW1‧‧‧ switch

SW2‧‧‧ switch

SWk‧‧‧ switch

Td‧‧‧ unit interval

UD‧‧‧unit delay element

Vout ₁ ‧‧‧Output signal

Vout ₂ ‧‧‧Output signal

Vout ₃ ‧‧‧Output signal

Vout ₄ ‧‧‧Output signal

Vout _N ‧‧‧Output signal

W1‧‧‧ data line/address electrode

W2‧‧‧ data line/address electrode

Ww‧‧‧ data line/address electrode

X1‧‧‧X scan line / X electrode

X2‧‧‧X scan line / X electrode

Xx‧‧‧X scan line / X electrode

Y1‧‧‧Y scan line / Y electrode

Y2‧‧‧Y scan line / Y electrode

Yy‧‧‧Y scan line / Y electrode

1A is a block diagram of a display device in accordance with some embodiments of the present inventive concept; FIG. 1B is a diagram showing a panel of a thin film transistor liquid crystal display (TFT-LCD) panel as illustrated in FIG. 1A. a circuit diagram of a pixel; FIG. 1C is a circuit diagram of a pixel when the display panel illustrated in FIG. 1A is an organic light emitting diode (OLED) panel; FIG. 1D is one of some embodiments according to the inventive concept A block diagram of a plasma display device; FIG. 2 is a block diagram of an output driver in accordance with some embodiments of the inventive concept; FIG. 3 is a detailed view of one of the register arrays and an extension illustrated in FIG. a block diagram of one of the delay cell arrays; FIG. 4 is a block diagram showing one of the examples of one of the delay cells illustrated in FIG. 3; FIG. 5 is a block diagram of one of the output drivers in accordance with another embodiment of the inventive concept; 6 is a diagram showing in detail one of the register array and an extended delay unit array illustrated in FIG. 5; FIGS. 7A to 7D are diagrams of FIG. 6 according to different embodiments of the inventive concept. A circuit diagram of one of the delay units included in the illustrated array of extended delay cells; FIG. 8A is a diagram illustrating one of the sawtooth extended output drive architectures of an output driver in accordance with some embodiments of the present inventive concepts; 8B shows the output timing of the data line to illustrate a conventional simultaneous switching architecture; FIG. 8C shows the output timing of the data line to illustrate a sequential extended output driving architecture as a comparative example; FIG. 8D shows the output timing of the data line to illustrate the concept according to the present invention. One of the embodiments has a sawtooth extended output drive architecture; Figures 9A-9C are used to compare peak currents in the architecture, peak currents in a sequential extended output drive architecture, and a sawtooth extended output drive architecture. FIG. 10 is a diagram showing an output timing of a data line in a sawtooth extended output architecture in accordance with some embodiments of the present inventive concept; FIG. 11 is a diagram showing the concept according to the present invention. One of the other embodiments is a data line-time chart of the output timing of the data lines in the sawtooth extension output architecture; 12 is a data line-time chart showing one of the output timings of data lines in a sawtooth extended output architecture according to another embodiment of the inventive concept; FIG. 13 is a diagram showing a zigzag extension according to other embodiments of the inventive concept. One of the output timings of the data lines in the output architecture Figure 14 is a block diagram of an output driver in accordance with another embodiment of the inventive concept; Figure 15 is a block diagram of an output driver in accordance with another embodiment of the inventive concept; Figure 16 is a concept in accordance with the present invention. A block diagram of one of the output drivers of another embodiment; FIG. 17 is a flow chart of one of the methods of driving a display device according to some embodiments of the present inventive concept; FIG. 18 is a diagram of driving one of other embodiments according to the inventive concept. One of the methods of one of the display devices; FIG. 19 is a block diagram of an electronic system including one of the display devices according to some embodiments of the present inventive concept; FIG. 20 includes one of the embodiments according to the inventive concept. A block diagram of one of the electronic systems of the display device; and FIG. 21 is a block diagram of an electronic system including one of the display devices in accordance with other embodiments of the inventive concept.

100‧‧‧Extended delay cell array

200‧‧‧output driver

210‧‧‧Data Storage Block/Storage Array

220‧‧‧Output module

221‧‧‧Latch circuit

222‧‧‧ position shifter

223‧‧‧Output buffer

CON‧‧‧ control signal

D ₁ ‧‧‧Information

D ₂ ‧‧‧Information

D ₃ ‧‧‧Information

D _N ‧‧‧Information

D _N-1 ‧‧‧Information

D _N-2 ‧‧‧Information

O ₁ ‧‧‧ data line

O ₂ ‧‧‧ data line

O ₃ ‧‧‧ data line

O _N ‧‧‧ data line

O _N-1 ‧‧‧ data line

O _N-2 ‧‧‧ data line

Claims (23)

A display driver integrated circuit comprising: a data storage block configured to store data corresponding to each of N data lines in a display device, wherein N is 2 or greater than 2 An integer adjustment block that is configured to adjust an output timing of data corresponding to the respective N data lines in accordance with a zigzag extension pattern; and an output module configured to be based on the The output timing is adjusted to output an output signal based on the data to the N data lines. The display driver integrated circuit of claim 1, wherein the data storage block comprises N registers for storing the data in response to a control signal; and the extension adjustment block comprises an extended delay unit array to be dependent on the sawtooth The pattern adjusts the output timing of the registers. The display driver integrated circuit of claim 2, wherein the extended delay cell array is configured to lag one of the N data lines by one of the N data lines by causing one of the first one of the N data lines to output timing And outputting timing of one of the k data lines and causing one of the N data lines to output timing to lead the output timing of the kth data line to adjust the output timings of the N data lines; And a difference between the earliest output timing of one of the N data lines and a latest output timing is within a desired time period. The display driver integrated circuit of claim 3, wherein the extended delay cell array is configured to repeat the output timing change according to the sawtooth pattern Adjusting the output timing of the N data lines. The display driver integrated circuit of claim 4, wherein the extended delay unit array comprises a plurality of delay units, wherein the plurality of delay units delay data of the N data lines according to the respective output timings of the N data lines . The display driver integrated circuit of claim 2, further comprising: a switch controller configured to generate and output a switch control signal for controlling the output timing of the N data lines, wherein the extension The delay unit array includes a switching circuit including N switching elements respectively connected to the registers, the N switching elements being configured to respond to the switch control signal in one of the N data lines Turning on one of the first one of the N data lines and one unit time interval before the output timing of the kth data line when one of the k data lines outputs L times a unit time interval At M times, one of the N data lines is turned on to output the second one. The display driver integrated circuit of claim 6, wherein the extended delay cell array is configured to adjust the output timing of the N data lines in accordance with the sawtooth pattern by repeating a change in output timing. The display driver integrated circuit of claim 1, wherein the output module comprises: a latch circuit configured to latch an output signal of each of the N data lines; a bit shift a device configured to shift a level of the latched output signal; and An output buffer configured to output the shifted output signal to each data line. The display driver integrated circuit of claim 1, wherein the data storage block comprises N registers, the N registers being configured to store the data in response to a control signal; and wherein the extension adjustment area The block includes: a latch circuit configured to adjust an output timing of the N registers according to the zigzag pattern according to an adjustment signal; and a switch controller configured to generate the adjustment signal The output timing of the N data lines is controlled to control the latch circuit. The display driver integrated circuit of claim 9, wherein the latch circuit is configured to adjust the output timing of the N data lines by latching data in response to the adjustment signal to cause the N data lines One of the first one of the output timings lags behind one of the k data lines of the N data lines, and is configured to latch the data in response to the adjustment signal to cause the N data One of the second lines of the output timing is ahead of the output timing of the kth data line; and a difference between one of the N data lines and the latest output timing is at a desired time Within the cycle. The display driver integrated circuit of claim 10, wherein the output module comprises: a one-bit shifter configured to shift a level of the latched output signal; and an output buffer It is configured to output the shifted output signal to each data line. The display driver integrated circuit of claim 1, wherein the data storage block comprises: N scratchpads configured to store the data in response to a control signal; and a plurality of latch circuits configured Each of the N registers is latched, wherein the extended adjustment block includes an array of extended delay cells configured to adjust an output of the latch circuits according to the sawtooth pattern Timing. The display driver integrated circuit of claim 12, wherein the extended delay cell array is configured to latch data by responding to the adjustment signal such that one of the first one of the N data lines outputs a timing lag Outputting a timing to one of the kth data lines of the N data lines, and latching the data in response to the adjustment signal such that one of the N data lines outputs one of the timings ahead of the first The output timing of the k data lines to adjust the output timings of the N data lines; and a difference between the earliest output timing of the N data lines and a latest output timing is at a desired time Within the cycle. The display driver integrated circuit of claim 13, wherein the extended delay cell array is configured to adjust the output timing of the N data lines in accordance with the sawtooth pattern by repeating a change in output timing. The display driver integrated circuit of claim 13, wherein the extended delay unit array comprises a plurality of delay units, wherein the plurality of delay units delay the N data lines according to the respective output timings of the N data lines material. The display driver integrated circuit of claim 15, wherein each of the plurality of delay units comprises at least one of a buffer, an inverter, a transistor, and a switching element. A display device includes: a display panel comprising N data lines, a plurality of gate lines, and a plurality of pixels connected between the N data lines and the respective gate lines, wherein the N series 2 Or an integer greater than 2; an output driver configured to drive the N data lines; a gate driver configured to gate the plurality of gate lines; and a control circuit Controlling the output driver and the gate driver, wherein the output driver includes: a data storage block configured to store data corresponding to each of the N data lines; an extended adjustment block And configured to adjust an output timing of data corresponding to the respective N data lines according to a zigzag extension; and an output module configured to be based on the adjusted output timing The output signal of the data is output to the N data lines. The display device of claim 17, which is a liquid crystal display (LCD) device or an organic light emitting diode (OLED) device. An output driver includes: a data storage block configured to store data from a data line in the output driver; An extended adjustment block configured to adjust an output timing of data corresponding to the data lines in a zigzag pattern. The output driver of claim 19, wherein the data storage block comprises one of a plurality of scratchpad registers. The output driver of claim 19, wherein the sawtooth pattern is defined by a lag time L*td and a lead time M*td, wherein L and M are natural numbers, LM is greater than or equal to 1, and td is a unit time interval. The output driver of claim 19, wherein the extended adjustment block is an extended delay cell array. The output driver of claim 22, wherein the array of extended delay cells comprises a unit delay element in parallel with the fuse, wherein the fuses are initially in a disconnected state and are configured to be connected by applying a current.