TW201301380A - Wafer treatment method and fabricating method of MOS transistor - Google Patents

Abstract

A wafer treatment method is provided including the followings. A wafer is provided, wherein the wafer includes a substrate, a first oxide layer located on a front side of the substrate and a second oxide layer located on a back side of the substrate. An etching process is performed to entirely remove the first oxide layer. A fabricating method of a MOS transistor applying the wafer treatment method is also provided.

Description

Wafer processing method and MOS transistor manufacturing method

The present invention relates to a method of processing a wafer and a method of fabricating the MOS transistor, and more particularly to a method of processing a wafer that removes only an oxide layer on the front side of a wafer or MOS transistor, and a method of fabricating the MOS transistor.

The conventional semiconductor process is formed with a layer of tantalum nitride on the back side of the wafer to prevent the components doped in the wafer from being released from the back side of the wafer during the process, thereby causing contamination of the process environment and affecting the process. Yield.

However, the tantalum nitride layer can prevent the components doped in the wafer from being released, and can prevent the back side of the wafer from being etched, but the nitridation due to the difference in lattice size and arrangement between the tantalum nitride and the tantalum wafer. The formation of germanium will cause residual thermal stress and internal stress on the germanium wafer, causing the wafer to bend so that the surface is not flat, thus making the subsequent yellow light process impossible to align, the wafer edge yield is lowered, and problems in other processes are derived. , resulting in various defects in the formed semiconductor components.

The invention provides a method for processing a wafer and a method for fabricating the MOS transistor to solve the above problems.

The present invention provides a method of processing a wafer. First, a wafer is provided, including a substrate, a first oxide layer on a front side of the substrate, and a second oxide layer on a back side of the substrate. Next, an etching process is performed to completely remove the first oxide layer.

The invention provides a method for fabricating a MOS transistor. First, a substrate is provided. Next, an epitaxial process is performed to form an epitaxial layer on a front side of the substrate. Then, an oxidation process is performed to form an oxide layer on the epitaxial layer and a back surface of the substrate, respectively. Then, a doped region is formed in the epitaxial layer. Thereafter, an etching process is performed to remove the oxide layer on the surface of the epitaxial layer.

Based on the above, the present invention provides a method of processing a wafer and a method of fabricating the MOS transistor, which only etch the oxide layer on the front side of the wafer and retain the oxide layer on the back side of the wafer. In this way, the oxide layer on the back side can be used as a barrier layer to replace the conventional nitride layer to block the leakage of dopant impurities in the wafer. Moreover, with this oxide layer as a barrier layer, there is no problem that the conventional wafer is distorted due to stress.

1-9 are cross-sectional views showing a method of processing a wafer in accordance with a preferred embodiment of the present invention. Please refer to Figure 1-9. As shown in FIG. 1 , first, a wafer 100 is provided. The wafer 100 includes a substrate 110 , a first oxide layer 120 , and a second oxide layer 130 . The first oxide layer 120 is located on a front surface S1 of the substrate 110, and the second oxide layer 130 is located on a back surface S2 of the substrate 110. In general, the substrate 110 can be a germanium substrate, a germanium-containing substrate, a germanium insulating substrate, and the like. The first oxide layer 120 and the second oxide layer 130 may be, for example, a native oxide layer of the substrate 110 or an oxide layer formed by an oxidation process.

As shown in FIG. 2, an etching process P1 is performed to completely remove the first oxide layer 120. It is emphasized herein that the present invention removes only the first oxide layer 120 and leaves the second oxide layer 130 without wet etching by immersing the entire wafer 100 directly in the wet bench. The process, such as a Buffered Oxide Etched (BOE) process, results in simultaneous etching of the first oxide layer 120 and the second oxide layer 130. In detail, since the substrate 110 is generally doped with impurities such as germanium or the like, such as etching away the second oxide layer 130 on the back surface S2, impurities in the substrate 110 are leaked, which pollutes the process environment. However, a nitride layer (not shown), such as a tantalum nitride layer, is formed on the back surface S2 of the substrate 110 to further block the leakage of impurities. The nitride layer may also be different from the material of the substrate 110. Stress is generated on the substrate 110 causing the wafer 100 to be distorted. Once the wafer 100 is distorted, it will have a negative impact on subsequent series of semiconductor processes, such as yellow light misalignment, poor flatness, edge yield degradation and defects. Therefore, in the present invention, the first oxide layer 120 is etched separately, and the second oxide layer 130 is left, so that the non-stressed second oxide layer 130 can replace the barrier function of the nitride layer (not shown). In this way, not only the impurities in the substrate 110 can be prevented from leaking, but also the wafer 100 can be prevented from being twisted. Moreover, the step of forming a nitride layer can be reduced, and the process can be simplified.

In the present embodiment, the etching process P1 is an etching process in which only a single wafer is etched at a time, and the etching process P1 may be a dynamic spin etching process. For example, the wafer 110 can be placed on a pedestal (not shown), and then the etched droplets are etched onto the front side of the wafer 110, and the first oxide layer 120 is completely etched away by rotating the wafer 110. The invention is not limited thereto.

Furthermore, in general, the thickness of the first oxide layer 120 and the second oxide layer 130 are both greater than 2000 angstroms. In the present embodiment, the first oxide layer 120 has a thickness of 3,500 angstroms and the second oxide layer 130 has a thickness of 2,000 angstroms. Taking the etching process P1 as a wet etching process as an example, in order to effectively etch the oxide layer of this thickness, the etching liquid may etch the first oxide layer 120 with an etching solution containing hydrofluoric acid. In particular, the concentration of the hydrofluoric acid is 49%, which is greater than the concentration of the conventionally diluted hydrofluoric acid, so that the first oxide layer 120 can be effectively etched away. In an embodiment of the present invention, the SEZ machine can be used for the etching process, but it can also be another machine that can etch the first oxide layer 120 separately, and the invention is not limited thereto. Furthermore, after the etching process P1 is performed, a cleaning process (not shown) may be further performed to clean the front surface S1 of the substrate 110, wherein the cleaning process is washed, for example, with a cleaning liquid containing ozone ionized water, but is not limited thereto.

Next, as shown in FIG. 3, after the etching process P1 is performed, an epitaxial process P2 may be selectively performed to form an epitaxial layer 140 on the front surface S1 of the substrate 110. The epitaxial process P2 is, for example, an N-type germanium epitaxial process, a P-type germanium epitaxial process, a germanium epitaxial process, or a carbon epitaxial process, depending on the characteristics of the semiconductor component to be formed. In this embodiment, N-type germanium epitaxy is formed on the N-type substrate.

As shown in FIG. 4, an oxidation process P3 may be further performed to form an oxide layer 150 on the front surface S1 of the substrate 110, and an oxide layer 160 on the back surface S2 of the substrate 110, wherein the oxide layer 160 includes the second oxide layer 130. And the oxide layer 162 formed in the oxidation process P3, in other words, the oxidation process P3, can thicken the second oxide layer 130 on the back surface S2. As a result, the oxide layer 150 is formed by the oxidation process P3, and the thicker oxide layer 160 can be formed in the lower layer, thereby further enhancing the function of preventing the impurities on the back surface of the wafer 110 from leaking out. The oxidation process P3 is, for example, an oxidation process such as a rapid thermal oxidation process or an in situ water vapor generation (ISSG) oxidation process, which simultaneously forms an oxide layer on the front surface S1 and the back surface S2 of the substrate 110. Further, an oxidation process in which an oxide layer is formed only on the front surface S1 of the substrate 110 is also within the scope of the present invention. Since the etching process P1 of the present invention etches only the oxide layer of the front surface S1, the effect of the present invention can be attained even if the oxide layer of the back surface is not increased in the subsequent oxidation process P3.

As shown in FIG. 5, after the oxidation process P3 is performed, an etching process P4 is performed to remove at least a portion of the oxide layer 150 of the front surface S1, for example, the oxide layer 150 or the patterned oxide layer 150 may be completely removed. Taking the patterned oxide layer 150 as an example, a photoresist layer Q may be first formed on the oxide layer 150 by etching lithography, then the photoresist layer Q is patterned, and the pattern of the photoresist layer Q is transferred to oxidation. On layer 150.

After the photoresist layer Q is removed, as shown in FIG. 6, an ion implantation process P5 is performed with the patterned oxide layer 150 as a mask to form a doping region A in the epitaxial layer 140. Herein, the ion can be adjusted by changing the pattern density of the oxide layer 150 or by etching only the upper half of the oxide layer 150 by using a half tone mask to leave a thin oxide layer 150. The implantation process P5 is doped with the impurity concentration, distribution, and uniformity of impurities in the epitaxial layer 140 to improve electrical quality. In this way, the doping region A can be formed in the epitaxial layer 140 by the steps of FIGS. 5-6.

As shown in FIG. 7, an etching process P6 is performed to remove the remaining oxide layer 150 on the surface of the epitaxial layer 140. Of course, the etching process P6 is the same as the etching process P1, and only the oxide layer 150 on the epitaxial layer 140 is etched without etching the oxide layer 160 on the back surface S2 of the substrate 110.

In addition, since the depth of the ion implantation process P5 that can be doped into the epitaxial layer 140 is limited, it is necessary to form, for example, a super-junction MOS transistor, a high voltage semiconductor device, or the like. In the case of the thick doped region A, the steps of Figs. 3-7 can be repeated. For example, as shown in FIG. 8, after the oxide layer 150 is removed, an epitaxial process P7 is performed on the epitaxial layer 140 to form an epitaxial layer 170. In other words, the thickness of the epitaxial layer is gradually increased. Then, the above oxidation process, patterning process, ion implantation process, and the like are sequentially performed to form a doped region (not shown) in the epitaxial layer 170, which is the doped region A in the epitaxial layer 170. Continuation. Thereby, a thicker epitaxial layer and a doped region A can be formed. Of course, the above process can be repeated according to actual needs, for example, 5-8 times. In this way, the structure as shown in Fig. 9 can be formed. As shown, the epitaxial layer 180 has a thickness h and has a doped region B therethrough. Moreover, the oxide layer 160 on the back surface S2 is also thickened at the same time during the plurality of oxidation processes, and is not affected by the etching process for removing the front surface S1 oxide layer 150.

Finally, the oxide layer 160 can be selectively removed at a time to further form other portions of the semiconductor component to be formed, in conjunction with product characteristics and actual process requirements. For example, in the case of forming a super-interface MOS transistor, as shown in FIG. 10, FIG. 10 is a schematic cross-sectional view of a super-interface MOS transistor according to a preferred embodiment of the present invention. After forming the doped region B, a dielectric layer (not shown) and an electrode layer (not shown) are sequentially formed on the epitaxial layer 180 and patterned to form at least one gate dielectric. Layer 192 and at least one gate electrode layer 194 are respectively disposed on each of the gate dielectric layers 192. Then, an ion implantation process is performed, for example, to form at least one source region 212, such that a source/drain pair 210 is formed with the epitaxial layer 214 outside the doped region B. Then, a sidewall spacer, an interlayer dielectric layer, a metal interconnect process, and the like can be formed. Thereafter, after the wiring process of the front surface S1 is completed, the oxide layer 160 of the back surface S2 is removed to expose the substrate 110. Next, a drain metal 220 is formed on the back surface S2 of the substrate 110. In this way, the fabrication of the MOS transistor can be completed. In one embodiment, the source/drain pair 210 has a first conductivity type, such as an N-type, and the doped region B has a second conductivity type, such as a P-type. As such, the doped region B can serve as a separation region.

In summary, the present invention provides a method for processing a wafer and a method for fabricating the MOS transistor, which only etch the oxide layer on the front side of the wafer and retain the oxide layer on the back side of the wafer. In this way, the oxide layer formed successively on the back side can be used as a barrier layer to replace the leakage of doping impurities in the wafer by the conventional nitride layer. Moreover, the oxide layer is a barrier layer, and does not cause the problem of distortion of the conventional wafer due to stress, thereby preventing semiconductor elements such as MOS transistors formed on the wafer from being misaligned, such as conventional processes. Problems such as falling edge yield or defects.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Wafer

110. . . Base

120. . . First oxide layer

130. . . Second oxide layer

140, 170, 180, 214. . . Epitaxial layer

150, 160, 162. . . Oxide layer

190. . . Source/bungee area

192. . . Gate dielectric layer

194. . . Gate electrode layer

200. . . Gate structure

210. . . Source/bungee pair

212. . . Source area

220. . . Bungee metal

A, B. . . Doped region

h. . . thickness

P1, P4, P6. . . Etching process

P2. . . Epitaxial process

P3. . . Oxidation process

P5. . . Ion implantation process

Q. . . Photoresist layer

S1. . . positive

S2. . . back

1-9 are cross-sectional views showing a method of processing a wafer in accordance with a preferred embodiment of the present invention.

Figure 10 is a cross-sectional view showing a super-interface MOS transistor in accordance with a preferred embodiment of the present invention.

110. . . Base

130. . . Second oxide layer

P1. . . Etching process

Claims (18)

A method for processing a wafer, comprising: providing a substrate, a substrate, a first oxide layer on a front surface of the substrate, and a second oxide layer on a back surface of the substrate; and performing an etching process to The first oxide layer is completely removed. The processing method of the wafer according to claim 1, after performing the etching process, further comprising: performing a plurality of oxidation processes to form an oxide layer on the front surface and the back surface of the substrate, respectively, and After the oxidation process, only the oxide layer on the front side is removed. The method for processing a wafer according to claim 2, wherein before each performing the oxidation process, further comprising: performing an epitaxial process to form an epitaxial layer on the front side. The method of processing a wafer according to claim 1, wherein the etching process etches only a single wafer at a time. The method for processing a wafer according to claim 2, wherein the etching process is a dynamic spin etching process. The method of processing a wafer according to claim 1, wherein the etching process comprises etching with an etchant containing hydrofluoric acid, and the concentration of the hydrofluoric acid is 49%. The method for processing a wafer according to claim 2, wherein the oxidation process of the back surface is thickened each time the oxidation process is performed. A method for fabricating a MOS transistor, comprising: (a) providing a substrate; (b) performing an epitaxial process to form an epitaxial layer on a front surface of the substrate; (c) performing an oxidation process, Forming an oxide layer on the epitaxial layer and a back surface of the substrate; (d) forming a doped region in the epitaxial layer; and (e) performing an etching process to remove the oxide on the surface of the epitaxial layer Floor. The method for fabricating a MOS transistor according to claim 8 , wherein after the etching process is performed to remove the oxide layer on the surface of the epitaxial layer, the method further comprises: repeating at least one time (b), (c) ), (d) and (e) steps. The method for fabricating a MOS transistor according to claim 8, wherein the step of forming the doped region comprises: performing an etching process to pattern the oxide layer on the epitaxial layer; and performing an ion cloth The implanting process forms the doped region in the epitaxial layer. The method of fabricating the MOS transistor according to claim 8, wherein the etching process comprises etching with an etching solution containing hydrofluoric acid, and the concentration of the hydrofluoric acid is 49%. The method of fabricating the MOS transistor according to claim 8, wherein the etching process etches only a single wafer at a time. The method for fabricating a MOS transistor according to claim 8, wherein the etching process is a dynamic spin etching process. The method for fabricating an MOS transistor according to claim 9, wherein each time the oxidation process is performed, the oxide layer on the back surface is thickened. The method of fabricating the MOS transistor according to claim 9, wherein the etching process is performed to remove the oxide layer on the surface of the epitaxial layer, further comprising: forming at least one gate dielectric layer and at least one a gate electrode layer; and forming at least one source region to form a source/drain pair with the epitaxial layer outside the doped region. The method of fabricating the MOS transistor according to claim 15, wherein after forming the source region, further comprising: removing the oxide layer of the back surface to expose the substrate; and the back surface of the substrate Form a bungee metal. The method of fabricating an MOS transistor according to claim 16, wherein the source/drain pair has a first conductivity type and the doped region has a second conductivity type. The method for fabricating a MOS transistor according to claim 16, wherein the doped region is a separation region.