TW201250949A - System-in-packeage (SiP) and manufacturing method thereof - Google Patents

System-in-packeage (SiP) and manufacturing method thereof Download PDF

Info

Publication number
TW201250949A
TW201250949A TW101118807A TW101118807A TW201250949A TW 201250949 A TW201250949 A TW 201250949A TW 101118807 A TW101118807 A TW 101118807A TW 101118807 A TW101118807 A TW 101118807A TW 201250949 A TW201250949 A TW 201250949A
Authority
TW
Taiwan
Prior art keywords
liquid crystal
substrate
die
passive component
pasting
Prior art date
Application number
TW101118807A
Other languages
Chinese (zh)
Other versions
TWI553795B (en
Inventor
Tae-Sin Kang
Myung-Woon Hwang
Seung-Yup Yoo
Beom-Jin Kim
Ji-Hwan Kim
Original Assignee
Fci Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fci Inc filed Critical Fci Inc
Publication of TW201250949A publication Critical patent/TW201250949A/en
Application granted granted Critical
Publication of TWI553795B publication Critical patent/TWI553795B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A system-in-package (SiP) and manufacturing method are described. The SiP structure includes a substrate, a liquid crystal disposed on the substrate, a die disposed on the liquid crystal, a leading wire connection portion for connecting the substrate to the die, a forming portion for packaging the substrate, the liquid crystal, the die and the leading wire. An attach material is used to adhere the bottom portion of the die to the top portion of the liquid crystal.

Description

201250949 、發明說明： 【發明所屬之技術領域】 本發明關於一種封裝及其製造方法’且特別是有關於一種系統級封裝 (System-in-package，SiP)結構及其製造方法。 【先前技術】. %知的系統級封裝(SiP)結構製造技術是在基材(substrate)u上將被動 元件13及液晶12等的晶片外部部件安裝、設置於安裝有晶粒(Die)14的周 邊，使得被動元件13及液晶12在電路上連接於晶粒14，從而形成一個系 統。如S 1圖所示的系統級封裝(SiP)、结構實現方法雖然是最為簡單且被廣 泛使用的結構，但系統級封裝10大小會隨著部件面積而增加，因此很難適 用於如智慧型電話一樣集成度較高的產品。 另-習知技術是將晶粒黏貼至習知被動元件的上方之結構，但由於被 安裝的各被動組件之高度有差異，使得將晶粒黏貼於被動組件上方時晶粒 的黏貼力會變弱’而黏貼力的變弱導致在進行引線連結件時因鍵合設備的 壓力而出現晶粒的移動，因此對引線連結件的鍵合產生困難。 【發明内容】 為了解決上述現有的問題’本發曰月的目的在於提供-種系統級封裝㈣ •結構及其製造方法，為能縮小與部件面積成正比而增加的封装大小，將晶 :粒_黏貼於液晶㈣此响)及被動元件的上方，從而縮小晶粒安裝面 積大]、的縣的別、，為能支#晶麵將較大輔的液晶設置于晶粒的下 方，由此触晶粒的無力，從柯崎決由鶴元制高賴糾起的 引線連結件時的困難。 ’當晶粒過多地大 本發明的另—目的在於提供_種封裝及其製造方法 201250949 於液晶面積時，在其間通過互補品來使用間隙部(Spacer)，從而加強晶粒支 撐力。 為了達到所述目的，根據本發明的第一實施例的系統級封裝(sip)結 構’其特徵在於，包括：基材(Substrate)、位於所述基材上方的液晶(Liquid Crystal)、位於所述液晶上方的晶粒、將所述基材上面與晶粒的上面以電性 方式連接的引線連結件、以及將所述基材上方及液晶、晶粒、引線連結件 的外部進行澆鑄的成型部，其中所述晶粒的下方還包括一用於黏貼于液晶 上方的黏貼材質部(Attach Material)。 根據本發明的第二實施例的系統級封裝(SiP)結構，其包括：基材、位 於所述基材上方的液晶、位於所述液晶側面的被動組件^JCC)、位於所述液 晶上方的晶粒、將所述基材上面與晶粒的上面以電性方式連接的引線連結 件、以及將所述基材上方及液晶、被動元件、晶粒、引線連結件的外部進 行澆鑄的成型部，其中所述晶粒的下方還包括一用於黏貼于液晶上方的黏 貼材質部。 根據本發明的第三實施例的系統級封裝(sip)結構，其包括：基材、位 於所述基材上方的液晶、位於所述液晶側面的被動組件、位於所述液晶及 被動組件上方的晶粒、將所述基材上面與晶粒的上面以電性方式連接的引 線連結件、以及將所述基材上方及液晶、被動元件、晶粒、引線連結件的 外部進行堯鑄的成型部，其中所述晶粒的下方還包括一用於黏貼於液晶及 被動組件上方的黏貼材質部。 根據本發明的第四實施例的系統級封裝(sip)結構，其包括··基材位 於所述基材上方的液晶、位於所述液晶側面的被動組件、位於所述液晶上 201250949 方的間隙部(Sp·)、錄__部上方的晶粒、騎述級上面與晶粒 的上面以電性方式連接的β丨線連結件、以及將所述基材上方及液晶、被動 組件、嶋m餅賴件的外部進行麟的部，其中所述間 隙部的下方還包括-用於無于液晶上方的黏貼材質部，所述晶粒的下方 還包括一用於黏貼於間隙部上方的黏貼材質部。 根據本發明的第五實施例的系驗封裝㈣結構，其包括：基材、位 於所述基材上方驗晶、位於所述液晶側面的被動組件、位於所述液晶及 被動組件上方的_部、位於所述間隙部上方的晶粒、將所述基材上面與 晶粒的上面以電性方式連接的引線連結件、以及將所述基材上方及液晶、 被動組件、嶋部、晶粒、引線連結件的外部進行麟祕型部，其中所 述間隙相下方還包括—用於黏貼於液晶及被動組件上方_貼材質部， 所述晶粒的下方還包括—用於雜於間隙部上方的㈣材質部。 根據本發明的第一 1第五實施例的系統級封裝(sip)結構，所述黏貼材 質部是由環氧、聚醯亞胺或雙轉所組成的其中一種。 根據本發明的第一實施例至第五實施例的系統級封裝⑼P)結構，所述 基材的下方包括至少—個焊球(sdderBall)。 根據本發明的第—實施例的系統級封裝(SiP)、结構的製造方法，其包括 下列步驟：在步驟(A·1)巾’紐晶安裝於基材的上面-側;在步驟(A-2)f， 通過黏貼材質部而在所述液晶的上方黏貼晶粒;在步驟(八斯，將所述基材 與8曰粒進行引線連結件而以電性方式連接;以及在步驟(A_4)中，所述基材上 方及液晶、晶粒、引線連結件的外觸成成型部。 根據本發明的第一實施例的系統級封裝⑶巧結構的製造方法，在所述 201250949 步離·4)之後，還包括步驟_，在基材下方形成至少—個焊球。 根據本發_第二實施儀系統級封裝(Sip)結構的製造方法其包括 下列步驟：在步驟㈣中，在基材的上面—側安裝液晶;在步雖2)中，在 所述液晶的側部安驗動組件;在步驟㈣中，通過黏貼材質部而在所述液. 晶的上方黏貼晶粒;在步驟(㈣中，將所述基材與晶粒進行⑽連結件而以 電性方式棘及在麵(B_5)巾，在所述顧上綠液晶、鶴組件、晶 粒、引線連結件的外部形成成型部。 根據本發明的第二實施例的系統級封裝㈣結構的製造方法，在所述 步驟(B-5)之後，還包括步驟(B_6)，在基材下方形成至少—個焊球。 根據本發日月的第三實施例的系統級封裝_結構的製造方法，其包括 下列步驟：在步驟㈣中，將液晶安裝於基材的上面一側；在步驟㈣中， 在所述液晶的側部安裝被動組件；在步導3)卜通過黏貼材質部，在所 述液晶及被動組件的上方黏貼晶粒；在步驟(c_4)中，將所述基材與晶粒進 行引線連結件㈣紐方式連接；叹在麵(c_5)巾，麵縣材上方及 液晶、被動組件、晶粒、引線連結件的外部形成成型部。 根據本發_第三實酬的級級封修ρ)結翻製造方法，在所述 步驟(C·5)之後’還包括步驟(c_6)，在基材下方形成至少一個焊球。 根據本發明的第四實施例的系統級封裝(Sip)結構的製造方法，其包括· 下列步驟：在步驟㈣中，在基材上面的一側安裝液晶；在步驟㈣中，‘ 在所述液曰日的側部安裝被動組件；在步驟阳)中，通過黏貼材質部而在所 述液晶上方黏貼間隙部；在步驟(D_4)中，通過黏貼材質部而在所述間隙部 上方黏貼晶粒；在步驟(D_5)中，將所述基材與晶粒進行引線連結件而以電 201250949 性方式連接;以及在步驟(D-6)中’在所述基材上方及液晶、被動組件、間隙 部、晶粒、引線連結件的外部形成成型部。 根據本發明的第四實施例的系統級封裝(Sip)結構的製造方法，在所述 步驟(D-6)之後，還包括步驟(D_7)，在基材下方形成至少一個焊球。 根據本發明的第五實施例的系統級封裝(SiP)結構的製造方法，其包括 下列步驟：在步驟(E-1)中，在基材上面的一側安裝液晶；在步驟(E 2)中， 在所述液晶的側部安裝被動組件；在步驟(E_3)中，通過黏貼材質部而在所 述液晶及被動組件上方黏貼間隙部；在步驟(E_4)中’通過黏貼材質部而在 所述間隙部上方黏貼晶粒；在步驟(E_5)中，將所述基材與晶粒進行引線連 結件而以電性方式連接;以及在步卿_6)巾，摘述紐±方及液晶、被動 組件、間隙部、晶粒、引線連結件的外部形成成型部。 根據本發明的第五實施例的系統級封裝(Sip)結構的製造方法，在所述 步驟(E-6)之後，還包括步驟(E_7)，在基材下方形成至少一個焊球。 根據本發明的第一實施例至第五實施例的系統級封蓼(Sip)結構的製造 方法，所述黏貼材質部是由環氧、聚醯亞胺或雙面膠中的一個而實現。 如上所述，根據本發明的各種實施例的系統級封裝(SiP)結構及其製造 方法具有如下效果。 第一，將液晶及被動元件集成于封裝之内，從而簡便地實現成為一個 系統級封裝(Sip)結構。 第二，當與現有的系統級封裝(SiP)結構相同地可以實現一個系統時， 本發月進纟將晶粒黏貼至液晶及被動元件的上方，從而使得封裝内部的 叹。十空間能縮小至晶粒面積大小小，由此實現部件的小型化。 201250949 第一將μ粒僅黏貼於被動組件的上方時，由於晶粒的黏貼力小而很 難進行引線連結件’當根據本製造方法，將較大面積驗晶設置于晶粒的 下方後黏貼晶粒時’晶粒的雜力會提高，從錢解決引線連結件時晶粒 出現移動的問題。 第四，將間隙部作為液晶與晶粒中間的支撑墊，從而使得比液晶面積 大很多的aB#4也可以穩定地黏貼於液晶及被動元件的上方使得.較大面積 的晶粒也可以實現部件的小型化。 第五’隨著部件的小型化，可以減少成本。 第六，隨著部件小型化及系統級封裝(SiP)結構中的液晶的集成 ，可以 適用於需要較高集成度的如智慧型電話的系統。 【實施方式】 參照附圖對根據本發明的具體實施例進行如下的詳細說明。 圖2為根據本發明的第一實施例的系統級封裝(Sip)結構之示意圖。 如圖2所示的第—實施例的系統級封裝(SiP)結構l〇〇a包括：基材 (SubStrate)ll〇a ;位於基材u〇a上方的液晶①丨职记Crystal)l2〇a ;位於液晶 120a上方的晶粒(Die)13〇a ;將基材u〇a的上面與晶粒13加的上面以電性 方式連接的引線連結件MQa;以及將基材UGa上方及液晶脑、晶粒·、 引線連結件140a的外部進行澆鑄的成型部15〇a。 其中’在晶粒130a的下方還包括一用於黏貼於液晶12〇a上方的黏貼材 質部(Attach Material) 131 a。 圖3為根據本發明的第二實施例的系統級封裝(sip)結構之示意圖。 如圖3所示的第二實施例的系統級封裝(SiP)結構100b包括：基材 201250949 ll〇b，位於基材ii〇b上方的液晶1咖；位於液晶側部的被動組件 (RLC)170b ;位於液晶120b上方的晶粒u〇b ;將所述基材n〇b的上面與晶 粒130b上面以電性方式連接的引線連結件勵；及將基材脑上方及液 晶120b、被動組件i70b、晶粒13〇b、引線連結件M〇b的外部進行澆鑄的 成型部150b。 這時，在晶粒130b的下方還包括一用於黏貼於液晶12〇b上方的黏貼 材質部131b。 圖4為根據本發明的第三實施例的系統級封裝(Sip)結構之示意圖。 如圖4所示的第三實施例的系統級封裝(Sip)結構1〇〇c包括：基材 ll〇c，位於基材ll〇c上方的液晶(Liquid Crystal)12〇c ;位於液曰曰曰i2〇c側部 的被動組件隱；位於液日日a 12Ge及被動組件隱上方紅粒·;將基 材ll〇c的上面與晶粒i3〇c的上面以電性方式連接的引線連結件14〇c ;及 將基材110c上方及液晶12〇c、被動組件17〇c、晶粒隱、引線連結件赚 的外部進行澆铸的成型部15〇c。 並且，在晶粒130c的下方還包括一用於黏貼於液晶12〇c及被動組件 170c上方的黏貼材質部131c。 圖5為根據本發明的第四實施例的系統級封裝(Sip)結構之示意圖。 如圖5所示的第四實施例的系統級封裝(Sip)結構1〇〇d包括·基材 110d ;位於基材110d上方的液晶120d ;位於液晶圓側部的被動組件 170d ;位於液晶120d上方的間隙部180d ;位於間隙部18〇d上方的晶粒 ;將基材_的上面與晶粒13Gd上面以電性方式連接的引線連結件 140d ;將基材110d上方及液晶12〇(1、被動組件nod、間隙部18〇d、晶粒 201250949 130d、引線連結件I40d的外部進行澆鑄的成型部15〇d。 其中’間隙部刪的下方還包括一用於黏貼於液晶删上方的黏貼 材質部181d ’在晶粒130d的下方還包括一用於黏貼於間隙部麵上方的 黏貼材質部131d。 圖6為根據本發明的第五實施例的系統級封裝(Sip)結構之示意圖。 如圖6所示的第五實施例的系統級封裝(Sip)結構驗包括：基材 ll〇e ,位於基材n〇e上方的液晶12〇e ;位於液晶側部的被動組件 17〇e;位於液晶120e及被動組件17〇e上方的間隙部18〇e;位於間隙部i8〇e ’方的晶粒130e ;將基材UOe的上面與晶粒13〇e上面以電性方式連接的 引線連結件140e ;及將基材110e上方及液晶n〇e、被動組件17〇e、間隙 部180e、晶粒13〇e、引線連結件14〇e的外部進行澆鑄的成型部15加。 並且’在間隙部180e的下方還包括一用於黏貼於液晶12〇e及被動組件 170e上方的黏貼材質部181e，在晶粒13〇e的下方還包括一用於黏貼於間隙 部180e上方的黏貼材質部me。 根據本發明的第一至第五實施例的系統級封裝(Sip)結構l〇〇a〜1〇〇e的 黏貼材質部131a〜131e及181d〜181e是由環氧、聚醯亞胺或雙面膠中的一 個而實現。 並且’根據本發明的第一實施例至第五實施例的系統級封裝(Sip)結構 $ 100a〜100e)的基材ll〇a〜110e)為，下部形成有至少一個焊球(Solder &quot; ball)160a〜160e的球格陣列(Ball Grid Array, BGA)形態，也可以不需要透過 焊球的平面閘格陣列(Land Grid ^吁，LGA)形態實現出來。 圖7為示意根據本發明的第一實施例中系統級封裝(SiP)結構的製造方 201250949 法之步驟順序圖。 如圖7所示的第一實施例的系統級封裝(Sip)結構腦a的製造方法，包 括在乂驟(八-1) (siioa)中，在基材ii〇a上面的一側安裝液晶㈣砲 ^加㈣隱；在步驟(A—2) (S120A)中，通過黏貼材質部(Attach Material)131a 而在液晶120a上方黏貼晶粒(Die)13〇a;在步驟(a_3)(s13〇a)中，將基材^㈨ 於晶粒130a進行引線連結件14〇而以電性方式連接；以及在步驟(A》 (S140A)巾在基材u〇a上方及液晶12〇a、晶粒13〇a、引線連結件的 外部形成成型部150a。 其中，步驟(A-4)(S140A)為止為未形成有焊球的lGA形態，但之後還 包括步驟(A-5)，在基材ii〇a下方形成至少一個焊球廳，從而可以以bga 形態實現。 圖8為示意根據本發明的第二實施例中系統級封裝(Sip)結構的製造方 法之步驟順序圖。 如圖8所示的第二實施例的系統級封裝(Sip)結構1〇此的製造方法，包 括·在步驟(B-1)(S110B)中，在基材il〇b上面的一側安農液晶12〇b ;在步 驟(B-2) (Sl2〇B)中，在液晶i2〇b .的側部安裝被動組件;在步驟 (B-3) (S130B)中，通過黏貼材質部131b而在液晶12〇b上方黏貼晶粒13此； 1在步驟(B-4) (S140B)中，將基材110b與晶粒130b進行引線連結件·而 以電性方式連接；以及在步驟(B_5) (S150B)中，在基材n〇b上方及液晶 120b、被動組件170b、晶粒130b、引線連結件140b的外部形成成型部15〇b。 並且，步驟(B-5)(S150B)為止為未形成有焊球的LGA形態，但之後還201250949, EMBODIMENT OF THE INVENTION: TECHNICAL FIELD The present invention relates to a package and a method of fabricating the same, and in particular to a system-in-package (SiP) structure and a method of fabricating the same. [Prior Art] A known system-in-package (SiP) structure manufacturing technique is to mount and mount a wafer external component such as a passive component 13 and a liquid crystal 12 on a substrate u to mount a die (Die) 14 The periphery is such that the passive component 13 and the liquid crystal 12 are electrically connected to the die 14 to form a system. Although the system-in-package (SiP) and structure implementation methods shown in Figure 1 are the simplest and widely used structures, the size of the system-in-package 10 increases with the area of the components, making it difficult to apply to smart types. A product with a higher level of integration. Another conventional technique is to attach the die to the structure above the conventional passive component, but due to the difference in height of the passive components to be mounted, the adhesion of the die will change when the die is pasted on the passive component. The weakening of the adhesive force causes the movement of the crystal grains due to the pressure of the bonding apparatus when the lead bonding member is performed, and thus the bonding of the lead bonding members is difficult. SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the purpose of the present invention is to provide a system-level package (four) structure and a manufacturing method thereof, in order to reduce the package size which is proportional to the component area, the crystal size: _Adhesive to the liquid crystal (4) and the top of the passive component, so as to reduce the size of the die mounting area, and the county's other, the crystallized surface of the larger auxiliary liquid is placed under the die, thereby touching The weakness of the grain is difficult from the fact that Keqi is determined by the Heyuan system. </ RTI> When the crystal grains are excessively large, another object of the present invention is to provide a package and a method for manufacturing the same. In the liquid crystal area, a space portion is used by a complementary product therebetween to enhance the crystal grain supporting force. In order to achieve the object, a system-in-package (sip) structure according to a first embodiment of the present invention includes: a substrate, a liquid crystal located above the substrate, and a location a die above the liquid crystal, a lead connecting member electrically connecting the upper surface of the substrate and the upper surface of the die, and a molding for casting the upper portion of the substrate and the liquid crystal, the die, and the lead connecting member The portion of the die further includes an adhesive material for adhering to the liquid crystal. A system-in-package (SiP) structure according to a second embodiment of the present invention, comprising: a substrate, a liquid crystal above the substrate, a passive component (JCC) on a side of the liquid crystal, above the liquid crystal a die, a lead connecting member electrically connecting the upper surface of the substrate and the upper surface of the die, and a molding portion for casting the upper portion of the substrate and the liquid crystal, the passive component, the die, and the lead connecting member The underside of the die further includes an adhesive material portion for adhering to the liquid crystal. A system-in-package (sip) structure according to a third embodiment of the present invention, comprising: a substrate, a liquid crystal above the substrate, a passive component on a side of the liquid crystal, above the liquid crystal and the passive component a die, a lead connecting member electrically connecting the upper surface of the substrate and the upper surface of the die, and a molding for casting the upper portion of the substrate and the liquid crystal, the passive component, the die, and the lead bonding member The portion of the die further includes an adhesive material portion for adhering to the liquid crystal and the passive component. A system-in-package (sip) structure according to a fourth embodiment of the present invention, comprising: a liquid crystal on a substrate above the substrate, a passive component on a side of the liquid crystal, and a gap of 201250949 on the liquid crystal a portion (Sp·), a die above the __ portion, a β-twist connector electrically connected to the upper surface of the die and an upper surface of the die, and a liquid crystal, a passive component, and a ruthenium on the substrate The outer part of the m cake is subjected to a portion of the lining, wherein the lower portion of the gap portion further includes - for the adhesive material portion not above the liquid crystal, and the bottom portion of the die further includes a sticker for adhering over the gap portion Material department. According to a fifth embodiment of the present invention, a package (4) structure includes: a substrate, a crystal on the substrate, a passive component on the side of the liquid crystal, and a portion above the liquid crystal and the passive component a die located above the gap portion, a lead connecting member electrically connecting the upper surface of the substrate and the upper surface of the die, and a liquid crystal, a passive component, a beak, a die above the substrate The outer portion of the lead connecting member is subjected to a secluded portion, wherein the gap portion further includes - for adhering to the liquid crystal and the upper portion of the passive component - the material portion, and the bottom of the die further includes - for intermingling with the gap portion The top (four) material section. According to the system-in-package (sip) structure of the first to fifth embodiments of the present invention, the adhesive material portion is one of epoxy, polyimide or double-turn. According to the system-in-package (9) P) structure of the first to fifth embodiments of the present invention, the underside of the substrate includes at least one sStack Ball. A system-in-package (SiP), structure manufacturing method according to a first embodiment of the present invention, comprising the steps of: mounting a neodymium on the top side of the substrate in step (A·1); -2) f, pasting the crystal grains on the liquid crystal by pasting the material portion; in the step (eight s, the substrate is electrically connected to the lead bond of 8 曰 particles; and in the step ( In A_4), the outer portion of the substrate and the liquid crystal, the crystal grain, and the lead bonding member are externally contacted into a molding portion. The manufacturing method of the system-in-package (3) according to the first embodiment of the present invention is performed at the step of 201250949 4) After that, the method further includes the step of forming at least one solder ball under the substrate. The manufacturing method of the system-in-package (Sip) structure according to the present invention includes the following steps: in the step (4), the liquid crystal is mounted on the upper side of the substrate; in step 2), in the liquid crystal a side anchoring component; in step (4), pasting the die on the liquid crystal by pasting the material portion; in the step ((4), the substrate and the die are bonded to the die (10) to be electrically a method of forming a molded portion on the outside of the green liquid crystal, the crane component, the die, and the lead bonding member. The manufacturing of the system-in-package (four) structure according to the second embodiment of the present invention. The method, after the step (B-5), further comprises a step (B_6) of forming at least one solder ball under the substrate. The system-in-package_structure manufacturing method according to the third embodiment of the present invention , comprising the steps of: in step (4), mounting the liquid crystal on the upper side of the substrate; in step (4), installing a passive component on the side of the liquid crystal; in step (3), by pasting the material portion, Pasting the die on the liquid crystal and the passive component; in step (c_4), Die into the substrate and the lead line coupling member connected iv York; the sigh face (C_5,) towels, and the upper surface of the liquid crystal material county, passive components, die, molding portion formed in the lead connecting the outer member. According to the method of the present invention, the step of manufacturing the knuckle, after the step (C·5), further includes the step (c_6) of forming at least one solder ball under the substrate. A method of fabricating a system-in-package (Sip) structure according to a fourth embodiment of the present invention, comprising the steps of: in step (4), mounting a liquid crystal on one side of a substrate; and in step (4), a passive component is mounted on a side of the liquid helium day; in the step Yang), a gap portion is pasted on the liquid crystal by pasting the material portion; in the step (D_4), the crystal is pasted on the gap portion by pasting the material portion a granule; in the step (D_5), the substrate and the die are subjected to a wire bonding member to be electrically connected in a 201250949 manner; and in the step (D-6), a liquid crystal and a passive component are disposed above the substrate. A molded portion is formed on the outside of the gap portion, the die, and the lead connecting member. A method of fabricating a system-in-package (Sip) structure according to a fourth embodiment of the present invention, after the step (D-6), further comprising a step (D_7) of forming at least one solder ball under the substrate. A method of fabricating a system-in-package (SiP) structure according to a fifth embodiment of the present invention, comprising the steps of: in step (E-1), mounting a liquid crystal on one side of a substrate; in step (E 2) a passive component is mounted on a side of the liquid crystal; in the step (E_3), a gap portion is pasted over the liquid crystal and the passive component by pasting the material portion; and in the step (E_4), by pasting the material portion a die is pasted on the gap portion; in the step (E_5), the substrate and the die are electrically connected to each other by a wire bond; and in the step _6) towel, the New Zealand and A molding portion is formed on the outside of the liquid crystal, the passive component, the gap portion, the die, and the lead bonding member. A method of fabricating a system-in-package (Sip) structure according to a fifth embodiment of the present invention, after the step (E-6), further comprising a step (E_7) of forming at least one solder ball under the substrate. According to the manufacturing method of the system-level sealing (Sip) structure of the first to fifth embodiments of the present invention, the adhesive material portion is realized by one of epoxy, polyimide or double-sided tape. As described above, the system-in-package (SiP) structure and the method of fabricating the same according to various embodiments of the present invention have the following effects. First, the liquid crystal and passive components are integrated into the package, making it easy to implement a system-in-package (Sip) structure. Second, when a system can be implemented in the same way as the existing system-in-package (SiP) structure, this month's enamel will adhere the die to the liquid crystal and the passive component, thus making the inside of the package sigh. Ten spaces can be reduced to a small size of the crystal grain area, thereby achieving miniaturization of components. 201250949 When the first μ particle is adhered only to the top of the passive component, it is difficult to carry out the lead bonding member due to the small adhesion force of the die. When the large-area crystal is placed under the die according to the manufacturing method, the paste is pasted. In the case of crystal grains, the impurity of the crystal grains is increased, and the problem of the movement of the crystal grains when the lead bonding member is solved is solved. Fourthly, the gap portion is used as a support pad between the liquid crystal and the crystal grain, so that the aB#4 which is much larger than the liquid crystal area can be stably adhered to the liquid crystal and the passive element. The larger area of the crystal grain can also be realized. Miniaturization of components. Fifth, with the miniaturization of components, costs can be reduced. Sixth, with the miniaturization of components and the integration of liquid crystals in a system-in-package (SiP) structure, it can be applied to systems that require higher integration, such as smart phones. [Embodiment] A specific embodiment according to the present invention will be described in detail below with reference to the accompanying drawings. 2 is a schematic diagram of a system level package (Sip) structure in accordance with a first embodiment of the present invention. The system-in-package (SiP) structure 10a of the first embodiment shown in FIG. 2 includes: a substrate (SubStrate) 11A; a liquid crystal 1 above the substrate u〇a) a die (Die) 13〇a located above the liquid crystal 120a; a wire bond MQa electrically connected to the upper surface of the substrate u〇a and the die 13; and a substrate UGa above and a liquid crystal The molded portion 15A for casting the outside of the brain, the crystal grain, and the lead wire connecting member 140a. Wherein the underside of the die 130a further includes an adhesive material 131a for adhering over the liquid crystal 12A. 3 is a schematic diagram of a system level package (sip) structure in accordance with a second embodiment of the present invention. The system-in-package (SiP) structure 100b of the second embodiment as shown in FIG. 3 includes: a substrate 201250949 ll 〇 b, a liquid crystal 1 located above the substrate ii 〇 b; a passive component (RLC) located at the side of the liquid crystal 170b; a crystal grain u〇b located above the liquid crystal 120b; a wire bonding member electrically connecting the upper surface of the substrate n〇b and the die 130b; and the substrate above the brain and the liquid crystal 120b, passive The molded portion 150b is molded by the outside of the module i70b, the die 13〇b, and the lead fastener M〇b. At this time, an adhesive material portion 131b for adhering to the upper surface of the liquid crystal 12〇b is further included under the die 130b. 4 is a schematic diagram of a system level package (Sip) structure in accordance with a third embodiment of the present invention. The system-in-package (Sip) structure 1〇〇c of the third embodiment shown in FIG. 4 includes: a substrate 11〇c, a liquid crystal 12〇c located above the substrate 11〇c; The passive component on the side of 曰曰i2〇c is hidden; the red particle on the liquid day and day a 12Ge and the passive component is hidden; the lead which electrically connects the upper surface of the substrate 11〇c and the upper surface of the die i3〇c The connecting member 14〇c and the molded portion 15〇c for casting the outside of the substrate 110c and the liquid crystal 12〇c, the passive component 17〇c, the die, and the lead bond. Further, under the die 130c, an adhesive material portion 131c for adhering to the liquid crystal 12c and the passive component 170c is further included. Figure 5 is a schematic diagram of a system level package (Sip) structure in accordance with a fourth embodiment of the present invention. The system-in-package (Sip) structure 1〇〇d of the fourth embodiment shown in FIG. 5 includes a substrate 110d; a liquid crystal 120d located above the substrate 110d; a passive component 170d located at a side of the liquid crystal circle; and a liquid crystal 120d a gap portion 180d above; a die located above the gap portion 18〇d; a wire bond member 140d electrically connecting the upper surface of the substrate_ to the upper surface of the die 13Gd; and a substrate 110d above and a liquid crystal 12〇 (1) The passive component nod, the gap portion 18〇d, the die 201250949 130d, and the molded portion 15〇d of the lead connector I40d are cast outside. The underside of the gap portion further includes a sticker for adhering to the liquid crystal. The material portion 181d' further includes a pasting material portion 131d for adhering over the gap portion surface under the die 130d. Fig. 6 is a schematic view showing a system-in-package (Sip) structure according to a fifth embodiment of the present invention. The system-in-package (Sip) structure of the fifth embodiment shown in FIG. 6 includes: a substrate 11〇e, a liquid crystal 12〇e located above the substrate n〇e; a passive component 17〇e located at a side of the liquid crystal; a gap portion 18〇e located above the liquid crystal 120e and the passive component 17〇e; a die 130e on the side of the gap portion i8〇e'; a wire bond member 140e electrically connecting the upper surface of the substrate UOe and the die 13〇e; and a substrate 110e above and a liquid crystal n〇e, passive The molded portion 15 is formed by the assembly 17〇e, the gap portion 180e, the die 13〇e, and the outside of the lead connecting member 14〇e. And 'there is also a lower portion of the gap portion 180e for adhering to the liquid crystal 12〇e And the adhesive material portion 181e above the passive component 170e further includes a pasting material portion me for adhering over the gap portion 180e below the die 13〇e. The system level according to the first to fifth embodiments of the present invention The adhesive material portions 131a to 131e and 181d to 181e of the package (Sip) structure 10a to 1〇〇e are realized by one of epoxy, polyimide or double-sided tape. And 'according to the present invention The substrate of the system-in-package (Sip) structure of the first embodiment to the fifth embodiment (100a to 100e) is lla to 110e), and the lower portion is formed with at least one solder ball (Solder &quot; ball) 160a to 160e. Ball Grid Array (BGA) form, it is also possible to eliminate the need to pass through the solder ball's planar gate grid array (L And Grid ^, LGA) form is realized. Figure 7 is a sequence diagram showing the steps of the manufacturer's 201250949 method of the system-in-package (SiP) structure in accordance with the first embodiment of the present invention. A method of manufacturing a system-in-package (Sip) structure brain a of the first embodiment shown in FIG. 7 includes installing liquid crystal on a side above the substrate ii〇a in a step (8-1) (siioa) (4) The gun is added (4) hidden; in the step (A-2) (S120A), the die (Die) 13〇a is pasted on the liquid crystal 120a by the adhesive material 131a; in the step (a_3) (s13) In 〇a), the substrate (9) is electrically connected to the die 130 of the die 130a; and in the step (A) (S140A), the substrate is over the substrate u〇a and the liquid crystal 12〇a, The die 13a and the outer portion of the lead bonding member are formed into a molding portion 150a. The step (A-4) (S140A) is an lGA form in which no solder balls are formed, but the step (A-5) is further included. At least one solder ball hall is formed under the substrate ii〇a so as to be realized in the form of bga. Fig. 8 is a sequence diagram showing the steps of the manufacturing method of the system-in-package (Sip) structure according to the second embodiment of the present invention. The system-in-package (Sip) structure of the second embodiment shown in FIG. 1 is a manufacturing method including, in the step (B-1) (S110B), on the side of the substrate il〇b Crystal 12〇b; in step (B-2) (Sl2〇B), a passive component is mounted on the side of the liquid crystal i2〇b.; in the step (B-3) (S130B), by bonding the material portion 131b Adhering to the die 13 above the liquid crystal 12〇b; 1 in step (B-4) (S140B), the substrate 110b and the die 130b are electrically connected to each other; and in the step (B_5) (S150B), the molding portion 15b is formed on the substrate n〇b and on the outside of the liquid crystal 120b, the passive component 170b, the die 130b, and the lead fastener 140b. Further, in the step (B-5) (S150B) It is an LGA form in which no solder balls are formed, but after that

包括步驟(B-6) ’在基材1 l〇b下方形成至少一個焊球丨6〇b，從而可以以BGA 11 201250949 形態實現。 圖9為不意根據本發明的第三實施例中系統級封襞(Sip)結構的製造方 法之步驟順序圖。 如圖9所示的第三實施例的系統級封裝(Sip)結構1〇〇c的製造方法，包* 括.在步驟(e.-l)(S110C)中，在基材ii〇c上面的一側安裝液晶⑽；在步 驟(C-2) (S120C)中，在液晶12〇c的側部安裝被動組件17〇c ;在步驟(C-3) (S130C)中，it過黏貼材質部131c而在液晶12〇c及被動組件·上方黏貼. 晶粒130c;在步驟(C-4)(S140C)中，將基材ll〇c與晶粒130c進行引線連結 件140c而以電性方式連接；以及在步驟(c_5)(sl5〇c)中，在基材n〇c上方 及液晶120c、被動組件i7〇c、晶粒i3〇c、引線連結件14〇c的外部形成成 型部150c。 其中，步驟(C-5)(S150C)為止為未形成有焊球的LGA形態，但之後還 包括步驟(C-6)’在基材ii〇c下方形成至少一個焊球丨6〇c，從而可以以BGA 形態實現。 圖10為示意根據本發明的第四實施例中系統級封裝(Sip)結構的製造方 法之步驟順序圖。 如圖10所示的第四實施例的系統級封裝(Sip)結構100d的製造方法， 包括：在步驟(D-1)(S110D)中，在基材110d上面的一側安裝液晶12〇d ;在 ¥ 步驟(D-2) (S120D)中，在液晶120d的側部安裝被動組件i7〇d;在步驟(D-3)&quot; (S130D)中，通過黏貼材質部181d而在液晶i2〇d上方黏貼間隙部 (Spacer)180d ;在步驟(D-4) (S140D)中’通過黏貼材質部i31d而在間隙部 180d上方黏貼晶粒I30d ;在步驟(D-5) (S150D)中，將所述基材u〇d與晶粒 201250949 聰進行引線連結件刚而以電性方式連接；以及在步驟㈣）哪㈣ •中在基材110d上方及液晶120d、被動組件nod、間隙部⑽心晶粒^d、 引線連結件14〇d的外部形成成型部I50d。 並且’步驟(D-6)(S160D)為止為未形成有焊球的]^形態，但之後還 包括步驟(D-7)，在基材鹽下方形成至少一個焊球丽，從而可以以腿 形態實現。 圖U為示意根據本發明的第五實施例中系統級封裝(Sip)結構的製造方 法之步驟順序圖。 如圖11所示的第五實施例的系統級封裝(SiP)結構100e的製造方法， 包括：在步驟(E-l) (S110E)中，在基材11〇e上面的一侧安裝液晶12〇e ;在 乂驟佐2)(812(®)中，在液晶i2〇e的側部安裝被動組件17〇e ;在步驟(e_3) (S130E)中，通過黏貼材質部181e而在液晶12〇e及被動組件i7〇e上方黏貼 間隙部180e;在步驟(E_4)(S140E)中，通過黏貼材質部nie而在間隙部i8〇e 上方黏貼晶粒130e ;在步驟(E_5) (S150E)中，將基材n〇e與晶粒13〇e進行 引線連結件140e而以電性方式連接；在步驟(E_6)巧丨的均甲，在基材u〇e 上方及液晶120e、被動組件17〇e、間隙部18〇e、晶粒13〇e、引線連結件 140e的外部形成成型部15〇e。 、 其中，步驟(E_6) (S160E)為止為未形成有焊球的LGA形態，但之後還 包括步驟(E-7)，在基材11 〇e下方形成至少一個焊球J6〇e，從*可以以Bga 形態實現。 根據本發明的第一實施例至第五實施例的系統級封裝(Sip)結構 100a〜l〇〇e的製造方法，其黏貼材質部131a〜131e及181d〜181e是由環氧、 13 201250949 聚醯亞胺或雙面膠所組成的其中一種。 雖然本發日月已用健實施_露如上，然其並非用錄定本發明，本 發明所屬技術賴巾具有通常知識者，在不脫縣發明之精姊範圍内， 當可作各種之更動細飾，@此本發明之健翻當視後附之巾請專利範 圍所界定者為準。 【圖式簡單說明】 第1圖為現有⑽、驗封裝(SiP)結構封裝結構的示意圖； 第2圖為根據本發明的第一實施例的系統級封裝(Sip)結構之示意圖； 第3圖為根據本發明的第二實施例的系統級封郞ip)結構之示意圖； 第4圖為根據本發明的第三實施例的系統級封裝(Sip)結構之示意圖： 第5圖為根據本發明的第四實施例的系統級封裝(Sip)結構之示意圖； 第6圖為根據本發明的第五實施例的系統級封裝(sip)結構之示意圖； 第7圖為根據本發明的第一實施例中系統級封裝(sip)結構的製造方法 之步驟順序圖； 第8圖為根據本發明的第二實施例中系統級封裝(Sip)結構的製造方法 &lt;步驟順序圖； 第9圖為根據本發明的第三實施例中系統級封裝(Sip)結構的製造方法 之步驟順序圖； 第10圖為根據本發明的第四實施例中系統級封裝(siP)結構的製造方法 &lt;步驟順序圖；以及 第11圖為根據本發明的第五實施例中系統級封裝(siP)結構的製造方法 &lt;步驟順序圖。Including step (B-6)', at least one solder ball 丨6〇b is formed under the substrate 1 l〇b, so that it can be realized in the form of BGA 11 201250949. Figure 9 is a sequence diagram showing the steps of a manufacturing method of a system level package (Sip) structure in accordance with a third embodiment of the present invention. A manufacturing method of a system-in-package (Sip) structure 1〇〇c of the third embodiment shown in FIG. 9 is included. In the step (e.-1) (S110C), on the substrate ii〇c The liquid crystal (10) is mounted on one side; in the step (C-2) (S120C), the passive component 17〇c is mounted on the side of the liquid crystal 12〇c; in the step (C-3) (S130C), the over-adhesive material is The portion 131c is pasted on the liquid crystal 12〇c and the passive component. The die 130c; in the step (C-4) (S140C), the substrate 11c and the die 130c are electrically connected to the lead connecting member 140c. In the step (c_5) (sl5〇c), a molding portion is formed on the substrate n〇c and on the outside of the liquid crystal 120c, the passive component i7〇c, the die i3〇c, and the lead bonding member 14〇c. 150c. Wherein, the step (C-5) (S150C) is an LGA form in which no solder balls are formed, but further includes a step (C-6) of forming at least one solder ball 丨6〇c under the substrate ii〇c, This can be achieved in the form of a BGA. Figure 10 is a sequence diagram showing the steps of a method of fabricating a system-in-package (Sip) structure in accordance with a fourth embodiment of the present invention. The manufacturing method of the system-in-package (Sip) structure 100d of the fourth embodiment shown in FIG. 10 includes: in step (D-1) (S110D), mounting liquid crystal 12〇 on one side of the substrate 110d. In the step (D-2) (S120D), the passive component i7〇d is mounted on the side of the liquid crystal 120d; in the step (D-3)&quot; (S130D), the liquid crystal i2 is adhered by the bonding material portion 181d. A gap portion (Spacer) 180d is adhered to the top of the crucible d; in the step (D-4) (S140D), the crystal grain I30d is pasted over the gap portion 180d by the adhesive material portion i31d; in the step (D-5) (S150D) , the substrate u〇d and the die 201250949 Cong wire joints are just electrically connected; and in step (4)) (4) • above the substrate 110d and the liquid crystal 120d, the passive component nod, the gap portion (10) The core die ^d and the outer portion of the lead fastener 14〇d form the molded portion I50d. And the 'step (D-6) (S160D) is a shape in which no solder balls are formed, but the step (D-7) is further included, and at least one solder ball is formed under the substrate salt, so that the leg can be formed Formal realization. Figure U is a sequence diagram showing the steps of a method of fabricating a system-in-package (Sip) structure in accordance with a fifth embodiment of the present invention. A method of manufacturing a system-in-package (SiP) structure 100e according to a fifth embodiment shown in FIG. 11 includes: in step (El) (S110E), mounting a liquid crystal 12〇 on a side above the substrate 11〇e In the step 2) (812(®), the passive component 17〇e is mounted on the side of the liquid crystal i2〇e; in the step (e_3) (S130E), the liquid crystal 12〇e is adhered by the material portion 181e And the gap portion 180e is pasted on the passive component i7〇e; in the step (E_4) (S140E), the die 130e is pasted over the gap portion i8〇e by pasting the material portion nie; in the step (E_5) (S150E), The substrate n〇e and the die 13〇e are electrically connected to the lead bonding member 140e; in the step (E_6), the uniformity of the substrate, above the substrate u〇e and the liquid crystal 120e, the passive component 17〇 e, the gap portion 18〇e, the die 13〇e, and the lead connecting member 140e are formed outside the molded portion 15〇e. wherein, in the step (E_6) (S160E), the LGA form in which the solder ball is not formed is formed, but after that Further including the step (E-7), at least one solder ball J6〇e is formed under the substrate 11 〇e, which can be realized in the form of Bga from *. According to the first to fifth embodiments of the present invention In the method of manufacturing the system-in-package (Sip) structures 100a to 100E, the adhesive material portions 131a to 131e and 181d to 181e are one of epoxy, 13 201250949 polyimine or double-sided tape. The present day and the month have been implemented with the implementation of the above-mentioned _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ @本本本发明的 Theft is attached to the scope of the patent, whichever is defined by the patent scope. [Simplified Schematic] Figure 1 is a schematic diagram of the existing (10), inspection package (SiP) structure package structure; A schematic diagram of a system-in-package (Sip) structure according to a first embodiment of the present invention; FIG. 3 is a schematic diagram of a system-level package ip) structure according to a second embodiment of the present invention; Schematic diagram of a system-in-package (Sip) structure of a third embodiment: FIG. 5 is a schematic diagram of a system-in-package (Sip) structure according to a fourth embodiment of the present invention; FIG. 6 is a fifth embodiment according to the present invention. Schematic diagram of a system-in-package (sip) structure of an example; Figure 7 is a sequence diagram showing the steps of a method of fabricating a system-in-package (sip) structure in accordance with a first embodiment of the present invention; and Figure 8 is a diagram showing the fabrication of a system-in-package (Sip) structure in accordance with a second embodiment of the present invention. Method &lt;Step Sequence Diagram; FIG. 9 is a sequence diagram showing the steps of a method of manufacturing a system-in-package (Sip) structure according to a third embodiment of the present invention; FIG. 10 is a system level in a fourth embodiment according to the present invention. The manufacturing method of the package (siP) structure &lt;step sequence diagram; and FIG. 11 is a manufacturing method &lt;step sequence diagram of the system-in-package (siP) structure according to the fifth embodiment of the present invention.

14 201250949 【主要元件符號說明】 10 系統級封裝結構 11基材 12液晶 13被動元件 100a~100e 系統級封裝結構 110a~110e 基材 120a~120e 液晶 130a~130e 晶粒 131a 〜131e 黏貼材質部 140a~140e 引線連結件 150a〜150e 成型部 160a〜160e 焊球 170b~170e 被動組件 180d、180e 間隙部 181d、181e 黏貼材質部 3110八〜8140八步驟 S110B 〜S150B 步驟 81100^150(：步驟 SllOD 〜S160D 步驟 S110E 〜S160E 步驟 3 1514 201250949 [Description of main components] 10 System-in-package structure 11 Substrate 12 Liquid crystal 13 Passive components 100a~100e System-level package structure 110a~110e Substrate 120a~120e Liquid crystal 130a~130e Die 131a~131e Adhesive material part 140a~ 140e lead connectors 150a to 150e molding portions 160a to 160e solder balls 170b to 170e passive components 180d, 180e gap portions 181d, 181e bonding material portions 3110 8 to 8140 8 steps S110B to S150B step 81100^150 (steps S11OD to S160D) S110E ~ S160E Step 3 15

Claims (1)

201250949 七、申請專利範圍： l種系統級封裝結構，包括：_基材、位於該基材上方的一液晶、 “液sail方的㈤粒、將該基材的上面與該晶粒上面以電性方式連接 的引線連，..。件、以及將該基材上方及該液晶、該晶粒、該引線連結件的 卜P進行鱗的成型部，其中該晶粒的下方還包括用於黏貼於該液晶的 上方的一黏貼材質部。 2. 種系統級封裝結構，包括：一基材、位於該基材上方的液晶、位 於該液晶側部的-被動組件、位於該液晶上方的—晶粒、將該基材的上面 與該晶粒上㈣紐方式連接的—⑽連結件、縣基材上方及該液晶、 該被動7L件、該晶粒、該引線連結件的外部進行鱗的—成型部，其中該 晶粒的下謂包括用於無於該液晶上方的—獅材質部。 3. -種系統級封裝結構，包括：_基材、位於該基材上方的一液晶、 位於該液晶側部的—被動組件、位於該液晶及被動組件上方的—晶粒、將 該基材的上面與綠粒上面以電性方式連接的__引、線連結件、以及將該基 材上方及該液晶、該被動元件、該晶粒、刻線賴件的外部進行麟的 -成型部’其中在該晶粒的下方還包括用於黏貼於該液晶及被動組件上方 的一黏貼材質部。 4. -種系統級封裝結構，包括：一基材、位於該基材上方的一液晶、 位於該液晶側部的-被動組件、位於該液晶上方的—間隙部、位於該間隙 部上方的-晶粒、將該基材的上面與該晶粒上面以電性方式連接的一引線 連結件、以及將該基材上方及該液晶、該被動組件、該間隙部、該晶粒、 該引線連結件的外部進行鱗的—成型部，其中在該_部的下方還包括 16 201250949 一用於黏貼於液晶上方的一黏貼材質部，在該晶粒的下方還包括用於黏貼 於該間隙部上方的另一黏貼材質部。 5· —種系統級封裝結構’包括：一基材、位於該基材上方的一液晶、 位於該液晶側部的一被動組件、位於該液晶及該被動組件上方的一間隙 部、位於該間隙部上方m將該基材的上面與該晶粒上面以電性方 式連接的丨線連結件、以及將該基材上方及該液晶、該被動組件、該間 隙部、該晶粒、該引線連結件的外部進行澆鑄的一成型部，其中在該間隙 部的下方還包括用於黏齡該液晶及該被動組件上方的一黏貼材質部，在 該晶粒的下謂包括用於_於隙部上方的另—雜材質部。 6. 如申請專利範圍第i至5中的任意一項所述的系統級封裝結構，其 中s玄黏貼材質部係為環氧、聚醯亞胺或雙面膠其中一種。 7. 如申吻專利圍第i至5中的任意一項所述的系統級封裝結構，其 中在該基材的下方還包括至少一個焊球。 8. -種系紐縣結構的製造^法，包括下列倾： (A-1)在基材上面的一側安裝液晶； (A-2)通獅貼㈣部而在該液晶上方黏貼晶粒； (A-3)將該基材與晶粒進行引線連結件而以電性方式連接；以及 (Μ在該基材上方及液晶、晶粒、引線連結件的外部形成—成型部。 9. 如申請專利範圍第8所述的系統級封裝結構的製造方法心 述步驟㈣之後，還包括步驟(A_5):在基材下方形成至少—個焊球。 10· -種系統級封褒結構的製造方法，包括下列步驟： (B-1)在基材上面的一側安裝液晶； 17 201250949 (B-2)在該液晶的側部安裝被動組件； (B-3)通過黏貼材質部而在該液晶上方黏貼晶粒； (B-4)將該基材與晶粒進行引線連結件而以電性方式連接以及 (B-5)在該基材上方及液晶、被動組件、晶粒、引線連結件的外部 一成型部。 ’ 11. 如申請專利範圍第10所述的系統級封裝結構的製造方法，其中在 所述步驟(B-5)之後，還包括步驟(B_6):在基材下方形成至少—個焊球。 12. —種系統級封裝結構的製造方法，包括下列步驟： (C-1)在基材上面的一側安裝液晶； (C-2)在該液晶的側部安裝被動組件； (C-3)通過黏貼材質部而在該液晶及被動組件上方黏貼晶粒； (C-4)將該基材與晶粒進行引線連結件而以電性方式連接；以及 (C-5)在該基材上方及液晶、被動組件、晶粒、引線連結件的外$_ 一成型部。 13. 如申請專利範圍第12所述⑽統級封裝結構的製造方法，其中在 所述步驟(C-5)之後，還包括步驟(c_6):在基材下方形成至少—個谭球。 14. 一種系統級封裝結構的製造方法，包括下列步驟： (D-1)在基材上面的一側安裝液晶； (D-2)在該液晶的側部安裝被動組件； (D-3)通過黏貼材質部而在該液晶上方黏貼間隙部； (D-4)通過黏貼材質部而在該間隙部上方黏貼晶粒； (D-5)將該紐與晶粒進行⑽連結件㈣電性方式連接；以及 18 S- 201250949 (D-6)在該基材上方及液晶、被動組件、間隙部、晶粒、引線連結件的 外部形成一成型部。 15. 如申請專利範圍第14所述的系統級封裝結構的製造方法，其中在 所述步驟(D_6)之後’還包括步驟(D_7):在基材下方形成至少_個焊球。 16. —種系統級封裝結構的製造方法，包括下列步驟： (E-1)在基材上面的一側安裝液晶； (E-2)在該液晶的側部安裝被動組件； (E-3)通過_材質部而在雜晶及被她件上方雜間隙部； (E-4)通過黏貼材質部而在該間隙部上方黏貼晶粒； (E-5)將該基材與晶粒進行引線連結件而以電性方式連接；以及 _在該基材上方及液晶、被動組件、間隙部、晶粒、親結件的 外部形成一成型部。 17_如申請專難_ 16所述㈣駿«結構的製造方法’ A中在 所述步卿取後，還包括步離7):在基材下方縣結-個_。 18.如申請專利翻第8、1()、12、14 , .統級«結構的製造方法，其中該黏貼材質料=任意—項所述的系 膠其中—種。 鄕卩係知氧、聚®^胺或雙面 19201250949 VII. Patent application scope: l System-level package structure, including: _ substrate, a liquid crystal above the substrate, “liquid squaring (five) particles, the upper surface of the substrate and the upper surface of the substrate a connection of a lead wire, a member, and a molding portion of the liquid crystal, the crystal grain, and the wire bonding member of the lead bonding member, wherein the lower portion of the die further includes a sticker for bonding a pasting material portion above the liquid crystal. 2. A system-level package structure comprising: a substrate, a liquid crystal above the substrate, a passive component on a side of the liquid crystal, and a crystal above the liquid crystal a granule, a top surface of the substrate and a (10) bond on the die, a (10) bond, a top of the county substrate, and the liquid crystal, the passive 7L piece, the die, and the outer portion of the lead bond are scaled- a molding portion, wherein the lower portion of the die includes a lion material portion that is not used above the liquid crystal. 3. A system-level package structure, comprising: a substrate, a liquid crystal above the substrate, located at the The passive part of the liquid crystal side, located a liquid crystal and a die above the passive component, an electrical connection between the upper surface of the substrate and the green particle, a wire bond, and the substrate and the liquid crystal, the passive component, the The outer portion of the die and the splicing member is formed by a lining-forming portion, wherein an adhesive material portion for adhering to the liquid crystal and the passive component is further disposed under the die. 4. a system-level package structure, The invention comprises: a substrate, a liquid crystal above the substrate, a passive component located on a side of the liquid crystal, a gap portion located above the liquid crystal, a die located above the gap portion, and an upper surface of the substrate a lead connecting member electrically connected to the die, and a molding portion on the substrate and the liquid crystal, the passive component, the gap portion, the die, and the outer portion of the lead connecting member Further, under the _ portion, 16 201250949, an adhesive material portion for adhering to the upper surface of the liquid crystal is further included, and another adhesive material portion for adhering above the gap portion is further included below the die. - germline The package structure includes: a substrate, a liquid crystal above the substrate, a passive component on the side of the liquid crystal, a gap portion above the liquid crystal and the passive component, above the gap portion, a top surface of the substrate electrically connected to the top surface of the die, and the upper portion of the substrate and the liquid crystal, the passive component, the gap portion, the die, and the outside of the lead bond are cast a molding portion, further comprising an adhesive material portion for bonding the liquid crystal and the upper portion of the passive component under the gap portion, and the other portion of the die is included for the other side of the gap portion 6. The system-in-package structure according to any one of claims 1 to 5, wherein the smudged adhesive material portion is one of epoxy, polyimide or double-sided adhesive. The system-in-package structure of any one of clauses 1 to 5, wherein at least one solder ball is further included below the substrate. 8. - The manufacturing method of the New Zealand structure, including the following tilting: (A-1) Mounting liquid crystal on one side of the substrate; (A-2) Passing the lion paste (four) and pasting the crystal grains on the liquid crystal (A-3) electrically connecting the substrate and the die to the lead bonding member; and (forming the molding portion above the substrate and outside the liquid crystal, the crystal grain, and the lead bonding member. The manufacturing method of the system-in-package structure according to claim 8 is followed by the step (4), further comprising the step (A_5): forming at least one solder ball under the substrate. 10· - System level sealing structure The manufacturing method comprises the following steps: (B-1) mounting a liquid crystal on one side of the substrate; 17 201250949 (B-2) mounting a passive component on a side of the liquid crystal; (B-3) by pasting the material portion (B-4) electrically bonding the substrate and the die with a wire bond and (B-5) over the substrate and the liquid crystal, passive component, die, lead A molded portion of the outer portion of the joint. ' 11. A method of manufacturing a system-in-package structure according to claim 10 After the step (B-5), the method further includes the step (B_6): forming at least one solder ball under the substrate. 12. A method for manufacturing a system-level package structure, comprising the following steps: (C- 1) mounting liquid crystal on one side of the substrate; (C-2) mounting a passive component on the side of the liquid crystal; (C-3) pasting the die above the liquid crystal and the passive component by pasting the material portion; -4) electrically connecting the substrate to the die with a wire bond; and (C-5) over the substrate and outside the liquid crystal, passive component, die, lead bond 13. The method according to claim 12, wherein the step (C-5) further comprises the step (c_6): forming at least one Tan ball under the substrate. 14. A method of fabricating a system-in-package structure comprising the steps of: (D-1) mounting a liquid crystal on one side of a substrate; (D-2) mounting a passive component on a side of the liquid crystal; (D-3) Applying a gap portion to the liquid crystal by pasting the material portion; (D-4) pasting the gap portion by pasting the material portion (D-5) electrically connecting the button to the die (10) connector (4); and 18 S-201250949 (D-6) above the substrate and the liquid crystal, passive component, gap portion, die, A method of manufacturing a system-in-package structure according to claim 14, wherein after the step (D_6), the step (D_7) is further included: under the substrate Forming at least _ solder balls. 16. A method of manufacturing a system-level package structure, comprising the steps of: (E-1) mounting a liquid crystal on one side of a substrate; (E-2) mounting on a side of the liquid crystal Passive component; (E-3) through the _ material part in the impurity crystal and the gap part above her; (E-4) by pasting the material part and pasting the die above the gap; (E-5) The substrate and the die are electrically connected by a wire bond; and a molded portion is formed on the substrate and outside the liquid crystal, the passive component, the gap, the die, and the bonding member. 17_ If the application is difficult _ 16 (4) Jun «Structure manufacturing method' A in the step taken after the step, also includes step 7): under the substrate county - _. 18. For example, if the patent application is turned over, the method of manufacturing the structure of the structure, wherein the adhesive material is any one of the rubbers described in the item.鄕卩 system oxygen, poly-amine or double-sided 19
TW101118807A 2011-06-15 2012-05-25 System-in-packeage (sip) and manufacturing method thereof TWI553795B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR20110057838 2011-06-15

Publications (2)

Publication Number Publication Date
TW201250949A true TW201250949A (en) 2012-12-16
TWI553795B TWI553795B (en) 2016-10-11

Family

ID=47287996

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101118807A TWI553795B (en) 2011-06-15 2012-05-25 System-in-packeage (sip) and manufacturing method thereof

Country Status (3)

Country Link
KR (1) KR101191075B1 (en)
CN (1) CN102842540A (en)
TW (1) TWI553795B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102592640B1 (en) 2016-11-04 2023-10-23 삼성전자주식회사 Semiconductor package and method of manufacturing the semiconductor package
KR102298516B1 (en) 2020-02-28 2021-09-27 주식회사 웨이브피아 Lead frame of hermetic RF chip package for incorporating the function of impedance matching

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6673441B1 (en) * 1999-06-18 2004-01-06 Hitachi Chemical Company, Ltd. Adhesive, adhesive member, interconnecting substrate for semiconductor mounting having adhesive member, and semiconductor device containing the same
JP2003003134A (en) * 2001-06-20 2003-01-08 Japan Gore Tex Inc Sheet for ic chip adhesion and ic package
US7064430B2 (en) * 2004-08-31 2006-06-20 Stats Chippac Ltd. Stacked die packaging and fabrication method
KR100700983B1 (en) * 2005-07-06 2007-03-29 삼성전자주식회사 Manufacturing method for board assembly
US7622325B2 (en) * 2005-10-29 2009-11-24 Stats Chippac Ltd. Integrated circuit package system including high-density small footprint system-in-package
KR100780690B1 (en) 2006-03-03 2007-11-30 주식회사 하이닉스반도체 Method of manufacturing stack package
JP2010010480A (en) 2008-06-27 2010-01-14 Sanyo Electric Co Ltd Semiconductor module and method of manufacturing the same, and portable apparatus
JP2010103802A (en) 2008-10-24 2010-05-06 Epson Toyocom Corp Electronic device

Also Published As

Publication number Publication date
CN102842540A (en) 2012-12-26
TWI553795B (en) 2016-10-11
KR101191075B1 (en) 2012-10-16

Similar Documents

Publication Publication Date Title
TWI576927B (en) Semiconductor device and manufacturing method thereof
TW201840256A (en) Seal for microelectronic assembly
US7745918B1 (en) Package in package (PiP)
US20130203200A1 (en) Fabrication method of package structure having mems element
TW200950050A (en) Semiconductor package device, semiconductor package structure, and method for fabricating the same
TW200933764A (en) Integrated circuit package system with package integration
TW200834938A (en) Image sensor package with die receiving opening and method of the same
TW200834876A (en) Multi-chips package and method of forming the same
TW200818435A (en) Metal core foldover package structures, systems including same and methods of fabrication
TW200836310A (en) Wafer level image sensor package with die receiving cavity and method of making the same
TW200903746A (en) Image sensor package utilizing a removable protection film and method of making the same
US8288189B2 (en) Package structure having MEMS element and fabrication method thereof
TWI320963B (en) Method of manufacturing hybrid structure of multi-layer substrates and hybrid structure thereof
TW201142998A (en) System-in-package
TW200913194A (en) Semiconductor package and manufacturing method thereof
US20170113926A1 (en) Mems chip scale package
TWI587413B (en) Solder flow-impeding plug on a lead frame
TW201250949A (en) System-in-packeage (SiP) and manufacturing method thereof
US20080157398A1 (en) Semiconductor device package having pseudo chips
TW201112387A (en) Multi-chip package and method of forming multi-chip package
TWI547217B (en) Microelectronic package and method of manufacturing same
US20080265393A1 (en) Stack package with releasing layer and method for forming the same
CN103208467B (en) Package module with embedded package and method for manufacturing the same
CN103311211A (en) Multi-chip package
TW201106458A (en) Package structure with cavity and manufacturing method thereof

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees