201250268 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種為内置複數個D A轉換器、且將作為 各DA轉換器之輸出之複數階之階度電壓自各自對應之輸 出如> 子輸出之構成之半導體裝置（例如，液晶驅動器等）及 其檢查方法。 【先前技術】 近年來，由於圖像顯示裝置之技術之提高，可顯示精密 之CG(電腦•圖形）圖像、充滿身臨其境之感之高精度之自 然圖像等。然而，希望顯示更高階度、更高精度之圖像之 要求日益增高《在作為液晶顯示裝置之液晶面板中，對相 對顯示圖像之進一步之高精度化之要求亦提高，搭載於液 晶面板上之液晶驅動器之多輸出化、多階度化正逐漸進 步〇201250268 VI. Description of the Invention: [Technical Field] The present invention relates to an output of a gradation voltage of a complex order which is a built-in plurality of DA converters and which is an output of each DA converter, such as > A semiconductor device (for example, a liquid crystal driver or the like) having a sub-output and an inspection method thereof. [Prior Art] In recent years, due to the improvement of the technology of the image display device, it is possible to display a sophisticated CG (computer/graphic) image, a natural image with high precision that is immersive, and the like. However, there is an increasing demand for displaying images of higher order and higher precision. In the liquid crystal panel as a liquid crystal display device, the requirement for further high precision of the relative display image is also improved, and it is mounted on the liquid crystal panel. The multi-output and multi-stepization of liquid crystal drivers are gradually improving.
為進行多階度顯示，液晶驅動器之各輸出分別内置DA 轉換器而輸出階度電壓。圖3中顯示一般之液晶驅動器之 方塊構成圖。 圖3所示之液晶驅動器20係將對應各輸出之輸入rgb資 料（6位元以上/丨輸出）基於時脈(：{：而予以鎖存，充入取樣 °己隐體23 ’再基於掃描控制信號LS而充入保持記憶體24， 並經由位準轉換器25而向DA轉換器26輸入。 DA轉換器26於每次輸出選擇階度位準，經由各每次輸 出具有之輪出放大器27,而將電壓生成電路28(利用階梯 電阻或電容器等生成期望之電壓）中生成之各階度位準輸 163224.doc 201250268 出。作為上述電壓生成電路28而使用之階梯電阻如圖4所 示 般而5係藉由將該階梯電阻進行電阻分割而於各階 度生成期望之階度位準。 關於輸入資料，6位元DA轉換器之情形中可進行64階度 顯示，8位元DA轉換器之情形中可進行256階度顯示，1〇 位兀DA轉換器之情形中可進行丨〇24階度之顯示。 伴隨液晶驅動器之多階度化，用以確保液晶面板之顯示 等級之液晶驅動器之階度位準之測試，高精度測定係不可 缺少。即，有必要對自DA轉換器輸出之各階度電壓值是 否皆為正確電壓值，或各DA轉換器間輸出之階度電壓值 疋否分別相互均勻，進行進一步高精度測試。例如，設被 測試裝置（Device Under Test)之電源電壓相同時，有必要 藉由將輸出端子之性能自256階度4倍提高至1〇24階度，將 測定精度4倍高精度化。 以下，以作為測試對象之被測試裝置為例，説明輸出端 子數為m下，内置用以選擇^组之電壓位準而輸出至各輸出 端子之η階度DA轉換器之液晶驅動器用LSI之階度位準之 測試方法。 圖5係顯示利用高精度電壓計之階度測試方法（系統構 成）之簡略圖。該系統係由被測試裝置丨丨及半導體試驗裝 置（測試器）12構成》 測试器12對被測試裝置11輸入特定之輸入信號，判定自 被測試裝置11輸出之信號之良否。圖5之系統構成中，使 用測試器12將特定之輸入向被測試裝置u供給，即，向液 I63224.doc 201250268 曰曰驅動器供給輸入信號，而輸出第丨階度之階度電壓位 準。 其後，使用測試器12中内置之高精度模擬電壓測試器 15 ’測定全輸出Y1〜Ym(m輸出）之第1階度之階度電壓值， 並將其測定結果逐次儲存於測試器12中内置之記憶體13 中。 經η階度地重複該操作，最終將全輸出、全階度之資料 儲存於記憶體13中，其結果，儲存輸出狀態數mxn個之資 料。 相對儲存於記憶體13中之資料，使用内置於測試器12中 之運算裝置14進行特定之運算，可進行各輸出端子之各階 度電壓值之偏差量或各輸出端子間之階度電壓值之均勻性 之測試》 上述測試結果之一例如圖6所示。圖6中，例如相對第χ3 階度之理想電壓值，雖圖示有輸出丨〜輸出γ之各個電壓測 定值，但須檢查該值相對理想電壓值有多少偏差（階度偏 差測試），及，電壓測定值之上限值（ΜΑχ值）及下限值 (ΜΙΝ值）之差為何種程度（均勻性）。 該種液晶驅動器之測試中，隨著多輸出化、多階度化之 進程，促使資料之獲取量之增加及與之伴隨之資料處理時 間之增加’導致測s式時間大幅增加。又，由於階度數量之 增加，有必要對階度電壓值進行更高精度之測定，若測試 時間更進一步增加’則需要搭載高精度之電愿測試器之高 價半導體試驗裝置（測試器）。 I63224.doc 201250268 另一方面’由於輸出數量之增加’亦需要半導體測試裝 載（測試器）之多腳化，逐漸推動測試器之高價格化。 下述之專利文獻1中所示之液晶驅動器之構成為：内置 有測試電路’預燒控制電路基於經由測試器而供給之外部 時脈信號TESTCK、及測試啟動信號TESTEN，而生成測試 用之輸入信號並供給至液晶驅動器。 [先前技術文獻].For multi-level display, each output of the liquid crystal driver has a built-in DA converter to output a gradation voltage. Fig. 3 is a block diagram showing a general liquid crystal driver. The liquid crystal driver 20 shown in FIG. 3 is based on the input rgb data (6 bits or more / 丨 output) corresponding to each output based on the clock (: {: is latched, charged into the sample ° hidden body 23 ' and then based on the scan The control signal LS is charged into the holding memory 24, and is input to the DA converter 26 via the level converter 25. The DA converter 26 outputs a selected gradation level each time, and each of the outputs has a wheel-out amplifier. 27, and each of the gradation levels generated by the voltage generating circuit 28 (using a step resistor or a capacitor to generate a desired voltage) is output 163224.doc 201250268. The step resistor used as the voltage generating circuit 28 is as shown in FIG. In general, the 5 series generates a desired gradation level at each gradation by performing resistance division on the step resistor. Regarding the input data, a 64-bit display can be performed in the case of a 6-bit DA converter, and 8-bit DA conversion is performed. In the case of the device, 256-degree display can be performed, and in the case of a 1-inch 兀DA converter, 丨〇24-order display can be performed. With the multi-step of the liquid crystal driver, the liquid crystal panel is used to ensure the display level of the liquid crystal panel. Drive order The level measurement test, high-precision measurement system is indispensable. That is, it is necessary to determine whether the voltage values of the respective gradations output from the DA converter are correct voltage values, or whether the gradation voltage values of the outputs between the DA converters are respectively Uniformity of each other for further high-precision testing. For example, if the power supply voltage of the Device Under Test is the same, it is necessary to increase the performance of the output terminal from 256 steps to 1〇24. The measurement accuracy is 4 times higher. The following is an example of the device under test as a test object. The number of output terminals is m, and the built-in voltage level for selecting the group is output to the η-order DA of each output terminal. A test method for the gradation level of the LSI for a liquid crystal driver of a converter. Fig. 5 is a schematic diagram showing a gradation test method (system configuration) using a high-precision voltmeter, which is tested by a device under test and a semiconductor test. The device (tester) 12 constitutes a tester 12 that inputs a specific input signal to the device under test 11, and determines whether the signal output from the device under test 11 is good or not. In the system configuration of Fig. 5, The specific input is supplied to the device under test u by the tester 12, that is, the input signal is supplied to the liquid I63224.doc 201250268 曰曰 driver, and the gradation voltage level of the second gradation is output. Thereafter, the tester 12 is used. The high-precision analog voltage tester 15' built in is used to measure the first-order gradation voltage value of the full output Y1 to Ym (m output), and the measurement result is sequentially stored in the memory 13 built in the tester 12. The operation is repeated by η degree, and finally the data of the full output and the full scale is stored in the memory 13. As a result, the data of the output state number mxn is stored. The data stored in the memory 13 is used. The arithmetic unit 14 built in the tester 12 performs a specific calculation to perform a test for the deviation of each gradation voltage value of each output terminal or the uniformity of the gradation voltage value between the output terminals. Figure 6 shows. In FIG. 6, for example, for the ideal voltage value of the third rd order, although the voltage measurement values of the output 丨 to the output γ are shown, it is necessary to check how much the value deviates from the ideal voltage value (the gradation deviation test), and What is the difference (uniformity) between the upper limit value (ΜΑχ value) and the lower limit value (ΜΙΝ value) of the voltage measurement value. In the test of the liquid crystal driver, as the multi-output and multi-step process progresses, the increase in the amount of data acquisition and the accompanying increase in data processing time have led to a significant increase in the measurement time. Further, since the number of gradations increases, it is necessary to measure the gradation voltage value with higher precision, and if the test time is further increased, a high-priced semiconductor test device (tester) equipped with a high-precision electric tester is required. I63224.doc 201250268 On the other hand, 'the increase in the number of outputs' also requires the multi-legacy of the semiconductor test load (tester), which gradually pushes the price of the tester. The liquid crystal driver shown in the following Patent Document 1 has a built-in test circuit. The burn-in control circuit generates an input for testing based on the external clock signal TESTCK and the test enable signal TESTEN supplied via the tester. The signal is supplied to the liquid crystal driver. [Previous Technical Literature].
[專利文獻] [專利文獻1]曰本特開2008-4778號公報 【發明内容】 [發明所欲解決之問題] 如上所述’隨著液晶驅動器之階度數量之增加及輸出數 量之增加，被測試裝置11之理想輸出電壓與實際之液晶驅 動器專之輸出電壓之偏差電壓，及相對端子間偏差（均 一性）規定之樣式變得嚴格，一般64階度樣式為±2〇爪乂以 下，256階度樣式為土1〇 mV以下，隨著進一步階度數量之 增加變為數mV以下，高精度測定不可缺少。 如此’若階度數量增加則在測試器之高功能化（高精度 測定）之同時會招致測試時間之增大，進而因輸出數量增 加而需要測試器之多腳化。結果，如此，伴隨著階度數量 及輸出數量之增加，促進了測試器之高價格化，且測試時 間之增加招致測試處理能力之降低，逐漸推進了測試费用 之提向。 種不會招致測試 本發明鑒於上述狀況，其目的係提供一 163224.doc 201250268 器之高功能化或多腳化、及測試處理能力之降低，而可進 行階度電壓值之檢查之半導體裝置及其檢查方法。 [解決問題之技術手段] 為達成上述目的，本發明之半導體裝置構成為包含複數 個輸出端子’且可對每個上述輸出端子供給複數階段之階 度電壓’其特徵為具備： 電壓生成電路’其生成用以對上述輸出端子各者供給之 上述複數階段之階度電壓； 輸入測試用時脈信號之測試用時脈輸入端子； 輸入測試㈣制信號之測試用控制信號輸入端子； 測試控制電路’其基於上述測試用時脈信號、及上述測 試用控制信號’生成用以選擇上述電壓生成電路所生成之 上述複數階段之階度電壓中至少任一電壓之輸入信號；及 階度偏差判定電路，其將上述階度電壓與自外部測試電 路供給之參考電壓進行比較，將其比較結果輸出至階度偏 差判定輸出端子；且 依據上述輸入信號之上述階度電壓被供給至每個上述輸 出端子； 上述階度偏差判定電路進行如下判定：供給至特定之上 述輸出端子之上述電壓生成電路所生成之特定之上述階度 電壓是否在特定之電壓範圍内。 上述特徵之半導體裝置，進而較好的是具備切換開關， 其依據上述測試用控制信號，將輸出至上述輸出端子之上 述階度電壓，切換為對上述階度偏差判定電路之輸入。 163224.doc 201250268 上述特徵之半導體裝置進而較好的是，上述測試控制電 具備自外部輸入測試用輸入信號之測試用輸入端子 具備： 將用以選擇對每個上述輸出端子供給之上述階度電壓之 上述輸人信號，在上述測試用輸人信號、與基於上述測試 用時脈信號及上述測試用控制信號而生成之信號之間進行 切換之機構。 —上述特徵之半導體裝置進而較好的是’上述階度偏差判 定輸出端子之輸出結果’係作為高位準或低位準之任一者 之2值資訊而輸出。 為達成上述目的，本發明之半導體裝置之檢查方法之特 徵為：彡係在上述特徵之半導體裝置中，$行上述電壓生 成電路所生成之上述階度電壓是否在特定之電壓範圍内之 測試者，且具備： 將上述測試用時脈信號經由外部測試器而輸入至上述測 試用時脈輸入端子之步驟； 將上述測試用控制信號經由外部測試器而輸入至上述測 試用控制信號輸入端子之步驟； 基於上述測試用時脈信號、及上述測試用控制信號，由 上述測試控制電路生成用以依序選擇上述複數階段之階度 電壓並供給至上述輸出端子之各者之上述輸入信號之步 驟； 由上述階度偏差判定電路將該階度電壓與自外部測試器 供給之參考電壓進行比較’將其比較結果輸出至階度偏差 163224.doc 201250268 判定輸出端子之步驟；及 以外部測試器監視上述階度偏差判定輸出端子之輸出結 果之步驟；且 針對每個上述階度電壓進行該階度電壓是否在特定之電 壓範圍内之偏差測試、及進行每個上述輸出端子之上述階 度電壓之偏差之測試。 [發明之效果] 本發明之半導體裝置，階度偏差判定電路對是否可利用 電壓生成電路而生成之階度電壓被正常輸出，實際使用狀 態（例如若為液晶驅動器，則液晶面板）中可無問題使用， 進行比較而實施可w定，而對階度偏差判定輸出端子輸 出4可否判定結果（例如高位準之情形為不良，低位準之 情形為良品）。 藉此由於半導體裝置自身進行階度電Μ與理想電;§ ^考電㊉之電Μ比較’故無須用高精度之測定裝置（測試 藉由監視階度偏差職輸出端子之輸出狀態，即可 實現與先則同等之各輸出端子之各階度電壓值之偏差量或 各輸出端子間之階度電壓值之均—性測試。 t根據本發明’可實現不會招致測試器之高功能化 ^ 〗測5式處理能力之降低’而可進行階度電麼值 之檢查之半導體裝置及其檢查方法。 【實施方式】 163224.doc 201250268 係將内置DA轉換器之多階度、多輸出之液晶驅動器之情 形為例來說明’但本發明不限於該構成。本發明裝置3〇具 有：液晶驅動器20、測試控制電路3 1、階度偏差判定電路 33、及輸出切換開關34。 液晶驅動器20包含位移轉換器2丨、鎖存電路22(未圖 示）、取樣記憶體23、保持記憶體24、位準轉換器25、DA 轉換器26、輸出放大器27、及電壓生成電路28，係如圖3 所示與先前構成相同之構成。 液晶驅動器20係如上所述，將對應各輸出之輸入R(JB資 料（6位元以上/1輸出）基於時脈CK而予以鎖存，將每個輸 出數量之資料充入取樣記憶體23，基於掃描控制信號^而 充入保持記憶體24，經由位準轉換器25而向DA轉換器％ 輸入。DA轉換器26係於每次輸出選擇依據輸入RGB資料 之階度位準，再經由各個每次輸出具有之輸出放大器 27(27a〜27m)，而將電壓生成電路28中所生成之各階度位 準輸出。 此時’藉由液晶驅動器之驅動方式鄰接之液晶系輸出大 致區分為，向VH側位準與儿側位準反轉之點反轉驅動方 式、與選擇同1度位準之時輸出相同料之線反轉驅動 方式2類1省略關於㈣反轉_與⑽反轉驅動之說 明’但之後之說明假定為點反轉驅動。 液晶驅動器20係接受時脈信號CK、啟動脈衝信號SP、 極性控制信號REV、掃描控制信號Ls等之各種控制信號、 或顯示信號即RGB輸人，而進行其動作。因此，液晶驅動 163224.doc 201250268 器20需要多個信號輸人端子。於液晶驅動器之動作測試 時，若欲將該等多個信號自外部供給，則如上所述，用以 供信號輸入之腳數增多，其結果將招致測試之多腳化或測 試處理能力之降低。 為此，本實施形態中，測試控制電路3 1構成為，基於輸 入至測試用時脈輸入端子35之測試用時脈信號testck、 及輸入至測試用控制信號輸入端子36之測試用控制信號 TESTEN，由自身生成用於動作測試之各種信號。又，作 為該測試控制電路3 1之構成，因可利用例如專利文獻i之 圖2所記載之構成，故詳細之說明從略。 . 然而，測試控制電路31亦可另外設置用以接受該各種控 制k號之測試用輸入端子。該情形，測試控制電路3丨係將 自該測試用輸入端子輸入之測試用輸入信號直接作為用於 液BB驅動器20之動作測試之信號而使用。藉此，可構成為 切換使用基於測試用時脈信號TESTCK、及測試用控制信 號TESTEN而由自身生成用於動作測試之各種信號之情 形，與基於來自外部之測試用輸入信號而進行動作測試之 情形。 測試控制電路31係基於測試用控制信號TESTEN、及測 試用時脈信號TESTCK，選擇由電壓生成電路28生成之階 度電壓中之任一者’經由DA轉換器26、輸出放大器 27(27a〜27m)而生成用以輸出至各液晶輸出端子 29(29a〜29m)之輸入信號，並向液晶驅動器2〇輸出。測試 控制電路3 1可依據測試用時脈信號TESTCK之輸入數量（時 163224.doc 201250268 脈數量），而依序設定1階度至n階度之任意之階度電壓。 本實施形態中，測試控制電路3 1係基於測試用控制信號 TESTEN、及測試用時脈信號TESTCK，生成使該階度電壓 依序增加或減少而輸出全階度之輸入信號。 階度偏差判定電路33例如由比較器構成，於輸入端子之 一端’經由輸出切換開關34之切換開關而輸入放大器 27a〜27m之各輸出電壓，於另一端，由半導體試驗裝置（測 試器）32經由參考電壓輸入端子37而輸入階度電壓之理想 電壓作為參考電壓。階度偏差判定電路33比較輸入至該一 端之由放大器輸出之階度電壓、與輸入至該另一端之階度 電壓之理想電壓，將其比較結果輸出至階度偏差判定輸出 端子38。 輸出切換開關3 4於每個輸出放大器上設置切換開關，其 根據測試用控制信號TESTEN，將輸出放大器27a〜27m之 各輸出電壓之輸入目的地在對應之任一液晶輸出端子 29a〜29m與階度偏差判定電路33之輸入端子之-端之間切 換。 半導體裝置30經由端子35〜38而與半導體試驗裝置（測試 器）32相連接，且可進行由電壓生成電路28生成之階度電 麈與各輸出端子之理想電壓值之偏差、或各輸出端子間之 階度電壓值之均一性之檢查。 以下，茲參照圖2說明本發明之半導體裝置3〇之檢查方 法。圖2係顯示本發明之檢查方法之實施流程之時序圖。 將半導體裝置30之各端子35〜38 ’分別與半導體試驗裝 163224.doc •12- 201250268 置32連接，為使測試控制電路31動作，自半導體試驗裳置 32，經由測試用時脈輸入端子35輸入測試用時脈信號 TESTCK，及，經由測試用控制信號端子刊輸入測試用控 制信號TESTEN，而啟動測試用控制信號（此處為高位 準）。 接受此信號，測試控制電路31基於測試用時脈信號 TESTCK、及測試用控制信號TESTEN，相對各輸出放大器 27，使階度電壓自！階度依序增加至n階度而生成輸出全階 度之輸入信號。 此時，各輸出放大器27之輸出目的地係利用輸出切換開 關34而連接於階度偏差判定電路33之輸入端子。再者，利 用輸出切換開關34内之各個切換開關，將階度偏差判定電 路33之輸入端子之一端上連接之輸出放大器27之輸出階度 電壓，根據測試用時脈信號TESTCK而自輸出放大器27a依 序切換至27m。另一方面，階度偏差判定電路3 3之輸入端 子之另一端’有自半導體試驗裝置32供給之階度電壓之理 想電壓作為參考電壓而輸入，階度偏差判定電路3 3，係根 據測試用時脈信號TESTCK，將輸出放大器27之各輸出階 度電塵與該理想電壓之比較’自輸出放大器27&依序切換 至 27m。 圖2中’根據通過測試控制電路3 1之液晶驅動器20之控 制’對各輸出放大器27輸出有階度電壓之第1階度之電壓 時’參考電壓輸入端子37中有第1階度之階度電壓之理想 電壓自半導體試驗裝置32供給。階度偏差判定電路33將向 163224.doc 13 201250268 各輸出放大|§27輪中夕眘+ 之貫際之第1階度之階度電壓與自半 導體5式驗裝置3 2供給之採相愈厭^r L Aa ^ 內、，σ之理想電壓作比較，實施相對輸出放 大器27a〜27m所輸出之第】階度之各個階度電壓，該階度電 壓相對该理想電壓是否在特定之電壓範圍内之判定，且將 判定結果向階度偏差判定輸出端子38輸出。 此處，該判定結杲，判定結果在該電壓範圍内之情形為 低位準，在該電壓範圍以外之情形為高位準，並作為低位 準或同位準之2值資訊，向階度偏差判定輸出端子38輸 出。藉由監視階度偏差判定輸出端子3 8之輸出電壓，可識 別各輸出放大器27a〜27m之輸出階度電壓之第i階度有無問 題。 ， 然後’測試控制電路3 1以使各輸出放大器27a〜27m輸出 第2階度之階度電壓之方式控制液晶驅動器2〇，藉由輸出 切換開關34内之各切換開關之控制，進行相對輸出放大器 27a~27m所輸出之各個第2階度之階度電壓，該階度電壓相 對理想電壓是否在特定之電壓範圍内之判定，並將判定結 果向階度偏差判定輸出端子38輸出》 藉由依序重複至第η階度之階度電壓，可進行半導體裝 置30之寫入階度電壓之偏差測試，及均一性測試。 以上，本發明之半導體裝置30，藉由包含有測試控制電 路3 1、階度偏差判定電路33、及輸出切換開關34，可在多 輸出、多階度化進展之液晶驅動器LSI等之半導體積體電 路之檢查中，生成用以使作為被測試裝置之半導體裝置30 自身生成測試用之階度電壓之輸入信號，且被測試裝置亦 163224.doc -14- 201250268 會判定所生成之階度雷愚僧相料 X电壓值相對理想電壓（參考電壓）值其 偏差在允許範圍内，且僅蔣宜立丨中 值將其判疋結果輸出至半導體試驗 裝置（測試器）32，進行自丕划中 m , 疋仃民否判疋。因此，半導體試 (測試器）32與被測試裝置3〇僅供給電源或少數之控制信號 . 及判定結果’藉由傳達即可實現階度偏差之測試。 . 據此’不僅不需要先前之測試中所必要之高功能之半導 體試驗裝置’亦不依存輸出數量即可實現多數個同時測 定。 因可期待上述之效果，故今後多輸出、多階度化越發增 多之情形中仍無須投資高價之半導體試驗裝置，可實現多 數個同時測定，因此大大有助於測試費用之降低。 [產業上之利用可能性] 本發明可利用於液晶驅動器等之半導體裝置生成之階度 電Μ之階度偏差之檢查、及檢查方法。 【圖式簡單說明】 圖1係本發明之半導體裝置之簡略之電路構成圖。 圖2係顯示本發明之半導體裝置之檢查方法之實施流程 之時序圖。 圖3係進行多階度顯示之液晶驅動器之方塊構.成圖。 圖4係液晶驅動器中，階度電壓之產生所用之階梯電阻 電路之一例。 圖5係顯示使用高精度電壓表之階度測試方法（系統構 成）之簡略圖。 圖6係顯示液晶驅動器之階度測試之内容之圖》 I63224.doc -15- 201250268 【主要元件符號說明】 11 被測試裝置（DUT) 12 半導體試驗裝置（測試器） 13 記憶體 14 運算裝置 15 高精度模擬電壓測試器 20 液晶驅動Is 21 位移暫存器 22 鎖存電路 23 取樣記憶體 24 保持記憶體 25 位準轉換器 26 DA轉換器 27 輸出放大器 27a 〜27m 輸出放大器 28 電壓生成電路 29a 〜29m 液晶輸出端子 30 本發明之半導體裝置 31 測試控制電路 32 半導體試驗裝置（測試器） 33 階度偏差判定電路 34 輸出切換開關 35 測試用時脈輸入端子 36 測試用控制信號輸入端子 163224.doc -16- 201250268[Patent Document 1] [Patent Document 1] JP-A-2008-4778 SUMMARY OF INVENTION [Problems to be Solved by the Invention] As described above, "as the number of gradations of the liquid crystal driver increases and the number of outputs increases, The deviation between the ideal output voltage of the device under test 11 and the actual output voltage of the liquid crystal driver, and the deviation between the terminals (uniformity) are strict, and the general 64-order pattern is ±2〇〇, The 256-order pattern is below 1 〇mV, and as the number of further gradations increases to several mV or less, high-precision measurement is indispensable. If the number of gradations increases, the tester's high functionality (high-precision measurement) will increase the test time, and the number of outputs will increase the number of testers. As a result, with the increase in the number of orders and the number of outputs, the high price of the tester is promoted, and the increase in test time leads to a decrease in test processing capability, and the test cost is gradually advanced. In view of the above situation, the object of the present invention is to provide a semiconductor device capable of checking the gradation voltage value and providing a high functionality or multi-stepping of the 163224.doc 201250268 and a reduction in test processing capability. Its inspection method. [Means for Solving the Problems] In order to achieve the above object, a semiconductor device of the present invention is configured to include a plurality of output terminals ′ and to supply a gradation voltage of a plurality of stages to each of the output terminals, which is characterized by: a voltage generating circuit And generating a gradation voltage for supplying the plurality of stages of the output terminal; inputting a test clock input terminal for testing a clock signal; and inputting a test control signal input terminal for testing the signal of the test (4); testing the control circuit 'Generating an input signal for selecting at least one of the plurality of gradation voltages of the plurality of stages generated by the voltage generating circuit based on the test clock signal and the test control signal; and the gradation deviation determining circuit Comparing the gradation voltage with a reference voltage supplied from an external test circuit, and outputting the comparison result to the gradation deviation determination output terminal; and supplying the gradation voltage according to the input signal to each of the output terminals The above-described gradation deviation determination circuit performs the following determination: supply to special On said output terminal of said voltage generating circuit generates the above-described specific gradation of the voltage is within the specified voltage range. Further preferably, the semiconductor device of the above aspect includes a changeover switch for switching the gradation voltage outputted to the output terminal to the input of the gradation deviation determination circuit in accordance with the test control signal. Further, in the semiconductor device according to the above aspect, preferably, the test input circuit includes a test input terminal for inputting a test input signal from the outside, and the test input terminal is configured to select the gradation voltage supplied to each of the output terminals. The input signal is a mechanism for switching between the test input signal and a signal generated based on the test clock signal and the test control signal. Further, in the semiconductor device of the above feature, it is preferable that the output result of the gradation deviation determination output terminal is output as binary information of either the high level or the low level. In order to achieve the above object, the semiconductor device inspection method of the present invention is characterized in that, in the semiconductor device of the above characteristics, the tester of whether the gradation voltage generated by the voltage generating circuit is within a specific voltage range is And a step of: inputting the test clock signal to the test clock input terminal via an external tester; and inputting the test control signal to the test control signal input terminal via an external tester And generating, by the test control circuit, a step of sequentially selecting the gradation voltage of the plurality of stages and supplying the input signal to each of the output terminals based on the test clock signal and the test control signal; The gradation deviation determining circuit compares the gradation voltage with a reference voltage supplied from an external tester', and outputs the comparison result to the gradation deviation 163224.doc 201250268, the step of determining the output terminal; and monitoring the above by an external tester The step of determining the output of the output terminal by the gradation deviation; The gradation for each of the gradation voltage to bias voltage is within a certain voltage range of the test, and for the deviation of the gradation voltage output terminal of each of said test. [Effects of the Invention] In the semiconductor device of the present invention, the gradation deviation determining circuit outputs the gradation voltage generated by the usable voltage generating circuit normally, and the actual use state (for example, in the case of a liquid crystal driver, the liquid crystal panel) The problem is used, and the comparison can be performed to determine whether the gradation deviation determination output terminal output 4 can determine the result (for example, the case of a high level is bad, and the case of a low level is good). Therefore, since the semiconductor device itself performs the stepped electric power and the ideal electric power; § ^the electric power of the ten electric power is compared, so there is no need to use a high-precision measuring device (the test can be performed by monitoring the output state of the output terminal of the step deviation). Achieving the deviation of the gradation voltage values of the output terminals or the gradation voltage values between the output terminals of the output terminals, which are equivalent to the prior art, can be achieved according to the present invention, and the high functionality of the tester is not achieved. 〗 〖Measurement of the reduction of the processing power of the type 5, and the semiconductor device capable of checking the value of the gradual value and the inspection method thereof. [Embodiment] 163224.doc 201250268 is a multi-step, multi-output liquid crystal with built-in DA converter The case of the driver is described as an example. However, the present invention is not limited to this configuration. The device 3 of the present invention includes a liquid crystal driver 20, a test control circuit 31, a gradation deviation determination circuit 33, and an output changeover switch 34. The liquid crystal driver 20 includes Displacement converter 2, latch circuit 22 (not shown), sample memory 23, holding memory 24, level converter 25, DA converter 26, output amplifier 27, and voltage generation The circuit 28 has the same configuration as the previous configuration as shown in Fig. 3. The liquid crystal driver 20 locks the input R (JB data (6 bits or more / 1 output) based on the clock CK corresponding to each output as described above. The data of each output quantity is charged into the sampling memory 23, and is loaded into the holding memory 24 based on the scanning control signal ^, and is input to the DA converter via the level converter 25. The DA converter 26 is attached to each. The secondary output selection is based on the gradation level of the input RGB data, and is outputted by the output amplifiers 27 (27a to 27m) each of the outputs, and the gradation levels generated in the voltage generating circuit 28 are outputted. The output of the liquid crystal system adjacent to the driving method of the liquid crystal driver is roughly divided into a dot inversion driving method in which the VH side level and the child side level are reversed, and a line inversion in which the same material is output when the same level is selected. The driving method 2 class 1 omits the description of the (4) inversion _ and (10) inversion driving. However, the following description assumes the dot inversion driving. The liquid crystal driver 20 receives the clock signal CK, the start pulse signal SP, the polarity control signal REV, Scan control letter Ls and other control signals, or display signals, that is, RGB input, perform their operations. Therefore, the liquid crystal driver 163224.doc 201250268 20 requires a plurality of signal input terminals. When the liquid crystal driver is tested for operation, When a plurality of signals are supplied from the outside, as described above, the number of pins for inputting signals is increased, and as a result, the test is multi-legged or the test processing capability is reduced. To this end, in the present embodiment, the test control circuit is 3 1 is configured to generate various signals for operation test based on the test clock signal testck input to the test clock input terminal 35 and the test control signal TESTEN input to the test control signal input terminal 36. . Further, the configuration of the test control circuit 31 is exemplified by the configuration shown in Fig. 2 of the patent document i, and the detailed description thereof will be omitted. However, the test control circuit 31 may be additionally provided with test input terminals for accepting the various control k numbers. In this case, the test control circuit 3 directly uses the test input signal input from the test input terminal as a signal for the operation test of the liquid BB driver 20. Thereby, it is possible to switch between using the test-based clock signal TESTCK and the test control signal TESTEN to generate various signals for the operation test by itself, and performing an operation test based on the test input signal from the outside. situation. The test control circuit 31 selects one of the gradation voltages generated by the voltage generating circuit 28 based on the test control signal TESTEN and the test clock signal TESTCK, 'via the DA converter 26 and the output amplifier 27 (27a to 27m). An input signal for outputting to each of the liquid crystal output terminals 29 (29a to 29m) is generated and output to the liquid crystal driver 2A. The test control circuit 31 can sequentially set any gradation voltage of 1 degree to n degree according to the input quantity of the test clock signal TESTCK (time 163224.doc 201250268 pulse number). In the present embodiment, the test control circuit 31 generates an input signal for outputting the full scale by sequentially increasing or decreasing the gradation voltage based on the test control signal TESTEN and the test clock signal TESTCK. The gradation deviation determination circuit 33 is composed of, for example, a comparator, and inputs the output voltages of the amplifiers 27a to 27m via one of the input switches of the output changeover switch 34, and the semiconductor test device (tester) 32 at the other end. The ideal voltage of the gradation voltage is input as a reference voltage via the reference voltage input terminal 37. The gradation deviation determining circuit 33 compares the gradation voltage input from the amplifier to the one end and the ideal voltage of the gradation voltage input to the other end, and outputs the comparison result to the gradation deviation determining output terminal 38. The output changeover switch 34 is provided with a switch on each of the output amplifiers, and according to the test control signal TESTEN, the input destinations of the output voltages of the output amplifiers 27a to 27m are at any one of the corresponding liquid crystal output terminals 29a to 29m and the order. The end of the input terminal of the degree deviation determining circuit 33 is switched. The semiconductor device 30 is connected to the semiconductor test device (tester) 32 via the terminals 35 to 38, and can perform a deviation between the gradation power generated by the voltage generating circuit 28 and an ideal voltage value of each output terminal, or each output terminal. Check the homogeneity of the gradual voltage values. Hereinafter, a method of inspecting the semiconductor device 3 of the present invention will be described with reference to Fig. 2 . Fig. 2 is a timing chart showing an implementation flow of the inspection method of the present invention. Each of the terminals 35 to 38' of the semiconductor device 30 is connected to the semiconductor test package 163224.doc • 12 to 201250268 32, and the test control circuit 31 is operated, the semiconductor test is placed 32, and the test clock input terminal 35 is passed. The test clock signal TESTCK is input, and the test control signal TESTEN is input via the test control signal terminal, and the test control signal (here, the high level) is activated. Receiving this signal, the test control circuit 31 makes the gradation voltage from the output amplifier 27 based on the test clock signal TESTCK and the test control signal TESTEN. The gradation is sequentially increased to nth order to generate an input signal of full scale output. At this time, the output destination of each of the output amplifiers 27 is connected to the input terminal of the gradation deviation determining circuit 33 by the output switching switch 34. Further, the output gradation voltage of the output amplifier 27 connected to one end of the input terminal of the gradation deviation determining circuit 33 is outputted from the output amplifier 27a according to the test clock signal TESTCK by the respective switching switches in the output changeover switch 34. Switch to 27m in order. On the other hand, the other end of the input terminal of the gradation deviation determining circuit 33 has an ideal voltage of the gradation voltage supplied from the semiconductor testing device 32 as a reference voltage, and the gradation deviation determining circuit 3 3 is based on the test. The clock signal TESTCK compares the output gradation dust of the output amplifier 27 with the ideal voltage', and sequentially switches from the output amplifier 27& to 27m. In FIG. 2, when the voltage of the first gradation voltage having the gradation voltage is output to each of the output amplifiers 27 according to the control of the liquid crystal driver 20 through the test control circuit 31, the reference voltage input terminal 37 has the first order of magnitude. The ideal voltage for the voltage is supplied from the semiconductor test device 32. The gradation deviation determination circuit 33 will amplify the gradation voltage of the first gradation of the output of the 163224.doc 13 201250268 to the output of the §27 rounds and the supply of the semiconductor device 5 Comparing the ideal voltages of σ L Aa ^ and σ, the respective gradation voltages of the first gradation outputted by the output amplifiers 27a to 27m are implemented, and the gradation voltage is in a specific voltage range with respect to the ideal voltage. The determination is made, and the determination result is output to the gradation deviation determination output terminal 38. Here, the determination result is that the determination result is in the low voltage level in the voltage range, and the high level is outside the voltage range, and is used as the low level or the same level 2 value information, and the output is judged to the gradation deviation. Terminal 38 is output. By detecting the output voltage of the output terminal 38 by monitoring the gradation deviation, it is possible to recognize whether or not the ith gradation of the output gradation voltage of each of the output amplifiers 27a to 27m is present. Then, the test control circuit 31 controls the liquid crystal driver 2A so that the output amplifiers 27a to 27m output the second-order gradation voltage, and performs relative output by controlling the respective switching switches in the output switching switch 34. Each of the second-order gradation voltages output by the amplifiers 27a to 27m, whether the gradation voltage is within a specific voltage range with respect to the ideal voltage, and outputting the determination result to the gradation deviation determination output terminal 38" The order is repeated to the gradation voltage of the nth order, and the deviation test of the write gradation voltage of the semiconductor device 30 and the uniformity test can be performed. As described above, the semiconductor device 30 of the present invention includes the test control circuit 31, the gradation deviation determination circuit 33, and the output changeover switch 34, and can be used in a semiconductor product of a multi-output, multi-step progression of a liquid crystal driver LSI or the like. In the inspection of the body circuit, an input signal for generating a gradation voltage for testing is generated by the semiconductor device 30 itself as the device under test, and the device to be tested is also determined by the device 163224.doc -14-201250268 The ignorance phase X voltage value is within the allowable range relative to the ideal voltage (reference voltage) value, and only the median value of Jiang Yili is outputted to the semiconductor test device (tester) 32, and the self-decoding is performed. The public is not guilty. Therefore, the semiconductor tester (tester) 32 and the device under test 3 are supplied with only a power source or a small number of control signals. And the result of the determination is judged by the transmission of the gradation deviation. According to this, not only does the high-performance semiconductor test device necessary for the previous test are not required, but also a plurality of simultaneous measurements can be realized without depending on the output amount. Since the above-mentioned effects can be expected, there is no need to invest in a high-priced semiconductor test apparatus in the case of multi-output and multi-step enlargement in the future, and many simultaneous measurements can be realized, which greatly contributes to a reduction in test cost. [Industrial Applicability] The present invention can be used for inspection and inspection of gradation deviation of gradation generated by a semiconductor device such as a liquid crystal driver. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic circuit diagram of a semiconductor device of the present invention. Fig. 2 is a timing chart showing an implementation flow of the inspection method of the semiconductor device of the present invention. Fig. 3 is a block diagram of a liquid crystal driver for performing multi-step display. Fig. 4 is an example of a step resistance circuit used for generating a gradation voltage in a liquid crystal driver. Fig. 5 is a schematic diagram showing a gradation test method (system configuration) using a high-precision voltmeter. Fig. 6 is a view showing the content of the gradation test of the liquid crystal driver" I63224.doc -15-201250268 [Description of main component symbols] 11 device under test (DUT) 12 semiconductor test device (tester) 13 memory 14 arithmetic device 15 High-precision analog voltage tester 20 Liquid crystal drive Is 21 Displacement register 22 Latch circuit 23 Sample memory 24 Hold memory 25 Level converter 26 DA converter 27 Output amplifier 27a ~ 27m Output amplifier 28 Voltage generation circuit 29a ~ 29m liquid crystal output terminal 30 semiconductor device 31 of the present invention test control circuit 32 semiconductor test device (tester) 33 gradation deviation determination circuit 34 output changeover switch 35 test clock input terminal 36 test control signal input terminal 163224.doc - 16- 201250268
37 38 TESTCK TESTEN 參考電壓輸入端子 階度偏差測定輸出端子 測試用時脈信號 測試用控制信號 163224.doc 1737 38 TESTCK TESTEN Reference voltage input terminal Deviation deviation measurement output terminal Test clock signal Test control signal 163224.doc 17