201246488 六、發明說明： 【發明所屬之技術領域】 本發明係有關於晶片封裝體，且特別是有關於微機電 系統晶片封裝體(MEMS chip packages)。 【先前技術】 隨著電子產品朝向輕、薄、短、小發展的趨勢，半導 體晶片的封裝結構也朝向多晶片封裝（multi-chip package， MCP)結構發展，以達到多功能和高性能要求。多晶片封裝 結構係將不同類型的半導體晶片’例如邏輯晶片、類比晶 片、控制晶片或記憶體晶片，整合在單一封裝基底之上。 不同晶片之間可透過銲線而彼此電性連接。然而，隨 著需整合的晶片數量上升，將多晶片以銲線相連接會造成 封裝體體積無法有效縮小，且亦會佔去過多面積而造成製 作成本增加，不利於可攜式電子產品的應用。 【發明内容】 本發明一實施例提供一種晶片封裝體，包括：一第一 基底；一第二基底，設置於該第一基底之上，其中該第二 基底具有貫穿該第二基底之至少一開口，該至少一開口於 該第二基底之中劃分出彼此電性絕緣的複數個導電區；一 承載基底，設置於該第二基底之上；至少一阻擋塊體，對 應地設置於該第二基底之該至少一開口之上，且大抵完全 覆蓋該至少一開口； 一絕緣層，設置於該承載基底之一表 面及一侧壁之上；以及一導電層，設置於該承載基底上之201246488 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to chip packages, and more particularly to MEMS chip packages. [Prior Art] As electronic products are moving toward light, thin, short, and small trends, the package structure of semiconductor wafers is also moving toward a multi-chip package (MCP) structure to meet versatility and high performance requirements. Multi-chip package structures integrate different types of semiconductor wafers, such as logic wafers, analog wafers, control wafers or memory chips, onto a single package substrate. Different wafers can be electrically connected to each other through a bonding wire. However, as the number of wafers to be integrated increases, connecting the multi-wafers with the bonding wires may result in an ineffective reduction of the package volume, and may also occupy too much area, resulting in an increase in manufacturing cost, which is not conducive to the application of portable electronic products. . An embodiment of the present invention provides a chip package including: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate has at least one of the second substrate An opening, the at least one opening defines a plurality of conductive regions electrically insulated from each other; a carrier substrate disposed on the second substrate; at least one blocking block correspondingly disposed on the first substrate An at least one opening of the second substrate and substantially covering the at least one opening; an insulating layer disposed on a surface of the carrier substrate and a sidewall; and a conductive layer disposed on the carrier substrate
Xll-024_9002-A36074TWF」ychen 201246488 該絕緣層之上，且電性接觸其中一該些導電區。 本發明一實施例提供一種晶片封裝體的形成方法，包 括：提供一第一基底；將一第二基底設置於該第一基底之 上’其中該第二基底具有貫穿該第二基底之至少一開口， 該至少一開口於該第二基底之中劃分出彼此電性絕緣的複 數個導電區；將一承載基底設置於該第二基底之上；部分 移除該承載基底以形成露出該第二基底之該些導電區之至 少一凹陷；於該第二基底之該至少一開口上對應地形成至 少一阻擋塊體，其中該至少一阻擋塊體大抵完全覆蓋該該 至少一開口；.於該承載基底上形成一絕緣層，其中該絕緣 層延伸於該至少一凹陷之一側壁之上；以及於該絕緣層之 上形成一導電層，其中該導電層電性接觸其中一該些導電 區。 【實施方式】 $下將詳細說明本發明實施例之製作與使用方式。然 ^主意的是，本發明提供許多可供應㈣發明概念，其可 2種特定型式實施。文中所舉例討論之特定實施例僅為 ^與使用本發明之較方式，以限制本發明之範 技fc人士自本揭露書之申請專财所能推及的 貫把方式皆屬本揭露書所欲揭露之内容。此外，在不 ϋίϋ中可能使用重複的標號或標示。這些重複僅為了 έ士月地敘述本發明’不代表所討論之不同實施例及/或 間具有任何關連性。再者，當述及—第—材料層位 ；一材料層上或之上時，包括第一材料層與第二材料 4 X11-024_9002-A36074TWFJychen 201246488 層直接接觸或間隔有一或更多其他材料層之情形。 本發明一實施例之晶片封裝體可用以封裝各種晶片。 例如’其可用於封裝各種包含主動元件或被動元件（acti ve or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件（electronic components)，例 如是有關於光電元件（opto electronic devices)、微機電系統 (IVLicro Electro Mechanical System; MEMS)、微流體系統 (micro fluidic systems)、或利用熱、光線及壓力等物理量變 化來測量的物理感測器（Physical Sensor)。特別是可選擇使 用晶圓級封裝（wafer scale package; WSP)製程對影像感測 元件、發光二極體(light-emitting diodes; LEDs)、太陽能電 池（solar cells)、射頻元件（RF circuits)、加速計 (accelerators)、陀螺儀（gyroscopes)、微制動器（micro actuators)、表面聲波元件（surface acoustic wave devices)、 壓力感測器（process sensors)喷墨頭（ink printer heads)、或功 率晶片（power IC)等半導體晶片進行封裝。 上述晶圓級封裝製程主要係指在晶圓階段完成封裝步 驟後，再予以切割成獨立的封裝體，然而，在一特定實施 例中’例如將已分離之半導體晶片重新分布在一承載晶圓 上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外， 上述晶圓級封裝製程亦適用於藉堆疊（stack)方式安排具有 積體電路之多片晶圓’以形成多層積體電路（multi_layer integrated circuit devices)之晶片封裳體。 第1A-1G圖顯示根據本發明一實施例之晶片封裝體的 製程剖面圖。在下述說明中，以採用晶圓級封裝製程的實 5 Xll-024_9002-A36074TWF_jych e η 201246488 鈀例為例。然應注意的是，本發明實施例亦可採用別於晶 圓級封裝製程的其他適合製程。 如第1A圖所示，提供基底1〇〇。基底1〇〇可為半導體 基底（例如，石夕基底）或半導體晶圓（例如，石夕晶圓）。採用半 導體BS圓可利於晶圓級封裝製程的進行，可確保封裝品 質，並節省製程成本及時間。在一實施例中，基底丨〇〇中 形成有複數個CMOS元件（未顯示）。基底1〇〇之表面上形 成有複數個接墊102。這些接墊102分別電性連接至相應 的CMOS元件。基底1〇〇之表面上還形成有保護層1〇4， 其可覆蓋基底100之表面，並具有露出接墊1〇2之開口。 保護層104之材質例如是氧化物、氮化物、氮氧化物、高 分子材料、或前述之組合。 如第1A圖所示，提供基底2〇〇。基底200可為半導體 基底（例如，矽基底）或半導體晶圓（例如，矽晶圓）。在一實 施例中，基底100中形成有複數個CMOS元件（未顯示）。 在一實施例中，基底200中形成有複數個MEMS元件。基 底200之上表面上可形成有絕緣層2〇6及承載基底2〇4。 絕緣層206之材質例如為氧化物、氮化物、氮氧化物、高 分子材料、或前述之組合。在一實施例中，絕緣層206之 材質為氧化矽。承載基底204例如可為半導體基底 ，例如 是石夕晶圓。基底200可透過形成於下表面上之接墊202而 接合於基底1〇〇之上。例如，在一實施例中，接墊202與 接塾102可分別包括鍺及鋁，並彼此接合，如第ία圖所 示。在一實施例中，接墊202及接墊102皆為導電材料。 因此’接墊202及接墊1〇2還可形成基底100與基底200 6 XU-024_9002-A36074TWFJychen 201246488 之間的導電通路。例如，基底100中之CMOS元件與基底 200中之MEMS元件可透過接墊202與接塾1〇2而彼此傳 遞電性訊號。在一實施例中，可分別對基底1〇〇及承載基 底204進行薄化製程。 在一實施例中，複數個預定切割道SC將基底100與 基底200之堆疊晶圓劃分成複數個區域。在後續封裝與切 割製程之後，每一區域將成為一晶片封裝體。在基底2〇〇 之每一區域之中，可形成有複數條貫穿基底2〇〇之縫隙（或 開口），其於基底200中劃分出複數個彼此不電性連接之導 電區。每一導電區可電性連接至相應的接墊202。在一實 施例中’這些導電區為基底200中之高摻雜區域。例如， 這些導電區中可摻雜有高濃度的p型摻質。在一實施例 中’數個接墊202可沿著預定切割道Sc之邊緣排列。 接著，如第1B圖所示，可部分移除承載基底2〇4以於 承載基底204中形成至少一凹陷208。凹陷208可大抵沿 著其中一預定切割道SC延伸。凹陷208可露出絕緣層 206。在一實施例中，可透過微影及蝕刻製程（例如，乾式 蝕刻）形成凹陷208。 第2圖顯示相應於第1B圖之結構的立體示意圖。如第 2圖所示，基底2〇〇可具有至少一開口，其於基底2〇〇中 劃分出複數個彼此不電性連接的導電區。在一實施例中.， 複數個開口 201a及201b將基底200劃分成複數個導電區 203a、203b、及203c。這些導電區因開口之隔離而彼此電 性絕緣。 在一實施例中’可透過微影及蝕刻製程於承載基底204 7 Xll-024_9002-A36074TWFJychen 201246488 中形成複數個朝基底200延伸之凹陷，例如包括凹陷208、 208a、及208b。透過蝕刻製程之參數及/或蝕刻劑之配方的 調整’可依需求使所形成之凹陷具有特定傾斜程度之側 壁。例如’在第2圖之實施例中，所形成之凹陷208、208a、 及208b可具有傾斜於承載基底204之上表面的側壁。然應 注意的是’本發明實施例不限於此。在其他實施例中，承 載基底204中所形成之凹陷可具有大抵垂直於承載基底 204之上表面的側壁。 在形成凹陷208、208a、及208b之後，可於承載基底 204中定義出複數個阻擋塊體，例如包括阻擋塊體204a及 204b。在此情形下’阻擋塊體之材質大抵相同於承載基底。 阻擔塊體可分別覆蓋下方之基底200中所對應之開口。例 如’阻擋塊體204a可大抵完全覆蓋基底200中之開口 201a，而阻擋塊體204b可大抵完全覆蓋基底200中之開口 201b。在一實施例中’阻擋塊體之寬度等於基底200中之 對應開口的寬度。在另一實施例中，阻擋塊體之寬度大於 基底200中之對應開口的寬度。 雖然，在上述實施例中，係透過對承載基底204之圖 案化製程而於基底200中之開口（例如，2〇la及201b)上分 別形成對應的阻擔塊體（例如’阻擔塊體204a及204b)，但 本發明實施例不限於此。在其他實施例中，可先圖案化承 载基底204以形成露出絕緣層206之溝槽。接著，於溝槽 底部之絕緣層206上，對應基底200中之開口（例如，2〇la 及201b)的位置形成可完全蓋住開口阻擋塊體。在此情形 下’所形成之阻擋塊體可由其他材料形成。因此，阻擔塊 8 Xll-024_9〇〇2-A36074TWFJychen 201246488 體之材質可不同於承載基底204。 在一實施例中’基底200之下表面上可形成有複數個 接墊202 ’這些接墊202可延著凹陷208(或沿著預定切割 道SC)而設置。每一導電區可電性連接至其中一相應的接 墊而與基底100中之相應的CMOS元件電性連接。例如， 在一實施例中’導電區203可透過第2圖所示之接墊202 及接墊102而與基底1〇〇中之相應的CMOS元件電性連接。 如第1C圖所示’接著於承載基底204之上形成絕緣層 210。絕緣層210之材質可為氧化物、氮化物、氮氧化物、 尚分子材料、或前述之組合。絕緣層210之形成方式例如 是氣相沉積、噴塗、塗佈、或印刷等。絕緣層21〇可填入 凹陷208之中。 接著’如第1C圖所示’例如以钱刻製程移除凹陷底部 之部分的絕緣層206及210以露出基底200之導電區。請 參照第2圖及第1C圖’在部分移除絕緣層206及210之後， 複數個彼此電性絕緣之導電區於凹陷底部露出。例如，凹 陷208可露出基底200之導電區203a，凹陷208a可露出基 底200之導電區203b，而凹陷208b可露出基底200之導 電區203c。由於阻擋塊體之阻播，阻擔塊體下方之絕緣層 206將保留而不被移除。因此，基底2〇〇中之開口（例如， 開口 201a及201b)將完全由上方之絕緣層206與阻擋塊體 (例如，阻擋塊體204a及204b)所覆蓋。 請繼續參照第1C圖，可接著於承載基底204之上形成 圖案化導電層。導電層之材質可包括鋁、銅、金、鎳、或 前述之組合。導電層之形成方式可包括物理氣相沉積、化 9 Xll-024_9002-A36074TWFJychen 201246488 學氣相沉積、塗佈、電鍍、無電鍍、或前述之組合。以下， 以採用電鍍製程為例說明一實施例之圖案化導電層的形成 過程。 如第1C圖所示’於承載基底204之上形成晶種層 214。晶種層214之材質例如為鋁、銅、或前述之組合，其 形成方式例如為濺鐘。晶種層214可大抵順應性且全面地 覆蓋於絕緣層210之上，並與所露出之導電區（例如，導電 區203a、203b、及203c)電性接觸。 接著，如第1D圖所示，例如透過微影及触刻製程而 將晶種層214圖案化以形成圖案化晶種層214a。圖案化晶 種層214a可僅電性接觸其中一導電區，例如是導電區 203a。晶種層214經圖案化之後，還可形成出電性連接其 他導電區（例如，導電區203b或203c)之圖案化晶種層。由 於先前所形成之阻擋塊體(204a及204b)已封住基底2〇〇於 凹陷底部處之開口（例如，開口 201va及201b)，因此晶種層 214之圖案化過程中所需採用之钱刻液及/或餘刻氣體將不 會經由基底200之開口而到達接墊202與接塾1 〇2，可確 保基底100與基底200之間的接合與電性連接。 如第1E圖所示’接著可透過電鍍製程而於晶種層214a 之表面上電鑛導電材料以形成導電層214b。在一實施例 中’導電層214b可包括鎳、金、銅、或前述之組合。在一 實施例中，在同一道電鍍製程中，亦可於其他晶種層上形 成其他導電層。例如，可形成出電性連接導電區2〇3b或 203c之導電層（未顯示）。 接者’如第1F圖所示’於導電層214b上形成防銲層 10 Xll-024_9002-A36074TWFJychen 201246488 216。防銲層216具有露出導電層214b之開口。接著，可 於開口所露出之導電層214b之上形成導電凸塊218。 如第1G圖所示，可沿著預定切割道SC切割顯示於第 1F圖之結構而形成複數個彼此分離的晶片封裝體。在一實 施例中，晶片封裝體包括：一第一基底1〇〇 ; —第二基底 200 ’設置於該第一基底之上，其中該第二基底具有貫穿該 第二基底之至少一開口（例如，開口 201a及201b)，該至少 一開口於該第二基底之中劃分出彼此電性絕緣的複數個導 電區（例如，導電區203a、203b、及203c); —承載基底204， 設置於該第二基底之上；至少一阻擋塊體（例如，阻擋塊體 204a及204b)，對應地設置於該第二基底之該至少一開口 之上’且大抵完全覆蓋該至少一開口（例如，阻擋塊體204a 大抵完全覆蓋開口 201a，而阻擋塊體204b大抵完全覆蓋 開口 201b); —絕緣層210，設置於該承載基底之一表面及 一側壁之上；以及一導電層（214a及214b)，設置於該承載 基底上之該絕緣層之上，且電性接觸其中一該些導電區（例 如，導電區203a)。 第3圖顯示本發明一實施例之晶片封裝體，其中相同 或相似之標號用以標示相同或相似之元件。在第3圖之實 施例中’承載基底204中之露出基底200之導電區（例如， 導電區203a)的凹陷（例如，凹陷208)之側壁係大抵垂直於 承載基底204之上表面。在一實施例中，由於凹陷具有大 抵垂直之侧壁，可使凹陷底部導電層214b與導電區203a 之接觸面積較大，可降低接觸電阻。此外，在一實施例中， 基底100上之保護層104還可直接接觸基底200，如第3 11 Xll-024_9002-A36074TWFJychen 201246488 圖所示。 本發明實施例還可有許多變化。例如，在形成圖案化 晶種層214a時，可使承載基底204之凹陷底部上之圖案化 晶種層214a不觸及預定切割道SC而使後續電鍍之導電層 214b亦不觸及預定切割道SC。換言之，可透過圖案化製 程之調整使所形成之圖案化導電層與預定切割道SC之間 隔有間距而不直接接觸。在此情形下，所形成之防銲層216 將於凹陷之底部處包覆導電層之側邊。換言之，防銲層216 包覆導電層之鄰近所接觸導電區之部分的一側邊。如此， 在後續切割製程中，切割刀片將不會切割到圖案化導電 層，可避免導電層因切割製程而受損或脫落。此外，由於 防銲層216包覆導電層之側邊，可避免導電層氧化或受損。 雖然本發明已以數個較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。Xll-024_9002-A36074TWF"ychen 201246488 Above the insulating layer, and electrically contacting one of the conductive regions. An embodiment of the present invention provides a method of forming a chip package, including: providing a first substrate; and disposing a second substrate on the first substrate; wherein the second substrate has at least one of the second substrate An opening, the at least one opening defines a plurality of conductive regions electrically insulated from each other; a carrier substrate is disposed on the second substrate; and the carrier substrate is partially removed to form the second substrate At least one of the plurality of conductive regions of the substrate; at least one blocking block is formed on the at least one opening of the second substrate, wherein the at least one blocking block substantially completely covers the at least one opening; Forming an insulating layer on the carrier substrate, wherein the insulating layer extends over a sidewall of the at least one recess; and forming a conductive layer over the insulating layer, wherein the conductive layer electrically contacts one of the conductive regions. [Embodiment] The manner of making and using the embodiment of the present invention will be described in detail below. However, it is an idea that the present invention provides a number of (4) inventive concepts that can be implemented in two specific versions. The specific embodiments discussed herein are merely examples of the use of the present invention in order to limit the scope of the present invention. The content to be disclosed. In addition, duplicate labels or labels may be used in the absence of 。. These repetitions are merely a mere description of the present invention by the gentleman's, and do not represent any connection to the various embodiments and/or discussed. Furthermore, when referring to a - material layer; on or above a material layer, the first material layer and the second material 4 X11-024_9002-A36074TWFJychen 201246488 layer are in direct contact or spaced apart from one or more other material layers. The situation. The chip package of one embodiment of the present invention can be used to package various wafers. For example, it can be used to package various electronic components including integrated circuits such as active components or passive elements, digital circuits or digital circuits, such as optical components. (opto electronic devices), IVLicro Electro Mechanical Systems (MEMS), micro fluidic systems, or physical sensors that measure physical quantities such as heat, light, and pressure. In particular, a wafer scale package (WSP) process can be selected for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors ink printer heads, or power chips ( A semiconductor wafer such as power IC) is packaged. The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed on a carrier wafer. The encapsulation process is also referred to as a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to a wafer package body in which a plurality of wafers having integrated circuits are arranged in a stack manner to form multi-layer integrated circuit devices. 1A-1G are cross-sectional views showing a process of a chip package in accordance with an embodiment of the present invention. In the following description, a palladium example using a wafer level packaging process is exemplified. It should be noted that embodiments of the present invention may also employ other suitable processes other than the wafer level packaging process. As shown in Fig. 1A, a substrate 1 is provided. The substrate 1 can be a semiconductor substrate (e.g., a stone substrate) or a semiconductor wafer (e.g., a stone wafer). The use of a semiconductor BS circle facilitates wafer-level packaging processes, ensuring package quality and saving process cost and time. In one embodiment, a plurality of CMOS elements (not shown) are formed in the substrate. A plurality of pads 102 are formed on the surface of the substrate. These pads 102 are electrically connected to respective CMOS components. A protective layer 1〇4 is also formed on the surface of the substrate 1 to cover the surface of the substrate 100 and has an opening exposing the pads 1〇2. The material of the protective layer 104 is, for example, an oxide, a nitride, an oxynitride, a high molecular material, or a combination thereof. As shown in Fig. 1A, a substrate 2 is provided. Substrate 200 can be a semiconductor substrate (e.g., a germanium substrate) or a semiconductor wafer (e.g., a germanium wafer). In one embodiment, a plurality of CMOS elements (not shown) are formed in substrate 100. In an embodiment, a plurality of MEMS elements are formed in the substrate 200. An insulating layer 2〇6 and a carrier substrate 2〇4 may be formed on the upper surface of the substrate 200. The material of the insulating layer 206 is, for example, an oxide, a nitride, an oxynitride, a high molecular material, or a combination thereof. In one embodiment, the insulating layer 206 is made of yttria. The carrier substrate 204 can be, for example, a semiconductor substrate such as a stone wafer. The substrate 200 is bonded to the substrate 1 through a pad 202 formed on the lower surface. For example, in one embodiment, the pads 202 and the pads 102 may include tantalum and aluminum, respectively, and are joined to each other, as shown in the Figure. In an embodiment, the pads 202 and the pads 102 are all electrically conductive materials. Thus, the pads 202 and pads 1〇2 can also form a conductive path between the substrate 100 and the substrate 200 6 XU-024_9002-A36074TWFJychen 201246488. For example, the CMOS components in the substrate 100 and the MEMS components in the substrate 200 can transmit electrical signals to each other through the pads 202 and the contacts 1〇2. In one embodiment, the substrate 1 and the carrier substrate 204 can be thinned separately. In one embodiment, a plurality of predetermined scribe lines SC divide the stacked wafers of substrate 100 and substrate 200 into a plurality of regions. After subsequent packaging and cutting processes, each region will become a chip package. In each of the regions 2 〇〇, a plurality of slits (or openings) penetrating through the substrate 2 may be formed, and a plurality of conductive regions which are not electrically connected to each other are divided in the substrate 200. Each conductive region can be electrically connected to a corresponding pad 202. In one embodiment, these conductive regions are highly doped regions in the substrate 200. For example, these conductive regions may be doped with a high concentration of p-type dopants. In one embodiment, a plurality of pads 202 may be aligned along the edge of the predetermined scribe track Sc. Next, as shown in FIG. 1B, the carrier substrate 2〇4 may be partially removed to form at least one recess 208 in the carrier substrate 204. The recess 208 can extend substantially along one of the predetermined scribe lines SC. The recess 208 can expose the insulating layer 206. In one embodiment, the recess 208 can be formed by a lithography and etching process (e.g., dry etching). Fig. 2 is a perspective view showing the structure corresponding to Fig. 1B. As shown in Fig. 2, the substrate 2 can have at least one opening which divides a plurality of conductive regions which are not electrically connected to each other in the substrate 2A. In one embodiment, the plurality of openings 201a and 201b divide the substrate 200 into a plurality of conductive regions 203a, 203b, and 203c. These conductive regions are electrically insulated from one another by the isolation of the openings. In one embodiment, a plurality of recesses extending toward the substrate 200, including recesses 208, 208a, and 208b, are formed in the carrier substrate 204 7 Xll-024_9002-A36074TWFJychen 201246488 by a lithography and etching process. The depressions formed by the etching process and/or the formulation of the etchant can be made to have sidewalls of a particular degree of inclination as desired. For example, in the embodiment of Fig. 2, the recesses 208, 208a, and 208b formed may have sidewalls that are inclined to the upper surface of the carrier substrate 204. It should be noted that the embodiment of the present invention is not limited thereto. In other embodiments, the depressions formed in the carrier substrate 204 can have sidewalls that are substantially perpendicular to the upper surface of the carrier substrate 204. After forming the recesses 208, 208a, and 208b, a plurality of blocking blocks can be defined in the carrier substrate 204, including, for example, blocking blocks 204a and 204b. In this case, the material of the blocking block is substantially the same as the carrier substrate. The resistive blocks may respectively cover the corresponding openings in the underlying substrate 200. For example, the <blocking block 204a can substantially completely cover the opening 201a in the substrate 200, and the blocking block 204b can substantially completely cover the opening 201b in the substrate 200. In one embodiment, the width of the blocking block is equal to the width of the corresponding opening in the substrate 200. In another embodiment, the width of the blocking block is greater than the width of the corresponding opening in the substrate 200. In the above embodiments, corresponding resistive blocks (eg, 'resistance blocks') are respectively formed on the openings (eg, 2〇1a and 201b) in the substrate 200 through the patterning process of the carrier substrate 204. 204a and 204b), but the embodiment of the invention is not limited thereto. In other embodiments, the carrier substrate 204 can be patterned first to form trenches that expose the insulating layer 206. Next, on the insulating layer 206 at the bottom of the trench, the positions of the openings (e.g., 2?la and 201b) corresponding to the substrate 200 are formed to completely cover the opening blocking block. The barrier block formed in this case can be formed of other materials. Therefore, the material of the resisting block 8 X11-024_9〇〇2-A36074TWFJychen 201246488 may be different from the carrier substrate 204. In one embodiment, a plurality of pads 202 may be formed on the lower surface of the substrate 200. These pads 202 may be disposed along the recess 208 (or along a predetermined scribe line SC). Each of the conductive regions is electrically connected to one of the corresponding pads to be electrically connected to a corresponding CMOS device in the substrate 100. For example, in one embodiment, the conductive region 203 can be electrically connected to the corresponding CMOS device in the substrate 1 through the pads 202 and pads 102 shown in FIG. An insulating layer 210 is formed over the carrier substrate 204 as shown in FIG. 1C. The material of the insulating layer 210 may be an oxide, a nitride, an oxynitride, a molecular material, or a combination thereof. The insulating layer 210 is formed by, for example, vapor deposition, spraying, coating, or printing. The insulating layer 21 can be filled in the recess 208. Next, as shown in Fig. 1C, the insulating layers 206 and 210 of the portion of the bottom of the recess are removed, for example, by a vacuum engraving process to expose the conductive regions of the substrate 200. Referring to FIG. 2 and FIG. 1C', after the insulating layers 206 and 210 are partially removed, a plurality of electrically insulating conductive regions are exposed at the bottom of the recess. For example, the recess 208 may expose the conductive region 203a of the substrate 200, the recess 208a may expose the conductive region 203b of the substrate 200, and the recess 208b may expose the conductive region 203c of the substrate 200. Due to the blocking of the blocking block, the insulating layer 206 under the resisting block will remain without being removed. Thus, the openings in the substrate 2 (e.g., openings 201a and 201b) will be completely covered by the upper insulating layer 206 and the blocking blocks (e.g., blocking blocks 204a and 204b). Continuing to refer to FIG. 1C, a patterned conductive layer can then be formed over carrier substrate 204. The material of the conductive layer may include aluminum, copper, gold, nickel, or a combination of the foregoing. The conductive layer may be formed by physical vapor deposition, vapor deposition, coating, electroplating, electroless plating, or a combination thereof. Hereinafter, the formation process of the patterned conductive layer of an embodiment will be described by taking an electroplating process as an example. A seed layer 214 is formed over the carrier substrate 204 as shown in FIG. 1C. The material of the seed layer 214 is, for example, aluminum, copper, or a combination thereof, and is formed by, for example, a splash clock. The seed layer 214 can be substantially conformed and fully overlaid over the insulating layer 210 and in electrical contact with the exposed conductive regions (e.g., conductive regions 203a, 203b, and 203c). Next, as shown in FIG. 1D, the seed layer 214 is patterned, for example, by lithography and a etch process to form a patterned seed layer 214a. The patterned seed layer 214a can be electrically contacted only to one of the conductive regions, such as the conductive region 203a. After the seed layer 214 is patterned, a patterned seed layer electrically connected to other conductive regions (e.g., conductive regions 203b or 203c) may also be formed. Since the previously formed barrier blocks (204a and 204b) have sealed the openings of the substrate 2 at the bottom of the recess (for example, the openings 201va and 201b), the money required for the patterning of the seed layer 214 is required. The engraving and/or residual gas will not reach the pad 202 and the interface 1 〇 2 via the opening of the substrate 200, and the bonding and electrical connection between the substrate 100 and the substrate 200 can be ensured. As shown in Fig. 1E, the conductive material is then electroformed on the surface of the seed layer 214a through an electroplating process to form a conductive layer 214b. In one embodiment, the conductive layer 214b may comprise nickel, gold, copper, or a combination of the foregoing. In one embodiment, other conductive layers may be formed on other seed layers during the same plating process. For example, a conductive layer (not shown) electrically connecting the conductive regions 2〇3b or 203c may be formed. The connector 'shows as shown in Fig. 1F' on the conductive layer 214b to form a solder resist layer 10 Xll-024_9002-A36074TWFJychen 201246488 216. The solder resist layer 216 has an opening that exposes the conductive layer 214b. Next, conductive bumps 218 can be formed over the conductive layer 214b exposed by the openings. As shown in Fig. 1G, a plurality of chip packages separated from each other can be formed by cutting the structure shown in Fig. 1F along a predetermined scribe line SC. In one embodiment, the chip package includes: a first substrate 1; a second substrate 200 ′ disposed on the first substrate, wherein the second substrate has at least one opening extending through the second substrate ( For example, the openings 201a and 201b), the at least one opening defines a plurality of conductive regions (eg, conductive regions 203a, 203b, and 203c) electrically insulated from each other in the second substrate; the carrier substrate 204 is disposed on Above the second substrate; at least one blocking block (for example, the blocking blocks 204a and 204b) is correspondingly disposed on the at least one opening of the second substrate and substantially covers the at least one opening (for example, The blocking block 204a substantially completely covers the opening 201a, and the blocking block 204b substantially covers the opening 201b); the insulating layer 210 is disposed on one surface and a side wall of the carrying substrate; and a conductive layer (214a and 214b) And disposed on the insulating layer on the carrier substrate and electrically contacting one of the conductive regions (eg, the conductive region 203a). Figure 3 is a diagram showing a chip package in accordance with an embodiment of the present invention, wherein the same or similar reference numerals are used to designate the same or similar elements. In the embodiment of Fig. 3, the sidewalls of the recess (e.g., recess 208) of the conductive region (e.g., conductive region 203a) of the exposed substrate 200 in the carrier substrate 204 are substantially perpendicular to the upper surface of the carrier substrate 204. In one embodiment, since the recess has a sidewall that is substantially perpendicular to the sidewall, the contact area between the recessed bottom conductive layer 214b and the conductive region 203a can be made larger, and the contact resistance can be lowered. In addition, in an embodiment, the protective layer 104 on the substrate 100 may also directly contact the substrate 200, as shown in the figure 3 11 X11-024_9002-A36074TWFJychen 201246488. There are many variations to the embodiments of the invention. For example, when the patterned seed layer 214a is formed, the patterned seed layer 214a on the recessed bottom of the carrier substrate 204 can be made to not touch the predetermined scribe line SC and the subsequent electroplated conductive layer 214b does not touch the predetermined scribe line SC. In other words, the patterned conductive layer formed can be spaced apart from the predetermined scribe line SC by direct adjustment through the patterning process without direct contact. In this case, the formed solder resist layer 216 will coat the sides of the conductive layer at the bottom of the recess. In other words, the solder resist layer 216 covers one side of the conductive layer adjacent to a portion of the conductive region that is in contact. Thus, in the subsequent cutting process, the cutting blade will not cut into the patterned conductive layer, and the conductive layer may be prevented from being damaged or peeled off due to the cutting process. In addition, since the solder resist layer 216 covers the sides of the conductive layer, oxidation or damage of the conductive layer can be avoided. While the invention has been described above in terms of several preferred embodiments, it is not intended to limit the scope of the present invention, and it is possible to make any changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.
Xll-024_9002-A36074TWFJychen 201246488 【圖式簡單說明】 第1A-1G圖顯示根據本發明一實施例之晶片封裝體的 製程剖面圖。 第2圖顯示相應於第1B圖之結構的立體示意圖。 第3圖顯示根據本發明一實施例之晶片封裝體的剖面 【主要元件符號說明】 100〜基底； 102〜接墊； 104〜保護層； 200〜基底； 201a、201b〜開口； 202〜接墊； 203a、203b、203c〜導電區； 204〜承載基底； 204a、204b〜阻擋塊體； 206〜絕緣層； 208、208a、208b〜凹陷； 210〜絕緣層； 214、214a〜晶種層； 214b〜導電層； 216〜防鲜層； 218〜導電凸塊； SC〜切割道。 13 Xll-024_9002-A36074TWFJychenXll-024_9002-A36074TWFJychen 201246488 [Simplified Schematic] FIG. 1A-1G is a cross-sectional view showing a process of a chip package according to an embodiment of the present invention. Fig. 2 is a perspective view showing the structure corresponding to Fig. 1B. 3 is a cross-sectional view of a chip package according to an embodiment of the present invention. [Main component symbol description] 100 to substrate; 102 to pad; 104 to protective layer; 200 to substrate; 201a, 201b to opening; 202 to pad ; 203a, 203b, 203c~ conductive region; 204~ bearing substrate; 204a, 204b~ blocking block; 206~ insulating layer; 208, 208a, 208b~ recess; 210~ insulating layer; 214, 214a~ seed layer; ~ Conductive layer; 216 ~ anti-fresh layer; 218 ~ conductive bump; SC ~ cutting track. 13 Xll-024_9002-A36074TWFJychen