TW201246218A - Method of programming memory - Google Patents

Abstract

A method of programming a memory, wherein the memory has a first cell, which has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. When programming process is performed to the first cell, a first voltage is applied to the control gate of the first cell, a second voltage is applied to the control gate of the second cell to slightly turn on the channel of the second cell, a third voltage and a fourth voltage are respectively applied to the first S/D region and third S/D region, and the second S/D region is floating. The carriers flow from the third S/D region to the first S/D region and is injected into the charge storage layer of the first cell by source side injection.

Description

201246218 VI. Description of the Invention: [0001] The present invention relates to the operation of a memory element, and more particularly to a method for staging a memory cell in a memory (array), and a method using the same Memory device. [0002] [Prior Art] Non-volatile memory (_, 1 & 1:] ^ mem....Because it has the ability to store, read, erase, etc. multiple times, and the data stored in it The advantage of not disappearing after power off, so many electrical products must have such a record, it body, in order to maintain the normal operation of the electric product, and become a memory component widely used in personal computers and electronic devices. A typical non-volatile memory component is generally designed to have a stacked-gate structure, including a floating gate (F1 〇ating Gate) fabricated with doped polysilicon. Control gate: The floating gate is located between the control gate and the substrate, and is in a floating state, not connected to any circuit, and the control gate is connected to the Word Line. In addition, a tunneling Oxide and an Inter_Gate Dielectric Layer are respectively disposed between the substrate and the floating gate and between the floating gate and the control gate. Another typical volatility Memory, it is electricity Charge trapping as a data storage type of Nitride read only memory. Using a charge trapping structure composed of an oxide layer-nitride layer-oxide layer (ie, the well-known 100116292 form) No. A0101 Page 4 of 36 page 1002027339-0 201246218 Layer 2 can store two-bit data. Generally, the two-bit data can be stored on the left side of the nitride layer in the charge trapping structure (ie left) Bits) or right side (ie, right bit) [0005] Ο [0006] [0007] 〇 [0008] In the current trend of increasing the degree of component integration, the size of components will be reduced according to design rules. The size of the memory cell is getting smaller and smaller. The punch-through current between the cells is more and more obvious. The breakdown current provided by the unselected memory cells will affect the selection. The stability of the memory cell during the stylization operation can significantly reduce the performance of the memory cell. SUMMARY OF THE INVENTION One embodiment of the present invention provides a method for staging a memory 'the first memory cell in the memory The adjacent second memory cells share an S/D region, the S/D region is floating during programming, and the second memory cell is used as a switching transistor, by making the channel region of the second memory cell slightly open. The first memory cell is programmed by the source side injection effect. One embodiment of the present invention further provides a program method for memory cells in a memory array, which combines a source side injection effect and a channel hot carrier injection effect. To program the above memory cells in a memory array. An embodiment of the present invention further provides a memory device, including a memory array and a circuit unit, wherein a stylized method of an embodiment of the present invention is applicable to the memory array, and the circuit unit can perform one of the present invention The steps of the stylized method of the embodiment. One embodiment of the present invention provides a stylized method of memory. The memory has a first memory cell' the first memory cell has a first S/D region and is associated with 100116292 Form No. A0101 Page 5 / Total 36 Page 1002027339-0 [0009] 201246218 Zone D, and the second memory cell has a third S/D zone opposite the second s/D zone. When staging the first memory cell, applying a first voltage to the first control gate of the first memory cell; applying a second voltage to the second control gate of the first 5 memory cells to make the channel of the second memory cell The region is in a micro-on state; and a third voltage is applied to the first S/D region, and the second S/D region is floating, applying a fourth voltage to the third s/〇 region, and the third voltage and the fourth voltage The carrier is caused to flow from the third S/D region to the first s/D region to inject the carrier into the charge storage layer of the first memory cell by the source side injection effect [0010] [0012] [0013] According to an embodiment of the invention, the second voltage is a starting voltage close to the second memory cell. According to an embodiment of the invention, the first memory cell and the second memory cell are all N-type memory cells, and the third voltage is higher than the fourth voltage in the positive direction. According to an embodiment of the invention, the charge storage layer is a charge trapping layer, and the carrier is trapped in a position in the charge trapping layer of the first memory cell near the second S/D region. One embodiment of the present invention provides a stylized method of memory. The memory has a first memory cell, the first memory cell has a first S/D region and shares a second S/D region with the first s memory cell, and the second memory cell has a second s/D region The third S/D area. When staging the first memory cell, applying a first voltage to the first control gate of the first memory cell; applying a second voltage to the second control gate of the second memory cell, causing the channel region of the second memory cell to be Switching between the micro-on state and the fully-on state; applying a third voltage to 100116292 Form No. A0101 Page 6/36 pages 1002027339-0 201246218 [0015] [0016]

[0019] [0019] a first S/D region, and the second S/D region is floating, applying a fourth voltage to the third S/D region, and the third voltage and the fourth voltage cause The substream flows from the third S/D region to the first S/D region to inject the carrier into the charge storage layer of the first memory cell using the source side injection effect and the channel hot carrier effect. According to an embodiment of the invention, the method for applying the second voltage to the second control gate of the second memory cell includes applying a plurality of voltage pulses (Voltage Pulses) having different intensities to the second control gate, applying a triangle Voltage pulse (Voltage Pulse) to the second control gate or apply a trapezoidal voltage pulse (Volt age Pulse) to the second control gate. According to an embodiment of the present invention, the value of the voltage pulse wave gradually increases from small to large or gradually decreases from large to small. In accordance with an embodiment of the present invention, the method of applying a second voltage to a second control gate of a second memory cell includes applying a triangular voltage pulse to a second control gate. According to an embodiment of the present invention, the value of the triangular voltage pulse wave gradually increases from small to large or gradually decreases from large to small. In accordance with an embodiment of the present invention, the method of applying a second voltage to a second control gate of a second memory cell includes applying a trapezoidal voltage pulse to a second control gate. According to an embodiment of the invention, the value of the trapezoidal voltage pulse wave is gradually increased from small to large and gradually decreased after a period of time or the value of the trapezoidal voltage pulse wave is gradually reduced from a large to a small value and maintained for a period of time. After gradually increasing. According to an embodiment of the present invention, the first memory cell and the second cell 100116292 form number A0101 page 7/36 page 1002027339-0 201246218 are all N-type memory cells, and the third voltage is in the positive direction voltage. . . According to an embodiment of the invention, the charge storage layer is one of a charge trapping layer or a nanocrystalline layer. Insulting the Gate [0021] According to an embodiment of the present invention, the above-mentioned charge library layer is. In the trap layer, the carrier is trapped in the charge trapping layer of the first memory cell to capture the position of the first S/D region and the second S/D region. Sinning [0022] One embodiment of the invention proposes a method of staging stylization in a memory array. During the stylization operation, applying a first voltage to the first control gate of the first memory cell via the sub-line of the first cell; applying a second voltage to the first memory cell via the first sub-line a second control gate of the adjacent first cell, such that the channel region of the second memory cell is in a micro gate: state or fully on state, wherein the first memory cell has a _S/D region and is associated with the second memory cell Sharing a second S/D zone, and the second memory cell has a third s/D zone opposite to the first-S/D zone; applying a third voltage to the first S/D zone via the first bit line; And the second S/D region is floating; and applying a fourth voltage to the third S/D region via the second bit line, wherein the third voltage and the fourth voltage cause the carrier to pass from the third S/D region Flowing into the first S/D region to inject the carrier into the charge storage layer of the first memory cell using the source side injection effect or the channel hot carrier effect. [0023] According to an embodiment of the invention, the charge storage layer is a charge trapping layer, such that the carrier is trapped in the charge trapping layer of the first memory cell near the first S/D region, first The position of the charge trapping layer of the memory cell near the first S/D region, or the charge trapping layer of the first memory cell is close to the _s/100116292 Form No. A0101 Page 8/36 Page 1002027339-〇201246218 D The location of the zone and the location close to the second S/D zone. [0024] According to an embodiment of the invention, the method for programming a memory cell in the memory array further includes applying a fifth voltage to a third bit line adjacent to the first bit line to suppress the first memory cell. The unselected memory cells sharing the first word line and the first bit line are programmed. [0025] According to an embodiment of the invention, the method for programming a memory cell in the memory array further includes applying a sixth voltage to a fourth bit line adjacent to the second bit line to suppress the first memory cell. The unselected memory cells sharing the first word line and the second bit line are programmed. According to the stylized method of one embodiment of the present invention, the memory cell is programmed by the source side injection effect, so that the applied bias voltage is low and the program speed can be increased. [0027] According to a stylized method according to an embodiment of the present invention, a memory cell is programmed by combining a source side injection effect and a channel hot electron injection effect, when used for a memory cell composed of two memory cells. In the group, a single memory cell four-dimensional data storage can be achieved. [0028] According to the stylized method of an embodiment of the present invention, the stylized speed of the memory cell can be increased, the component accumulation degree, and a larger memory margin can be increased. The above and other objects, and features and advantages of the present invention are described in detail with reference to the accompanying drawings. [Embodiment] [0030] An embodiment of the present invention provides a stylized method for a memory cell in a non-volatile memory, which is applicable to a 100116292 formed by two memory cells connected in series. Form No. A0101 Page 9 of 36 201246218 Memory cell group. In the memory cell group, one memory cell is used as a memory cell to be programmed, and the other memory cell is used as a switching transistor. By injecting the state of the channel region (micro-on state or 70-on state) of the memory cell as the switching transistor, the carrier is injected into the memory cell to be programmed by the source side injection effect or the channel hot carrier effect. Charge storage layer. [0033] FIG. 1 depicts a stylized method of memory cells in a non-volatile memory, not according to an embodiment of the present invention. In the following description, an N-type memory cell is taken as an example for explanation. Referring to Fig. 1, in the non-volatile memory, the memory cell group is formed by connecting the memory cell 102 and the memory cell 104 in series. The memory cell 1 〇 2 has a charge storage layer 106a and an n-type source/drain region (hereinafter referred to as §/1) region 108 in the substrate 1〇〇, and is shared with the adjacent memory cell 1〇4. 8/1) Region 11 () ^ The memory cell 104 has a charge storage layer 1 and an n-type s/D region 112 opposite to the s/D region 110. § The charge storage layers i 〇 6a, i 〇 6b of the cells 1, 2, 104 may be floating gates, charge trap layers or nanocrystalline layers. When the charge storage layers 1 〇 63 , : l 〇 6b are floating gates, they can be separated from the control gates 114a, 114b by the (10) 〇 composite layer. When the charge storage layers 106a, 1b, 6b are charge trapping layers, the material may include tantalum nitride (SiN), aluminum oxide or other high dielectric constant materials. When the charge storage layers 10a, 6b, 6b are nanocrystalline layers, they are nanocrystals containing ruthenium, osmium or a metal. This embodiment is exemplified by the stylization of the memory cell 1 , 2 in which the cell 104 is used as a switching transistor. In the stylized operation of this illustration, the gate voltage Vga is applied to the control gates 114 & The gate voltage vga must be large enough to allow hot electrons to be injected into the charge storage layer! 〇6a. Moreover, by controlling the magnitude of the gate voltage Vga, the programmed level of the memory cell 102 can also be controlled, · 100116292 Form No. A0101 Page 1 of 36 page 1002027339-0 201246218 Ο [0034] Store multi-bit data. The gate voltage vgb is applied to the control gate 114b' such that the channel region under the charge storage layer 1?6b is in a micro-open state. In the present embodiment, the so-called channel region is in the micro-on state, meaning that the channel Q is not fully turned on and only a small portion of electrons can flow through the channel region. The gate voltage Vgb is a starting voltage close to the memory cell 1〇4, preferably a starting voltage value of the memory cell 104±5% ^ voltage Vs and a voltage Vd higher than Vs in the positive direction are respectively applied to the S/ D zones 112, 108, and S/D zone 110 are floating. The voltage Vd must be large enough to heat the hot electrons in the horizontal direction so that the hot electrons can overcome the Si/Si 2 barrier height between the tantalum and the tantalum oxide. The voltages Vs, Vd cause electrons to flow from the S/D region 112 to the S/D region 108. Since the channel region of the memory cell 104 is in a micro-on state, only a small portion of the electrons can flow through the channel region of the memory cell 104, i.e., a smaller stylized current is formed. Moreover, the potential of the floating S/D region 110 will increase, and a significant heating field will be caused near the drain side of the memory cell 104 (S/D region 110). Thus, electrons can be injected into the charge storage layer 16a of the memory cell 102 on the source side (S/D region 110) of the memory cell 102 by the source side injection effect. In one example, the gate voltage Vga = l〇V, the gate voltage Vgb = Vth ± 5%, the voltage Vs = ground or 0V, and the voltage Vd = 3-5V. [0035] On the other hand, when the memory cell 104 is to be programmed, the memory cell 102 is used as a switching transistor. The gate voltage Vga is applied to the control gate 114b. The gate voltage Vgb is applied to the control gate 114a, the voltage Vs and the voltage Vd higher than Vs in the positive direction are applied to the S/D regions 108, 112, respectively, and the S/D region 110 is floating. The source side injection effect can be utilized, 100116292 Form No. A0101 Page 11 / Total 36 Page 1002027339-0 201246218 The source of the memory cell 104 is inverted (the charge storage layer l〇6b. Area 11〇) is injected into the electron Memory cell 1 〇 4 [0036] In an embodiment, when the layer is trapped, electrons are trapped in the memory layer 1G6a, the charge is trapped in the position _, and the electricity (4) = the storage layer 106a is near the S/D. The region no U6b〇, the position in the memory layer (10) close to the S/D region 11〇 [0037] According to one aspect of the present invention, the bias voltage thus applied is lower. 'Because the source side injection effect is used to program the memory cell 102 or remember the cell to ~, and can improve the stylization. [0038] Another FIG. 2 illustrates a non-volatile memory of an embodiment of a memory cell in accordance with the present invention. Referring to FIG. 2, this embodiment is an example of programming a memory cell 102. Among them, the memory cell 1 〇 4 is used as a switching transistor. In the illustrated stylized operation, the inter-electrode voltage Vga is applied to the control (4). The inter-electrode voltage Vga must be large enough to allow hot electrons to be injected into the charge storage layer 1Q6a. Moreover, by controlling the magnitude of the gate voltage Vga, it is also possible to control the programming level of the memory cell 1〇2 so that the delta memory can store multi-bit data. The gate voltage Vgb is applied to the control gate 丨 14b ′ such that the channel region under the charge storage layer 丨〇 6b is in a micro-on state, a fully-on state, or a transition between a micro-on state and a fully-on state. In this embodiment, the so-called channel region in the micro-on state means that the channel region is not fully turned on and only a small portion of electrons can flow through the channel region. At this time, the gate voltage Vgb is close to the initial voltage of the memory cell 104, and the value is The initial voltage value of the memory cell 104 is ± 5%; the so-called channel region is in the fully open state, meaning that most of the electrons can flow through the channel region 100116292. Form No. A0101 Page 12 / Total 36 1 1002027339-0 201246218 [0040]

[0041] At this time, the gate voltage Vgb is much larger than the initial voltage of the memory cell 104. The voltage Vs and the voltage Vd higher than Vs in the positive direction are applied to the s/d regions 112, 108, respectively, and the S/D region 110 is floating. The voltages Vs, Vd cause electrons to flow from the S/D zone Π2 to the S/D zone 108. The voltage Vd must be large enough so that the heated hot electrons can overcome the barrier height (Sl/Si02 barrier height) between the tantalum and the tantalum oxide. When the channel region of the memory cell 104 is in a micro-on state, only a small portion of electrons can flow through the channel region of the memory cell 1〇4, that is, a smaller process current is formed. Moreover, the apparent heating field is caused by the potential of the floating S/d region 11 将会 being increased toward the drain side (S/D region 110) close to the memory cell 104. Thus, the source side injection effect can be used to inject electrons into the charge storage layer 106a of the memory cell 102 at the source side (S/D region 11A) of the memory cell 1〇2. When the channel region of the memory cell 104 is completely In the on state, most of the electrons can flow through the channel region of the memory cell 1, which forms a large stylized current. Moreover, since the potential of the floating S/D region no will be pulled low, a significant heating field is caused near the drain side (s/D region 108) of the memory cell 102. Thus, electrons can be injected into the charge storage layer i 〇 6a of the memory cell 102 on the drain side (s/D region 108) of the memory cell 1 〇 2 by the channel hot electron injection effect. When the channel region of the memory cell 104 is changed between the micro-on state and the fully-on state, the channel hot electron injection effect and the source side injection effect can be utilized on the drain side of the memory cell 102 (S/D region 108). And the source side (S/D area 110) injects electrons into the charge storage layer i〇6a of the memory cell 102. 100116292 Form No. A0101 Page 13 of 36 1002027339-0 201246218 [0043] On the other hand, when the memory cell 104 is to be programmed, the memory cell 10 is used as a switching transistor. A gate voltage v g a is applied to the control terminal 114b. The gate voltage Vgb is applied to the control gate 114a such that the channel region under the charge storage layer 106a is in a micro-on state, a fully-on state, or a transition between a micro-on state and a fully-on state. The voltage Vs and the voltage Vd higher than Vs in the positive direction are applied to the S/D region 108, respectively, and the S/D region 11 is floated. The source side injection effect, the channel hot electron injection effect or the source side injection effect and the channel hot electron injection effect can be utilized on the source side (S/D area 110) and the drain side (S) of the memory cell 104. The /D region 11 2 ) or the source side (S/D region 11 〇) and the drain side (s/D region 11 2) both inject electrons into the charge storage layer 1 of the memory cell 104. [_] In one embodiment, when the charge storage layers 106a, 106b are charge trapping layers, the source side injection effect is used to program the electrons to be trapped in the charge storage layer 16a near the S/D. Position 2 of the region 110 and the position 3 of the charge storage layer 106b adjacent to the S/D region 110; the channel is hot-injected to cause the electrons to be trapped in the charge storage layer 16a near the S/D region. Position 1 of 〇8 and position 4 of the charge storage layer 丨〇6b near the S/D area 110. When the channel region under the charge storage layer 10b is changed between the micro-on state and the fully-on state, the source-side injection effect and the channel hot electron injection effect can be used in a stylization step to make the electron It is trapped in the charge storage layer 1〇63 in the position 2 near the 3/1) region 11() and in the charge storage layer 16a near the position 1 of the S/D region 108. When the channel region under the charge storage layer 106a is changed between the micro-on state and the fully-on state, the source 1002027339-0100116292 may be utilized in a stylization step. Form number A0101 U-page/total 36 pages The 201236218 side implant effect and the channel hot electron injection effect cause electrons to be trapped in the charge storage layer 106b at a position 3 near the S/D region 110 and a position 4 in the charge storage layer 106b near the S/D region 112. In this way, a single memory cell four-bit data storage is achieved. [0046] According to an embodiment of the present invention, a method of staging a memory cell in a non-volatile memory, when the electrons are injected into the positions 1, 2, 3, and 4, the stylized bias is set as shown in Table 1. [0047] Table 1 Control Gate Control Interpole S/D Zone S/D Zone 114a 114b 108 112 Position 1 Vga High Vgb Vd Vs (Ground) Position 2 Vga Low Vgb Vd Vs (Ground) Position 3 Low Vgb Vga V s (ground) Vd position 4 high Vgb Vga V s (ground) Vd

The reading method of the memory cell in the non-volatile memory according to an embodiment of the present invention is set as shown in Table 2 when the positions 1, 2, 3, and 4 of the memory cell are read. [0049] Table 2 Control Gate 114a Control Gate 114b S/D Zone 108 S/D Zone 112 Location 1 Vr >> Vth Ground Vdr Position 2 Vr >>Vth Vdr Ground Position 3 >>Vth Vr Ground Vdr Position 4 > Vth Vr Vdr Ground Form No. A0101 Page 15 / Total 36 Page 1002027339-0 100116292 201246218 According to one embodiment of the present invention, source side injection effect and channel hot electron injection are used in combination The effect is to program a memory cell with a charge trapping layer. When used in a memory cell group composed of two memory cells, a single memory cell group of four-dimensional data storage can be achieved. Moreover, the method according to an embodiment of the present invention can speed up the stylization speed of the memory cell and a larger memory window. 3 is a schematic diagram showing an initial voltage distribution of a memory cell as a switching transistor in accordance with an embodiment of the present invention. [0053] FIG. Fig. 3 shows how the voltage value range of the gate voltage Vgb is obtained. In Fig. 3, the original starting voltage distribution curve 200 of the memory cell as a switching transistor. When programmed using the source side injection effect, a low boundary start voltage profile 202 and a high boundary start voltage profile 204 are obtained. The voltage value XI of the corresponding minimum gate voltage Vgb is obtained according to the low boundary starting voltage distribution curve 202; the voltage value X2 of the corresponding maximum gate voltage Vgb is obtained according to the high boundary starting voltage distribution curve 204. When programmed by the channel hot electron injection effect, a low boundary start voltage distribution curve 206 and a high boundary start voltage distribution curve 208 are obtained. The voltage value X3 of the corresponding minimum gate voltage Vgb is obtained according to the low boundary starting voltage distribution curve 206; the voltage value X4 of the corresponding minimum gate voltage Vgb is obtained according to the high boundary starting voltage distribution curve 208. In order to make the memory cell as the switching transistor in the micro-on state, it is preferable to set the voltage value range of the gate voltage Vgb between the voltage value XI and the voltage value X2 (low Vgb shown in Table 1). Of course, the minimum value of the voltage value of the gate voltage Vgb may be slightly smaller than the voltage value XI; the maximum value of the voltage value of the gate voltage Vgb may be slightly larger than the voltage value X2 and smaller than the voltage value X3. Borrow 100116292 Form No. A0101 Page 16 of 36 1002027339-0 201246218 [0055] [0055] [0056]

[0058] 100116292 By causing the voltage range of the gate voltage V§b to cover the voltage value XI and the voltage value Χ2' and not exceeding the voltage value Χ3, it is possible to limit the use of the source side injection effect to program the memory. In order to make the memory cell as the switching transistor fully open, it is preferable to set the voltage value of the gate voltage Vgb to be larger than the voltage value χ3 (high Vgb shown in Table 1). In order to change the memory cell as the switching transistor between the micro-on state and the fully-on state, it is preferable that the operation region 21 is disposed between the voltage value χι and the voltage value X4, that is, the voltage value range of the gate voltage Vgb. Set between XI and X4. Of course, the minimum value of the voltage value of the gate voltage vgb may be slightly smaller than the voltage value XI; the maximum value of the voltage value of the gate voltage Vgb may be slightly larger than the voltage value X4. By making the voltage range of the gate sVgb cover the voltage value XI and the voltage value X4, the memory can be programmed in combination with the source side injection effect and the channel hot electron injection effect. Next, a method of applying the gate voltage Vgb to the control gate 丨丨 ", 114b to change the channel region under the charge storage layers 10a, 6b, 6b between the micro-on state and the fully-on state will be described. 4A is a timing diagram showing a voltage pulse applied during a stylized operation of a memory cell according to an embodiment of the present invention. The figure shows a voltage pulse applied during a programmatic operation of a memory cell according to an embodiment of the present invention. The relationship between the wave number and the voltage is shown in the position 2 of the charge storage layer 106a near the S/D region 110 and the position 1 near the S/D region 108 in the charge storage layer 1〇6& Referring to FIG. 2, FIG. 4A and FIG. 4B, the gate voltage Vga is applied to the control gate form No. A0101, page 17 / page 36, 1002027339-0 201246218 pole 114a. Voltage Vs and voltage Vd higher than Vs in the positive direction Applied to the S/D regions 112, 108, respectively, and the S/D region 110 is floating. The gate voltage Vgb is applied to the control gate 114b such that the channel region under the charge storage layer 106b is in a micro-on state and a fully-on state. The transition between the application of the gate voltage Vgb applied to the control gate The method of 114b includes applying a plurality of voltage pulses having different intensities to the control gate 114b. [0062] [0062] As shown in FIGS. 4A and 4B, the gate voltage Vgb is applied. It is applied to the control gate 114b in the form of a square voltage pulse. During the stylization operation, the intensity of each voltage pulse is increased by a constant, for example, by 0.5 V. The source side injection effect is used only. In the case of stylization, when the value of the gate voltage Vgb input for the first time is VI, the voltage value VI is, for example, slightly smaller than the voltage value XI; the value of the last input gate voltage Vgb is V2, and the voltage value is V2 is, for example, greater than the voltage value X2 and smaller than the voltage value X3. In the case of combining the source side injection effect and the channel hot electron injection effect, when the value of the first input gate voltage Vgb is VI, the voltage The value VI is, for example, smaller than the voltage value XI; the value of the last input gate voltage Vgb is V2, and the voltage value V2 is, for example, greater than the voltage value X4 °. Of course, a plurality of voltage pulses of different intensities can be used according to any Combination difference Figure 5A, Figure 5B is a timing diagram showing the application of a voltage pulse during a stylized operation of a memory cell in accordance with an embodiment of the present invention. 100116292 Form No. A0101 Page 18 of 36 1002027339-0 [0063] [0068] [0068] [0068] [0068]

As shown in FIGS. 5A and 5B, the gate voltage Vgb is applied to the control gate 114b in the form of a triangular voltage pulse. For example, during the stylization operation, the value of the triangular voltage pulse gradually increases from the voltage value VI to the voltage value V2 or gradually decreases from the voltage value V2 to the voltage value VI. Among them, the smaller the slope of the triangular voltage pulse wave, the better. In the case where the source side injection effect is used for stylization, the voltage value V1 is, for example, smaller than the voltage value X1, and the voltage value V 2 is, for example, greater than the electric value Χ2 and smaller than the voltage value Χ3. In the case of combining the source side injection effect and the channel hot electron injection effect into the stroke, the voltage value VI is, for example, smaller than the voltage value XI, and the voltage value V2 is, for example, greater than the voltage value Χ4. 6A and FIG. 6 are timing charts showing voltage pulse waves applied during a programmatic operation of a memory cell according to an embodiment of the present invention. As shown in Fig. 6A and Fig. 6B, the gate voltage Vgb is applied to the control gate 114b as a trapezoidal voltage pulse wave. During the stylization operation, the value of the trapezoidal voltage pulse wave gradually increases from the voltage value VI to the voltage value V2 and gradually decreases to the voltage value VI after a period of time, or the value of the trapezoidal voltage pulse wave gradually decreases from the voltage value V2 to the voltage. The value VI is gradually increased to the voltage value V2 after a period of time. In the case where the source side injection effect is used for stylization, the voltage value VI is, for example, smaller than the voltage value XI, and the voltage value V2 is, for example, greater than the voltage value X2 and smaller than the voltage value X3. In the case of combining the source side injection effect and the channel hot electron injection effect to be programmed, the voltage value VI is, for example, less than the voltage value XI, electricity 100116292 Form No. A0101 Page 19 / Total 36 Page 1002027339-0 [0070] 201246218 Pressure The value V2 is, for example, greater than the voltage value χ4. [0071] In one embodiment of the present invention, a square voltage pulse wave, a triangular voltage pulse wave, and a trapezoidal voltage pulse wave are described as an example. Of course, as long as the gate voltage Vgb is set to include the operation region 21A, other types of voltage pulse waves can be used. Figure 7 shows a circuit diagram of a non-volatile memory array in accordance with an embodiment of the present invention. The stylized method of one embodiment of the present invention is applicable to this non-volatile memory array. Referring to Fig. 7, the memory array includes a plurality of memory cells Mil to M54 arranged in a row/column array, a plurality of word lines WL1 to wu, and a plurality of bit lines BL1 to BL6. [0074] Each of the memory cells Mil to M54 has a control gate. In the same column, the memory cells M1 1 to M54 are connected in series by the S/D region to form a memory cell array ~ MR5, and each adjacent two memory cells is a memory cell group cl~cl〇. The s/D regions between the two memory cells in the memory cell groups C1 to C10 are floating. For example, the memory cells Mil~Ml4 are connected in series by the S/D region to form a memory cell array mr1, and the memory cells M21~M24 are connected in series by the S/D region to form a memory cell array MR2; and so on. The memory cells M51 to M54 are connected in series by the S/D region to form a memory cell array MR5. The memory cell Mil and the memory cell M12 constitute a memory cell group C1; the memory cell M13 and the memory cell M14 constitute a memory cell group C2; and the like, the memory cell M53 and the memory cell M54 constitute a memory cell group C10. [0075] The plurality of word lines WL1 to WL4 are arranged in parallel in the row direction. Each of the word lines WL1 WL WL4 is coupled to a control gate of a row of memory cells. For example, the word line WL1 is connected to the control gate of a row of memory cells Mil~M51; 1002027339-0 100116292 Form No. A0101 Page 20/36 pages 201246218 Character line WL2 and control of one line of memory cells M12~M52 The gate is coupled; and so on, the word line WL4 is coupled to the control gates of the row of memory cells M14 to M54. [0076] The plurality of bit lines BL1 to BL4 are arranged in parallel in the column direction. In the same column, the S/D regions of the series memory cells C1 to C10 are alternately coupled to the two bit lines. For example, the S/D regions of the series memory cells C1 C C2 are alternately coupled to the bit lines BL1 and BL2; the S/D regions of the series memory cells C3 C C4 are alternately coupled to the bit lines. BL2 and BL3; and so on, the S/D regions of the serial memory cells C9 to C10 are alternately coupled to the bit lines BL5 and BL6. Moreover, the adjacent two memory cell columns MR1 to MR5 share one bit line. For example, the memory cell array MR2 shares the bit line BL2 with the memory cell column MR1, and the memory cell column MR2 shares the bit line BL3 with the memory cell column MR3; and so on, the memory cell column MR4 shares the bit with the memory cell column MR3. The element line BL4, and the memory cell array MR4 and the memory cell column MR5 share the bit line BL5. [0077] When the memory cell M31 is programmed, a gate voltage Vga is applied to the word line WL1 coupled to the control gate thereof, and a control gate of the adjacent memory cell M32 belonging to the same memory cell group C5 is applied. The gate voltage Vgb is applied to the lighted word line wl2 to change the channel region of the memory cell M32 between the micro-on state and the fully-on state, and is respectively applied from the coupled bit line BL3 and the bit line BL4. The voltage Vd and the voltage Vs 'the memory cell M31 and the memory cell M32 share the S/D area are floating'. The bit line 3 is coupled to the S/D area of the selected memory cell M31, and the bit line BL4 is coupled adjacently. The S/D region of the memory cell M32. Thus, the source side injection effect and the channel hot electron injection effect can be used to inject electrons into the charge storage layer. 100116292 As shown in FIG. 7, when the charge storage layer of each memory cell is a charge trap layer form number A0101 page 21/36 pages 1002027339-0 201246218, two bits (bit A and bit) can be stored. Element B) is in a memory cell. By manipulating the gate voltage Vgb, the channel region of the memory cell M32 is in a micro-on state, a fully-on state, or a transition between a micro-on state and a fully-on state, and the bit A and the bit of the memory cell M31 are programmed. B or both bit a and bit B. [0082] On the other hand, in order to suppress the unselected memory cells M21 in the memory cell group C3 in which the word lines wli, WL2, and the bit line BL3 are shared with the memory cell group C5, it is stylized. The voltage Va can be applied to the bit line BL2 adjacent to the bit line BL3. The voltage Va is, for example, a voltage vd equal to 0.5 times to 1 time. In one embodiment, if the value of the voltage Va is sufficiently large, a large voltage difference is formed between the bit line BL2 and the bit line BL1, and the memory cell Mu may be programmed. In this case, by applying a voltage va to both the bit line BL2 and the bit line BL1 on the side of the bit line BL3, it is possible to suppress the unselected memory cell M21 and the memory cell 11 from being programmed. In another embodiment, if the voltage Va is approximately equal to 〇·5 times the voltage Vd, the voltage difference between the bit line BL3 and the bit line BL2 and the voltage difference between the bit line BL2 and the bit line BL1 are both It is small, so it can suppress the unselected memory cell M21 and the memory cell Mil from being stylized. Further, in order to suppress the unselected memory cell M4 in the memory cell group C7 sharing the word line wli, WL2 and the bit π line BL4 with the memory cell group, the voltage Vb may be applied to the bit of the adjacent bit line B14. Line BL5. The voltage Vb is, for example, equal to the voltage. (for example, 〇v or ground), so it is possible to suppress the unselected sinter M41 from being programmed. Further, by applying a voltage Vb (ground) to both the bit line BL5 and the bit line BL6 on the bit line BL4 side, 100116292 Form No. A0101 Page 22 / Total 36 Page 1002027339-0 201246218 suppresses unselected memory cells M41 and memory cell M51 are programmed. A method of programming a memory cell in a memory array according to an embodiment of the present invention is exemplified by a bias setting as shown in Table 3. [0084] Table 3 Bit A Bit B Bit A and B WL1 Vga Vga Vga WL2 Vgb 〇 X3) Vgb Vgb (>X2 and <X3) (X1-X4) BL3 Vd Vd Vd BL4 Vs Vs Vs ( Ov or ground) (0V or ground) (0V or ground) Unselected BL1 Va Va Va ~BL2 (0. 5~1 times (0. 5~1 times (0·5~1 times Vd) Vd Vd) Unselected BL5 Vb Vb Vb ~BL6 (0V or ground) (0V or ground) (0V or ground) Unselected WL3 (0V or ground) (0V or ground) (0V or ground) ~ WL4

FIG. 8 is a functional block diagram of a memory device 800 in accordance with an embodiment of the present invention. Referring to FIG. 8, the memory device 800 includes a controller 810 (circuit unit) and a non-volatile memory 820. The controller 810 programs the memory cells in the non-volatile memory 820 in accordance with an embodiment of the present invention. 100116292 Form No. A0101 Page 23/36 Page 1002027339-0 201246218 [0087] In summary, one embodiment of the present invention stylizes a memory cell by utilizing a source side injection effect, so that a bias voltage is applied, And can increase the speed of stylization. One embodiment of the present invention combines a source side injection effect and a channel hot electron injection effect to program a memory cell. When used in a memory cell group composed of two memory cells, a single memory cell group of four bits can be achieved. Store. The method of an embodiment of the present invention can speed up the programming speed of the memory cell, increase the component accumulation, and have a large memory margin. [0088] While the invention has been described above by way of a preferred embodiment, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0089] FIG. 1 illustrates a stylized method of memory cells in a non-volatile memory in accordance with an embodiment of the present invention. 2 illustrates a stylized method of memory cells in a non-volatile memory in accordance with another embodiment of the present invention. 3 is a schematic diagram showing an initial voltage distribution of a memory cell as a switching transistor in accordance with an embodiment of the present invention. 4A is a timing diagram of applying a voltage pulse wave during a programmatic operation of a memory cell in accordance with an embodiment of the present invention. 4B is a diagram showing the relationship between the number of applied voltage pulses and voltage during a program operation of a memory cell according to an embodiment of the present invention. 5A and FIG. 5B illustrate a memory cell 100116292 according to an embodiment of the present invention. Form No. A0101 Page 24 of 36 1002027339-0 201246218 [0096] [0097]

[0103] [0103] [0103]

[0106] [0109] [0109] [0110] A timing diagram of a voltage pulse applied during a stylized operation. 6A and FIG. 6B are timing diagrams showing voltage pulse waves applied during a stylized operation of a memory cell according to an embodiment of the present invention. 7 is a circuit diagram of a non-volatile memory array in accordance with an embodiment of the present invention. Figure 8 is a functional block diagram of a memory device in accordance with an embodiment of the present invention. [Description of main component symbols] 1, 2, 3, 4, 116a, 116b: Position 100: Substrate 102, 104, Mil ~ M54: Memory cells 106a, 106b: Charge storage layer 108, 110, 112: S/D area 114a 114b: control gate 800: memory device 810: controller A, B: bit BL1~BL6: bit line C1~C10: memory cell group MR1~MR5: memory cell VI, V2, XI, X2 X3, X4: Voltage value 100116292 Form number A0101 Page 25 / Total 36 page 1002027339-0 201246218 [0111] Va, Vd, Vs: Voltage [0112] Vga, Vgb: Gate voltage [0113] WL1 ~ WL4: Character Line 1002027339-0 100116292 Form Number A0101 Page 26 of 36

Claims (1)

201246218 VII. Patent application scope: 1. A program for staging a memory, the memory comprising a first memory cell having a first S/D region and shared with a second memory cell - a second S/D region, and the second memory cell has a third S/D region opposite to the second s/]) region, the method comprising: applying a first voltage to a first of the first memory cells a control gate; applying a second voltage to a second control gate of the second memory cell to cause the channel region of the second memory cell to be in a micro-on state; and 0 applying a third voltage to the first S /D zone, floating the second S/D zone to apply a fourth voltage to the third S/D zone, so that carriers are flowed from the third S/D zone to the first S/D zone, The carrier is injected into a charge storage layer of the first memory cell by a source side injection effect. 2. The method of staging a memory according to claim 1, wherein the second voltage is a starting voltage close to the second memory cell. 3. The method of staging a memory according to claim 1, wherein the charge storage layer is a charge trapping layer, and the carrier is trapped in the charge trapping layer of the first memory cell Q. The location of the second S/D zone. 4. A method of staging a memory, the memory comprising a first memory cell having a first S/D region and sharing a second S/D region with a second memory cell and The second memory cell has a third S/D region opposite to the second s/D region, the method comprising: applying a first voltage to a first control gate of the first memory cell; applying a first Passing a voltage to a second control gate of the second memory cell to change a channel region of the second memory cell between a micro-on state and a fully-on state; and 100116292 Form No. A0101 Page 27 of 36 page 1002027339 -0 201246218 applying a third voltage to the first S/D region, floating the second s/D region to apply a fourth voltage to the third s/D region, so that the carrier is caught from the third D region To the -S/j) region, the carrier is injected into the charge storage layer of the first memory cell by using a source side injection effect and a channel hot carrier effect. 5 · The stylized method of memory as described in claim 4 of the patent scope. The first voltage of the second memory cell is selected from the group consisting of applying a plurality of voltage pulses having different intensities to the "Xuandi-control gate, applying a triangle" a voltage pulse (Voltage Pulse) to the second control gate and applying a trapezoidal voltage pulse to one of the groups of the second control gate group. The memory staging method, wherein the charge storage layer is a charge trapping layer, and the carrier is trapped in the charge trapping layer of the first memory cell near the first S/D region and The position of the second s/j) region. The stylized method of the memory cell in the memory array, comprising: applying a first voltage to a first memory cell via a first word line Controlling a gate; applying a second voltage to a second control gate of a second memory cell adjacent to the first memory cell via a second word line to make the channel region of the second cell In a micro-on state or a fully-on state, wherein the first memory cell has a first The S/D zone is shared with the second memory cell - the second S/D zone ' and the second memory cell has a second S / D zone opposite to the second s/D zone, via a first bit The line 'applies a third voltage to the first-S/D area 100116292 Form No. A0101 Page 28/36 pages 1002027339-0 201246218 The second S/D area is floated; and via a second bit a line, applying a fourth voltage to the third S/D region > wherein a carrier flows from the third S/D region to the first S/D region to utilize a source side injection effect or a channel hot carrier The method of injecting a device into a charge storage layer of the first memory cell. The method of staging a memory cell in the memory array according to claim 7, wherein the charge storage layer is a charge trapping layer. The carrier is trapped in the charge trapping layer of the first memory cell near the second S/D region, and the charge trapping layer of the first memory cell is adjacent to the first S/D region a position or a position in the charge trapping layer of the first memory cell adjacent to the first S/D region and a position close to the second S/D region. The method for staging a memory cell in the memory array according to the seventh aspect, further comprising: applying a fifth voltage to a third bit line adjacent to the first bit line to suppress sharing with the first memory cell of the s Xuan The first character line and the unselected memory cell of the first bit line are programmed. The method for staging the memory cell in the memory array according to claim 7 of the patent application scope includes: Applying a sixth voltage to a fourth bit line adjacent to the second bit line to suppress a non-selected memory cell program sharing the first word line and the second bit line with the first memory cell Chemical. 100116292 Form No. A0101 Page 29 of 36 1002027339-0