TWI473098B - Low voltage programming in nand flash - Google Patents

Description

Reverse voltage stylization of gate flash memory

This invention relates to flash memory technology, and more particularly to flash memory suitable for low voltage stylization and erase operations in an anti-gate configuration.

Flash memory is a class of non-volatile integrated circuit memory technology. Traditional flash memory uses floating gate memory cells. As the density of the memory device increases, the floating gate memory cells are closer together, and the charge interaction stored in the adjacent floating gates causes a problem, thus forming a limitation, so that the floating gate density of the floating gate is used. Unable to upgrade. Another type of memory cell used in flash memory is called a charge trapping memory cell, which uses a charge trapping layer instead of a floating gate. The charge trapping memory cell utilizes a charge trapping material that does not cause interaction between individual memory cells as a floating gate, and can be applied to high density flash memory.

A typical charge storage memory cell includes a field effect transistor (FET) structure including a source and a drain separated by a channel, and a gate separated from the channel by a charge storage structure, wherein the charge storage structure comprises A tunneling dielectric layer, a charge storage layer (floating gate or dielectric layer), and a barrier dielectric layer. Earlier conventional designs, such as SONOS devices, in which the source, drain and channel are formed on the germanium substrate (S), the tunneling dielectric layer is over the germanium oxide (O), and the charge storage layer is formed of tantalum nitride. (N), the barrier dielectric layer is formed of ruthenium oxide (O), and the gate is polycrystalline germanium (S).

Flash memory devices can typically be implemented using either a NAND or a NOR architecture, but can be other architectures, including an AND architecture. This NAND architecture is favored especially for its high density and high speed advantages in data storage applications. The inverse OR gate (NOR) architecture is suitable for other applications such as program storage, because random access is an important functional requirement. In a NAND architecture, the stylization process typically relies on Fuller-Nordheim (FN) tunneling and requires high voltages, typically on the order of 20 volts, and requires high voltage transistors for processing. This extra high-voltage transistor and the transistors used in logic and other data streams are in the same integrated circuit, which increases the complexity of the process. This will increase the manufacturing cost of the device.

Therefore, there is a need to provide a new memory technology that can be programmed with low voltage in a NAND architecture.

The memory device described herein is configured for low voltage operation, and includes a plurality of memory cells arranged in series in a semiconductor body, for example, can be applied to a reverse gate array of an anti-gate array, having a plurality of characters. The line is coupled to the corresponding memory cell. The control circuit is coupled to the plurality of bit lines and the semiconductor body to be programmed to program a selected memory cell by hot carrier injection using a controlled word line voltage to a target memory cell Above, this is referred to as the switching voltage V-SW. A source extreme voltage is applied to one side of the string, which is commonly grounded or other specific voltage as the source terminal voltage. The side of the selected memory cell that applies the source extreme voltage during programming is referred to herein as the "equivalent source terminal" or "equivalent source." A source extreme voltage is applied to the other side of the string, which is to apply a supply potential, commonly referred to herein as VD, which is other specific voltages as the 汲 extreme voltage. The side of the selected memory cell that applies the extreme voltage during programming is referred to herein as the "equivalent 汲 extreme" or "equivalent 汲". In order to control the switching of the conductance of the memory cell, the V-SW is set to a bias condition during a portion of the stylized interval to establish a condition in the body adjacent to the target memory cell to support a sufficient thermal field (bungee-to-source voltage) and sufficient The channel current is in the target memory cell, wherein a stylized voltage is applied to the target memory cell to induce hot carrier injection. The hot carrier injection using this program can be implemented by applying a control circuit that applies a programmed voltage to the selected word line (corresponding to the target memory cell) in the stylized interval, which applies the switching voltage V-SW to the selected An adjacent word line on the equivalent source side of the word line applies a turn-on voltage to the other word line and connects the semiconductor body between the bit line and the common line to enable the flow of the program current.

In the stylized interval, the selected word line is biased by a stylized voltage that is sufficient to overcome the channel hot carrier barrier class. However, this stylized voltage can be much smaller than the voltage required for typical FN stylization. The word line corresponding to the plurality of memory cells receives a turn-on voltage that is lower than the stylized voltage to suppress interference of other memory cells. The switching voltage in the stylized interval is also similarly lower than the stylized voltage to suppress the interference of the switching memory cell.

For a reverse gate sequence embodiment, a first switch (ground selection switch or bottom bit line switch) is provided at a first end of the plurality of transistors, and a second switch (serial selection) A switch or a top bit line switch is provided at a second end of the plurality of transistors. In this embodiment, the control circuit operates in the stylized interval to turn on the first and second switching switches to cause current to flow in the semiconductor body. A select line (eg, a serial select line SSL or a ground select line GSL) may be coupled to the first and second change switches in parallel with the plurality of word lines. When the selected memory cell is adjacent to one of the select lines, the switching voltage V-SW can be applied to the switch instead of the memory cell. Alternatively, a dummy word line can be added to the string, which operates to receive the V-SW to program the first or last memory cell in the reverse gate sequence.

The control circuit is operable to apply a common voltage (eg, source or 汲 extremes) when the second plurality of memory cells are coupled to the same plurality of word lines, such as a parallel reverse gate sequence on one of the selected bit lines. Voltage) to both the first end and the second end of the plurality of transistors. In this arrangement, the semiconductor body regions at both ends of the selected word line are biased to a similar voltage level to prevent hot carrier injection on the unselected series.

The invention also provides a method for inducing a memory cell hot carrier injection to be programmed in one of the inverse gate arrays of the reverse gate array, which is based on using the V-SW adjacent to the selected memory cells to cause carriers. Flow and thermal fields. A stylized potential higher than the hot carrier injection barrier is applied to the selected memory cell, and then the drain-to-source voltage passes through the selected memory cell and the carrier flow in the selected memory cell reaches a sufficient temperature to support the hot load. Sub-injected class.

The objects, features, and embodiments of the present invention will be described in the accompanying drawings.

The embodiments of the present invention are described in detail with reference to the following Figures 1 to 22.

1A and 1B are cross-sectional views showing a conventional technique of a NAND architecture flash memory in which a plurality of dielectric charge trapping flash memory cells are arranged in series to form a reverse gate series and a bias supply. FN tunneling is used for stylization. Figure 1A shows a bias voltage for a reverse gate train comprising a target memory cell on a selected bit line, and Figure 1B shows a bias voltage for an unselected bit line on the gate sequence. A technique for implementing a backlash flash memory using an energy gap engineering SONOS charge trapping technique can be found in U.S. Patent No. 7,315,474, issued toU.S. The reverse gate series can be implemented using a number of different configurations, including fin field effect transistor technology, shallow trench isolation technology, vertical reverse gate technology, and the like. For an example of certain vertical reversal gate structures, see European Patent No. EP 2048709 to Kim et al., entitled "Non-volatile memory device, method of operating same and method of fabricating the same." Another similar structure is used for floating gate memory cells, using conductive floating gates.

Referring to FIG. 1A, the memory cell is formed on a semiconductor body 10. For an n-channel memory cell, the semiconductor body 10 can be an isolated p-well located in a deep n-well region of a semiconductor wafer. Alternatively, the semiconductor body 10 can be isolated by a dielectric layer or other material. A p-channel memory cell can also be used in some embodiments, wherein the doping material of the semiconductor body is n-type.

The plurality of flash memory cells can be arranged in a series of bit line directions that are orthogonal to the direction of the word line. The word lines 22-27 extend through a number of parallel anti-gate trains. Nodes 12-18 are n-type regions (for n-channel devices) in the semiconductor body and serve as source/drain regions for the memory cells. A first switch formed of a MOS transistor has a gate in the ground select line GSL 21 coupled to the corresponding memory cell having the first word line 22 and formed by the n-type region in the semiconductor body 10. One of the contacts 11 between. This contact 11 is connected to the common source line CS 30. A second switch formed by the MOS transistor has a gate in the string select line SSL 28 coupled to the corresponding memory cell having the last word line 27 and formed by the n-type region in the semiconductor body 10. One of the contacts 19 is between. This contact 19 is connected to the bit line BL 31. The first and second switching switches in this exemplary embodiment are MOS transistors, in this example thyristor dielectric layers 7 and 8.

In this illustration, there are six memory cells in this series for the sake of simplicity. In a typical configuration, an inverse gate sequence can contain 16, 32 or more memory bank arrangements. The word lines 22-27 corresponding to these memory cells have a charge trapping structure 9 between the word lines and the channel regions in the semiconductor body 10. The charge trapping structure 9 in this memory cell can be a dielectric charge trapping structure, a floating gate charge trapping structure, or other suitable flash memory structure suitable for programming using the techniques described herein. In addition, no junctions have been developed in embodiments that are inverse gate flash structures in which nodes 13-17, and optionally nodes 12 and 18, may be omitted from this configuration.

FIG. 1A shows a cross-sectional view of a conventional technique NAND architecture flash memory in which FN tunneling is induced to program a biased pattern of memory cells corresponding to word line 24. According to the bias voltage shown here, the ground select line GSL is biased to approximately 0V and the common source line is grounded such that the first switch corresponding to the ground select line GSL 21 is off and the tandem select line SSL bias To about V _CC and the selected bit line is also grounded, so that the second switch corresponding to the serial select line SSL 28 is turned on. Under these conditions, the semiconductor body in region 33 associated with the gate series is precharged to about 0V. The selected word line 24 is biased to a high voltage stylized class V-PGM, which in some embodiments can be on the order of 20 volts. The unselected word lines 22, 23, 25-27 are biased to a turn-on voltage V-PASS which is less than a V-PGM that is less than a stylized voltage that can suppress unselected cells in the series. As a result, electrons tunnel into the charge trapping structure of the selected memory cell.

FIG. 1B is a cross-sectional view showing a conventional flash memory (NAND) architecture flash memory, which shares the bias of the uncharacterized bit lines of the gate lines 22 to 27 and the gate series of the gate array. schematic diagram. As can be seen from the figure, the ground selection line GSL and the string selection line SSL of all the word lines are the same as those shown in FIG. 1A. Similarly, the common source line 30 is also grounded. However, the unselected bit lines are biased to a level of approximately V _CC . This will turn off the second switch, which corresponds to the string select line SSL, and decouples the semiconductor body in region 35 from the unselected bit line BL32. As a result, the semiconductor body in region 35 will self-pressurize by the capacitive coupling generated by the voltage applied to word lines 22-27, which can prevent the charge trapping structure in the memory cells of the unselected inverse gate series from being sufficiently disturbed. The electric field is formed. The so-called incremental step pulse programming (ISSP) operation based on capacitive self-pressure is well known in the art.

Figure 2 shows a stylized bias for selecting a NAND string, which is programmed using the hot carrier of the prior art.

In FIG. 2, the common source line CS 30 is grounded, and the selected bit line 31 is also coupled to V _D . The ground selection line GSL 21 is coupled to a pass voltage to turn on the first changeover switch 42 to couple the semiconductor body to the common source line CS 30. The serial select line SSL 28 is biased to a pass voltage to turn on the second switch 43 and couple the semiconductor body to the selected bit line 31, which is tied to V _D or a bit threaded bias Coupling. The word line corresponding to the target memory cell 40 receives the stylized pulse V-PGM. As a result of this stylized bias, a channel current IPGM flows in the semiconductor body in the series, which is indicated by trace 55 when fully turned on. Furthermore, the drain-to-source voltage (interval 56) through the target memory cell is small, and the voltage drop distribution along this series is shown by V _D to the trace 57 in the V _CHANNEL diagram. As a result, the heating electric field corresponding to the drain-to-source voltage in the stylized section of the target memory cell is small, so even if the channel current in this mode of operation is sufficiently high, the hot carrier is summarized. Injection is slow and inefficient. Therefore, hot carrier injection cannot be achieved to an important degree in the anti-gate stylization.

Figure 3 shows the programmed bias of the hot carrier injection described herein. It must be noted that for the n-channel embodiment, this hot carrier includes electrons. For p-channel embodiments, a similar biasing technique can be applied to induce thermowell injection, where the hot carrier includes a hole. The embodiments described herein are n-channels, but alternative p-channel embodiments may also be referred to as hot carrier injection.

The word line coupled to the memory cell 41 adjacent to the common source line CS 30 end of the target memory cell 40 receives a two-stage switching voltage V-SW that is arranged to cause an effective hot load during a period of the stylized interval. Sub-injection conditions. Under a biased condition of a stylized section, region 50 in semiconductor body 10 is precharged to a drain voltage V _D in response to a line between the target word line receiving the V-PGM and the second switch 43 The turn-on voltage V-PASS (汲 extreme) on all word lines. The region 51 in the semiconductor body 10 is coupled to the common source line CS 30 of approximately 0V and the voltage V-PASS (source terminal) is coupled to the switching memory cell 41 and the first switching switch 42. The word line between the two is precharged to the effective source voltage Vs. This V-PASS can be the same voltage as the V-PASS or a different voltage, depending on a particular application or stylized condition. Furthermore, this turn-on voltage V-PASS can be varied depending on the position on the string. The voltage level in region 50 and the reference voltage level in region 51 are isolated by the depletion channel region 52 underneath the switching memory cell 41 when the voltage V-SW is lower than the threshold voltage of the memory cell 41, and as shown in I _CHANNEL. Trace 60 in the figure generally has no current flowing through it. When the voltage V-SW reaches a stylized range, the current in the semiconductor body is increased to a stylized current level sufficient to support hot carrier injection, for a class 62 between the fully open channel current class 61 and the fully closed channel current class 60. between. In addition, through the voltage drop of the memory cell 41 channel 52, the region 64 shown in the track 63 of the V _CHANNEL map absorbs most of the voltage drop between the programmed bit line voltage and the common source line voltage. A thermal electric field is generated around the target memory cell 40, which supports hot carrier injection.

In this example, as with all of the examples shown herein, the first and second switchers (42, 43) are implemented using field effect transistors in series with the memory cells in the series. In the example shown in FIG. 2A, the gate dielectric layer of the field effect transistor is a single layer structure and typically includes hafnium oxide or nitrogen doped cerium oxide. In other embodiments, the gate dielectric layer of the field effect transistor is a single layer structure and typically includes hafnium oxide or nitrogen doped antimony oxide. A field effect transistor for switching switches (e.g., 42, 43) in the series can use a multi-layer gate dielectric layer, including the same gate dielectric layer as all of the charge trapping structures used in the series. This scheme can simplify the process of memory cells. In such an embodiment, the first and second switchers can be characterized as "memory cells." If necessary, the channel length of the field effect transistor as the switch can be longer than the channel length of the memory cell. Because, compared to the Fourier-Nordheim (FN) tunneling, using the relatively low operating voltages of the techniques described herein, the interference of memory cells in the array can be suppressed when the target cell is programmed. In addition, because the stylized line voltage used in this stylized method is lower than that of the conventional FN-based tunneling-based memory device, the anti-gate flash memory is also low. The vertical electric field of the layer is also small. For this reason, it is not necessary to use a high voltage drive and the reliability will be better. In addition, with the floating gate device, even if the memory cell has a lower gate coupling ratio due to component miniaturization, the stylized speed is not greatly reduced due to such a low gate coupling ratio. At the same time, because of the use of low voltage devices, the process can be simplified by omitting very high voltage devices.

A method of inducing hot carrier injection into a target memory cell during operation is to switch memory cell conductance by applying a switching word line voltage to control the target memory source terminal. The conductance is controlled such that it is sufficient to turn off the current in the switching memory cell and the reverse gate sequence can be divided into two regions, including an equivalent source region and an equivalent drain region. The voltage drop in the equivalent source region and the equivalent drain region is small. As a result, the applied bit line voltage mostly switches the memory cells through this. In addition, the conductance is sufficient to turn on this small amount but sufficient current can flow through the switching memory cell and the target memory cell, wherein the carrier is heated and injected into the charge trapping structure of the target memory cell.

The voltage on the selected bit line and the common source line should be high enough to induce a hot carrier heating electric field in the target memory cell. The voltage applied to the ground select line and the string select line should be high enough to fully turn on the voltage of the selected bit line and the common source line. The voltages applied to the ground select line and the string select line can be different. Similarly, the voltage applied to the unselected word line should be high enough to fully turn on the voltage applied to the selected bit line and the common source line. It must be noted that the turn-on voltage at the equivalent source terminal and the turn-on voltage at the equivalent 汲 terminal can be different. Similarly, it can vary along the length of the string if necessary. For word lines corresponding to the memory cells to be programmed, the applied stylized voltage should be high enough to cause electron injection. During the stylization operation, the voltage on the switching word line should fall within an operating range such that the drain-to-source voltage and stylized current in the target memory cell are high enough to generate hot carrier injection.

Figure 4 shows a layout of four inverted gate trains 101, 102, 103, 104, which are respectively connected to the respective bit lines via a serial selection transistor (e.g., 112) and a ground selection transistor (e.g., 111). BL-1 to BL-4 are coupled to a common source line CS 105. For purposes of illustration, the bias voltage shown herein stunts a target memory cell 100 corresponding to the word line WL(i) of the gate sequence 101. The first switch transistor transistor 111 is turned on by a turn-on bias voltage on the ground select line GSL, such as V-GSL (eg, the same voltage as V _D ) to pass through the common source line CS 105 to reverse the gate sequence equivalent source terminal Charge to the ground. The second switch transistor 112 is connected by a string select line on-line voltage V-SSL on the tandem select line, for example, higher than the bit line voltage V _D , and is opposite to the bit string selected by the gate sequence. Line BL-1 to bit line voltage. The switching memory cell 113 corresponding to the word line WL(i+1) is adjacent to the target memory cell 100. Therefore, the word line WL(i+1) receives the V-SW in the stylized section. On the unselected bit line, the unselected bit line voltage is set to ground, or a level close to the common source line CS, so that both the equivalent source and the equivalent 汲 extreme are precharged to the same or The proximity voltage causes the hot carrier injection rate to be lower. Note that when the target memory cell is at the first word line WL(0), the serial selection line SSL can be used to apply a switching voltage V-SW, which can be adapted to use the switching memory cell 111 instead of a memory cell. To operate.

Figure 5 is a diagram showing an example timing diagram of the bias voltage during operation of Figure 4. The unselected bit line (e.g., BL-2) and the common source line CS are biased to ground in this interval. The serial select line SSL and the ground select line GSL are coupled to approximately 10V. Moreover, both the equivalent source and the equivalent 汲 extreme of the unselected word line in this example are coupled to approximately 10V. The selected bit line (BL-1) is coupled to a sufficiently high drain voltage level in this stylized section, which can generate a hot carrier injection, for example 4V. The selected word line receives a stylized pulse of approximately 14V in the stylized section of this example. The switching voltage V-SW is dynamically set to a level according to a threshold voltage of the switching memory cell adjacent to the target memory cell. For a low threshold voltage switching memory cell, its V-SW may be -4V for example. Alternatively, the switching voltage V-SW can be set to scan through an operating range based on the distribution of the threshold voltages in the memory array, which will be described in more detail below.

Fig. 6 shows the change of the threshold voltage and the stylized time when the hot carrier injection uses the adjustment bias voltage in Fig. 5 and the stylized potential used for FN tunneling is the same as the stylized potential used for hot carrier injection. relation chart. As can be seen from the figure, the track 1130 shows that the programmed time for hot carrier injection when switching the memory cells in a low critical state is on the order of 3 microseconds. Trace 1120 shows that the stylized time for FN tunneling at a similar stylized potential can exceed 100 milliseconds. Thus, the trim bias described herein can achieve a faster stylization at relatively low voltages.

In contrast, representative bias levels for the erase operation are shown in the table below.

Fig. 7 is a graph showing the relationship between the applied switching voltage V-SW and the change of the threshold voltage, the track 120 is for a switching memory cell having a threshold voltage of -3 V, and the track 121 is for a switching memory cell having a threshold voltage of 1 V. . Trace 120 shows that the preferred switching voltage range for the low threshold voltage memory cell in this example is approximately between -4.6 and -2.7V. The preferred switching voltage range for a 1V threshold voltage memory cell is approximately between -0.2 and +1.6V. These results show that the preferred switching voltage range for switching memory cells is related to the threshold voltage of the switching memory cell. This phenomenon occurs because the conductance of the switching memory cell is determined by the difference between the switching voltage applied to its bit line and the threshold voltage. Since in most cases the switching memory cell is a memory cell, its threshold voltage will vary with the value of the data stored therein.

Figure 8 is a graphical representation of an inspired threshold voltage distribution 250 showing a larger inverse gate array including a plurality of inverted gate trains. Here, the threshold voltage distribution 250 has a threshold voltage value for a given number of memory cells at a value X3, another memory cell has a threshold voltage value at X4 and another memory cell has a threshold at a central value XC. Voltage value. For the three representative threshold voltage values described above, it has an appropriate switching voltage range. Therefore, for a memory cell having a threshold voltage value at X3, the appropriate switching voltage range is 251. For a memory cell having a threshold voltage value at XC, the appropriate switching voltage range is 252. For a memory cell having a threshold voltage value at X4, the appropriate switching voltage range is 253. As a result, for an entire array, its appropriate switching voltage range can be represented by the distribution 255, extending from an X1 value to an X2 value. Therefore, in a given array of given stylized operations, the switching voltage needs to fall within the range from X1 to X2. In a representative system, the outer edge of the appropriate switching voltage range for a fast stylized operation low value X1 is an appropriate switching voltage range that occurs at approximately 0~1V below X3 and for a fast stylized operation high value X2. The outer edge occurs at approximately 0~1V greater than X4. In other systems, the appropriate switching voltage range can extend approximately 2~3V outside of this threshold voltage range.

Using this technique in a trans-gate memory device, the algorithm that applies the appropriate switching voltage to the switching memory cell adjacent to the target memory cell will take into account the variation of the threshold voltage. Figure 9 shows a mechanism for applying a switching voltage through this desired range. This algorithm involves switching the voltage class in one step (stepped) of a series of stylized pulses, which has a verification and retry step after each programmed pulse. As shown in Fig. 9, the first pulse 261 should have a slightly smaller size than X1. Each pulse in this series (such as pulse 262) should be stepped by a small voltage, for example 0.2 volts. The last pulse 263 in this series should have a slightly larger size than X2. In an alternate embodiment, a one-step subtraction series can be applied, starting with a pulse that is slightly larger than X2 and ending with a pulse that is slightly smaller than X1. The advantage of a stepping pulse is that it can generate a square wave using a simpler circuit, but the disadvantage is that the programmed time of a given target memory cell may change depending on its neighboring switching memory cells.

Figure 10 shows an alternative embodiment that uses a slope switching voltage. In the stylized interval, the switching voltage can be gradually increased from a positive slope 264 that is slightly smaller than X1 to a peak greater than X2, and then falls back below X1 along line 265. In this manner, a portion of at least the stylized interval can pass through the appropriate switching voltage range of the switching memory cell. For this slope switching voltage, the slope of slope 264 should be small enough to ensure that all memory cells have sufficient reaction time to program the hot carrier injection of the target memory cell. This slope can vary depending on the type of memory cell. It is generally expected that different reverse gate configurations have a slope between 0.1 volts per microsecond and 10 volts per microsecond.

Figure 11 shows a falling slope switching voltage. In the switching pulse shown in Fig. 11, the switching voltage starts from a level slightly larger than X2, and falls along line 274 to a slightly smaller minimum value than X1, and then returns to the higher level along line 275.

Figure 12 shows a switching voltage pulse 285 having a slope leading and trailing edge, wherein the pulse increases from a slightly smaller class than X1 to a class slightly larger than X2, and then decreases from a class greater than X2 back to less than The class of X1. This pulse with a slope leading and trailing edge (284, 285) switching voltage can achieve a faster stylized speed at the slope leading and trailing edges, which is about 0.1 volts per microsecond to 10 volts per microsecond. between. Also shown is a reverse pulse 286 in which the pulse is reduced from the level greater than X2 to the level less than X1 at the leading edge 286, and thereafter increased from the level less than X1 to the level greater than X2 at the trailing edge 287.

Other switching voltage mechanisms can also be used. For example, the threshold voltage of the switching memory cell can be sensed first, and then a narrower switching voltage range is applied to match the threshold voltage.

Figure 13 is a diagram showing the bias conditions of the multiple switching memory cells 112, 113, 114 adjacent to the common source CS terminal of the array target memory cell 100. Using multiple switching memory cells, for example two, or three memory cells in this example including switching memory cells 112, 113, 114, which have a higher threshold voltage, will dominate this at a given switching voltage The performance of stylized operations. This makes it possible to tighten the distribution of the appropriate switching voltage. Therefore, FIG. 13 is a circuit diagram showing a layout of two reverse gate series 101, 102, which are respectively connected to the respective bit lines BL-1 via the serial selection transistor and the ground selection transistor. BL-2 is coupled to a common source line CS 105. The bias voltage shown here stylizes a target memory cell 100 corresponding to the word line WL(i) of the gate sequence 101. The first changeover switch transistor 111 is biased by V _D or other on-bias bias on the ground select line GSL to couple the anti-gate sequence to the common source line CS 105 via the common source line CS 105. The second switch transistor 112 is connected to the series select line on-voltage V-PASS on the tandem select line and the voltage V _D on the selected bit line BL-1, which will be opposite to the selected bit and the selected bit. The element line BL-1 is coupled. The three switching memory cells 112, 113, 114 corresponding to the word lines WL(i+1), WL(i+2), WL(i+3) are adjacent to the target memory cell 100. Thus, word lines WL(i+1), WL(i+2), and WL(i+3) receive V-SW to support the hot carrier injection stylized interval. On the unselected bit line, it is coupled to 0V, and the equivalent source and equivalent drain regions are biased to ground via unselected bit line BL-2 and common source line CS 105.

It is also possible to adjust the bias voltage and array configuration instead. A representative application is shown in Figure 4, which involves a bias voltage such that the current on the reverse gate train flows from the common source line (low voltage) to the selected bit line (high voltage). Figure 14 shows the opposite direction current in an alternate embodiment. In the example shown in Figure 14, the selected bit line is biased to ground and the common source line is biased to the drain potential V _D . The target memory cell corresponding to the word line WL(i) receives the stylized potential. The switching voltage is applied to the word line WL(i-1) opposite to the terminal line of the gate string. The bias voltage of the selected bit line of the ground potential is used to establish an equivalent source region between the tandem selection switch 112 and the target memory cell 156. Switching memory cell 155 receives the switching voltage whose supply switches the conductance of the memory cell to produce the previously described hot carrier injection conditions. The unselected bit line receives the supply potential, such as V _D , which is the same or close to the bias applied to the common source line CS. Therefore, the equivalent source and the equivalent drain region of the unselected gate series have similar voltages and suppress hot carrier injection.

Figure 15 shows another alternative embodiment in which the bias voltage is not selected and the boosted equivalent source region is used in the gate train to suppress stylized interference. Under this arrangement, the bias voltage is similar to that in Fig. 14, except that the series select line is set to V _D , which is the same as the bias voltage V _{D of the} bit line BL-2. As a result, the equivalent source region 180 of the semiconductor body of the string 102 is isolated from the unselected bit lines. In addition, it is also isolated from the common source line as a result of the word line WL(i-1) receiving the switching voltage, isolating the equivalent drain region 181 from the equivalent source region 180. The isolated equivalent source region 180 is self-boosted by capacitive coupling at the V-PASS potential because the stylized interval voltage pulse has a voltage class close to the equivalent drain region 181. In addition, the current in this series is also blocked, suppressing hot carrier injection.

When the programmed target memory cell is the first memory cell in the gate sequence, adjacent to the ground selection line, causing no memory cell adjacent to the equivalent source terminal of the target memory cell can be used as the switching memory. Cell. In contrast, when the programmed target memory cell is the last memory cell in the gate sequence, adjacent to the string selection line, and the string is biased such that the equivalent source terminal is above, again It causes the memory cell to be adjacent to the equivalent source end of the target memory cell and can be used as a switching memory cell. In these cases, the tandem select line or ground select line can control the conductance of the semiconductor body in a manner that acts as a memory cell at a suitable bias voltage. In an alternate embodiment, a dummy word line can be used.

Figure 16 shows a schematic layout similar to the word line of Figure 3 and the source-drain series of the gate array, in addition to the bottom dummy word line BDWL adjacent to the ground selection line GSL and The top dummy word line TDWL is adjacent to the string selection line SSL. If a one-way current operation is used, the dummy word line can be placed only on one side. As shown, the source drain series 500-503 are vertically extending on the page. The horizontal wires are located above the source drain series 500-503. These horizontal wires include a string select line SSL, a top dummy word line TDWL, word lines WL(0) through WL(N-1), and a bottom dummy word line BDWL. In addition, the horizontal wire further includes a ground selection line GSL and a common source line CS. The dummy word lines at the upper and lower ends of the series can be used as a control for a dummy memory cell when the hot carrier injection is programmed as previously described.

Figure 17 shows a layout of the seven reverse gate series 201~207 arranged in a virtual ground and gate structure. In the virtual grounded anti-gate architecture described herein, the bit line is simultaneously a bit line coupled to the sense amplifier and a reference line coupled to the reference voltage source, depending on the row position being accessed. The reverse gate sequence is coupled to the corresponding set of bit lines BL-1 to BL-8 by the top bit line selection transistor BLT and the bottom bit line selection transistor BLB. For the sake of explanation, the bias voltage shown in the figure is a bias voltage that stylizes a target memory cell 300 corresponding to the word line WL(i) in the gate sequence 204. The first changeover switch transistor 301 selects VPASS on the transistor BLB from the bottom bit line to couple the reverse gate sequence 204 with the bit line BL-5, and BL-5 is grounded. The second switch transistor 302 selects V-PASS on the transistor BLT from the top bit line to couple the AND gate column 204 to the bit line BL-4, which is biased to VD. All of the bit lines BL-1 to BL-3 on the left side of the reverse gate train 204 are biased to VD. All of the bit lines BL-6 to BL-8 on the right side of the reverse gate train 204 are biased to ground. The switched memory cell 304 corresponding to the word line WL(i+1) is adjacent to the target memory cell 300. Therefore, the word line WL(i+1) receives the V-SW. Region 310 in the semiconductor body is biased to an equivalent drain voltage VD, thus providing an equivalent drain region opposite gate array 204. On the unselected bit lines on the right side, the equivalent drain and source regions 312 and 313 are biased to ground by bit lines BL-5 through BL-8 to avoid interference with the memory cells on the series. On the unselected bit lines on the left side, regions 314 and 315 are coupled to relatively high voltages (e.g., VDs on bit lines BL-1 through BL-3) to avoid interference of memory cells on the series. Therefore, when the switching memory cell 304 receives a switching voltage to cause hot carrier injection, the target memory cell 300 is programmed by hot carrier injection, and other memory cells in the array are not disturbed.

Figure 18 shows a schematic diagram of the adjustment bias similar to that of Figure 17 arranged into a virtual ground-to-gate architecture in which the switching transistor is on the other side. The reverse gate sequence is coupled to the corresponding set of bit lines BL-1 to BL-8 by the top bit line selection transistor BLT and the bottom bit line selection transistor BLB. For the sake of explanation, the bias voltage shown in the figure is a bias voltage that stylizes a target memory cell 320 corresponding to the word line WL(i+1) in the gate sequence 204. The first changeover switch transistor 321 selects V-PASS on the transistor BLB from the bottom bit line to couple the reverse gate sequence 204 with the bit line BL-5, and BL-5 is biased to VD. The second switch transistor 322 selects V-PASS on the transistor BLT from the top bit line to couple the AND gate column 204 to BL-4, which is grounded. All of the bit lines BL-1 to BL-3 on the left side of the gate series 204 are biased to ground. All of the bit lines BL-6 to BL-8 on the right side of the reverse gate train 204 are biased to VD. The switched memory cell 324 corresponding to the word line WL(i-1) is adjacent to the target memory cell 320. Therefore, the word line WL(i-1) receives the V-SW. The region 331 in the semiconductor body is biased to an equivalent gate voltage VD. On the unselected bit lines on the right side, regions 332 and 333 are biased to a relatively high voltage to avoid interference with the memory cells on the series. On the left unselected bit line, regions 334 and 335 are biased to ground by bit lines BL-1 through BL-4 to avoid interference of memory cells on the series. Therefore, hot carrier injection occurs in the target memory cell 320, and other memory cells in the array are not disturbed.

Figures 19, 20 and 21 show the feasibility of using shared bit line or word line decoding techniques in very densely packed very high density arrays, such as those encountered with certain 3D and advanced 2D array structures. The use of shared bit lines or word lines allows for the application of drivers and buffers that are more spaced than required in a generally densely packed array. In these configurations, there are a plurality of bit lines and a plurality of common source lines, wherein the first inverse gate sequence is coupled to the first bit line of the plurality of bit lines, and the source lines are shared with the plurality of lines The first common source line is coupled, and the second anti-gate string is coupled to the first bit line of the plurality of bit lines, and is shared by a second one of the plurality of source lines The source lines are coupled. The first and second anti-gate trains can be arranged adjacent in the column direction as shown in Fig. 19. The first and second anti-gate trains may also be arranged adjacent to each other in the row direction as shown in Fig. 20 or vertically stacked in a three-dimensional configuration as shown in Fig. 21.

In Fig. 19, a shared bit line structure is shown. The reverse gate trains 380, 381, 382, 383 are shown in the figure, wherein the reverse gate trains 380, 381 are coupled to the bit line BL1 via the shared contacts 398. Similarly, the AND gate series 382, 383 are coupled to the bit line BL2 via the shared contact 399. The two common source lines CS1 and CS2 are 395 and 396, respectively, which are arranged for use in the four series. The gate series 380, 382 are coupled to the common source line CS1 395, and the gate series 381, 383 are coupled to the common source line CS2 396. The stylized adjustment bias of the target memory cell 400 is shown in the figure. In this example, the target memory cell is coupled to word line WL7. The switching voltage V-SW is applied to the word line WL8. The turn-on voltage is applied to the unselected word line and ground select line GSL. The serial selection line SSL is coupled to the supply potential VD. The first common source line CS1 is coupled to the positive 4V, and the second common source line CS2 is coupled to the 0V. This configuration causes the semiconductor body having the equivalent source region of the stylized target memory cell 400 to be interposed between the SSL switch and the target memory cell, and the semiconductor body having the equivalent drain region is interposed between the GSL switch and the target memory cell. between. The memory cells 401, 402, and 403 of the shared word line WL7 are induced without being disturbed because the suppression condition is induced. For the memory cell 401, the memory cell is coupled to the second common source line CS2 on the GSL side of the target memory cell, which is set at 0V. Therefore, both the equivalent source and the equivalent source terminal of the memory cell 401 are coupled to 0V and the hot carrier injection is suppressed. For memory cells 402 and 403, the SSL line voltage is set at the supply potential VD which is insufficient to turn on the SSL switch, blocking the current on the series and suppressing hot carrier injection. Using the adjustment bias in Figure 19, the pitch of the bit line buffers can be relaxed and a larger buffer can be used.

In Fig. 20, a shared word line structure is shown, allowing the use of the relaxed word line buffer spacing as an example. The reverse gate trains 480, 481, 482, 483 are shown in the figure, wherein the reverse gate trains 480, 482 are coupled to the bit line BL1, which is labeled as line 450 and extends in the direction of the train. The gate series 481, 483 are coupled to the bit line BL2, which is labeled as line 451 and extends in the direction of the string. The word lines intersecting the opposite gate series 480, 482 and the opposite gate trains 481, 483 are connected in the area of 425 shown in Fig. 21. The two common source lines CS1 and CS2 are 428 and 429, respectively, which are arranged for use in the four series. The AND gate series 480 and 481 are coupled to the common source line CS1 428, and the AND gate series 482 and 483 are coupled to the common source line CS2 429. Alternatively, the AND gate trains 482 and 483 and the common source line CS2 may be stacked on the opposite gate trains 480 and 481 and the common source line CS1 428. In this example, target memory cell 420 is coupled to word line WL7, which is coupled to memory cells 421, 422, and 423 in the unselected string. The switching voltage V-SW is applied to the word line WL8. The turn-on voltage is applied to the unselected word line and ground select line GSL. The serial selection line SSL is coupled to the supply potential VD. The first common source line CS1 is coupled to the positive 4V, and the second common source line CS2 is coupled to the 0V. This configuration causes the semiconductor body having the equivalent source region of the stylized target memory cell 420 to be interposed between the SSL switch and the target memory cell, and the semiconductor body having the equivalent drain region is interposed between the GSL switch and the target memory cell. between. The memory cells 421, 422, and 423 of the shared word line WL7 are not interfered because the suppression condition is induced. For the memory cells 421 and 423, it is coupled to the bit line BL-2, and the memory cell on the GSL side of the target memory cell is coupled to the first common source line CS1, which is set at 4V. The SSL line voltage is set at the supply potential VD is insufficient to turn on the SSL switch, blocking the current on the series and suppressing hot carrier injection, even if the common source lines of the two series are set at 4V and 0V, respectively. . For the memory cell 422, the common source line CS2 is set to 0V. Therefore, both the equivalent source and the equivalent source terminal of the memory cell 421 are coupled to 0V and the hot carrier injection is suppressed.

Figure 21 shows a schematic diagram of a vertically stacked three-dimensional type and gate flash memory, in which the reverse gate series in one layer and the reverse gate series in another layer share bit lines, and in each layer The anti-gate sequence and the other anti-gate series in the same layer share the common source line. With this configuration, the adjustment bias voltage in Fig. 20 can be applied to achieve the hot carrier stylization of the three-dimensional type and gate flash memory in Fig. 21. Figure 21 shows that the memory cells of the two planes have six charge trapping memory cells arranged in a reverse gate configuration, which is representatively represented as a cube comprising a plurality of planes and a plurality of word lines. The two planar memory cells are defined at the intersection of the wires 1160, 1161, 1162 as the word lines WLn-1, WLn, WLn+1, having the first stacked conductive stripes, the second stacked conductive stripes, and the third stack Conductive stripes.

The first plane of the memory cell includes a memory cell 1170, 1171, 1172 on the conductive stripe and a gate string, and a memory cell 1173, 1174, 1175 on the conductive stripe and a gate string. The second plane of the memory cell in this example corresponds to the bottom plane in the cube, and the memory cells (e.g., 1182, 1184) are arranged in the inverse gate train in a manner similar to the first plane.

As shown in the figure, the wire 1161 as the word line WLn includes a vertical extension between the stacks to couple the wire 1160 to the memory cells 1170, 1173 on the first plane and to the memory cells of all planes in the stack. Pick up.

In this arrangement, tandem select transistors 1196, 1197 are coupled between respective inverted gate trains and corresponding bit lines BL1 and BL2. Similarly, a similar series-selective transistor connection at the bottom plane of the cube is interposed between the respective inverted gate columns and corresponding bit lines BL1 and BL2 in this arrangement so that row decoding can be applied to the bit lines. Tandem select line 1106 is coupled to tandem select transistors 1196, 1197 and arranged in parallel with the word lines, as shown in FIG.

The common source select transistors 1190, 1191 are arranged on opposite sides of the reverse gate train and are used to couple the reverse gate trains in a selected layer to a common source reference line. This common source reference line is decoded by the planar decoder in this structure. This ground selection line GSL can be implemented in the same manner as the wires 1160, 1161, 1162. The tandem select transistor and common source select transistor can use the same dielectric stack with a gate oxide layer as the memory cell in some embodiments. In other embodiments, a typical gate oxide layer can be used. In addition, the channel length and width can be adjusted to meet the design needs to provide transistor switching. The description of the stylized operation in Figure 20 can also be used in this configuration, where the target memory cell is memory cell A (1171 in Fig. 21) and the voltage V-SW is applied between the target memory cell and the SSL line. Switching transistor 1196, and the stylized interference condition is considered for memory cell B (1174 in Fig. 21), representing the same plane and the same column of memory cells as the target memory cell (not programmed because of switching memory cell 1197) Not turned on), consider memory cell C (1182 in Figure 21), representing the same plane and the same line of memory cells as the target memory cell (not programmed because of bit line and common source line voltage) All grounded), consider memory cell D (1184 in Figure 21), representing the same row of memory cells but different columns and different planes of memory cells (not programmed because the switched memory cell 1197 on the SSL line is not Open).

According to the above arrangement, the serial selection and common source selection lines are decoded in a manner of a cube followed by a cube. This character line is decoded in a column by column. This common source line is decoded in a plane followed by a plane. This is the meta line is decoded in a row by row.

Figure 22 shows a simplified schematic of an integrated circuit that uses the hot carrier described herein to inject a programmed anti-gate flash memory. The integrated circuit 810 includes a memory array 812 that uses charge trapping or floating gate memory cells, which are formed, for example, on a semiconductor substrate. A word line (column) ground selection and serial selection decoder (including a suitable driver) 814 is coupled to and electrically coupled to the plurality of word lines 816, the string selection lines, and the ground selection line, and along the memory array The column direction of 812 is arranged. The bit line (row) decoder and driver 818 is in electrical communication with the plurality of bit lines 820 and arranged along the row direction of the memory array 812 to read data or write data from the memory cells of the array 812. Optionally, a common source line decoder 819 is provided to support a shared word line and bit line arrangement as shown in Figures 20 and 21. The address is provided by bus 822 to word line and tandem select decoder 814 and bit line decoder 818. The sense amplifier and data input structures in block 824, including current sources for read, program, and erase modes, are coupled to bit line decoder 818 via data bus 826. The data is supplied to the data input line 828 by the input/output ports on the integrated circuit 810, or is input to the data input structure in block 824 by other internal/external data sources of the integrated circuit 810. Other circuitry 830 is included within integrated circuitry 810, such as a general purpose processor or special purpose application circuitry, or a combination of modules to provide system single chip functionality supported by the array. The data is provided by the sense amplifier in block 824, via the data output line 832, to the integrated circuit 810, or to other data terminals internal/external to the integrated circuit 810.

The controller 834 used in this embodiment uses a bias adjustment state mechanism to control the application of bias voltage adjustment supply voltage and current source 836, such as reading, programming, erasing, erasing confirmation, and stylization. Verify that the voltage or current is applied to the word line or bit line and control the operation of the word line/source line using the access control flow. The controller also applies a switching sequence to induce the hot carrier stylization described herein. Controller 834 can be implemented using special function logic circuitry well known in the art. In an alternate embodiment, the controller 834 includes a general purpose processor that can be used in the same integrated circuit to execute a computer program to control the operation of the device. In yet another embodiment, the controller 834 is a combination of special purpose logic circuitry and a general purpose processor. The controller 834 can be configured to implement a method for inducing a hot carrier to be injected into one of the reverse and gate arrays of the gate array to select a memory cell, comprising: applying a switching voltage to the adjacent one of the selected cells A word line of the word line controls the conductance of the anti-gate sequence to induce an equivalent source in the first semiconductor body region of one side of the selected memory cell of the anti-gate sequence and induce The effect is extremely high in one of the second semiconductor body regions of the other side of the selected memory cell of the gate sequence; biasing the equivalent drain to a source extreme voltage; biasing the equivalent source to An extreme reference voltage is applied; and a staging potential greater than one hot carrier injected into the energy barrier is applied to the selected memory cell.

The embodiment of the anti-gate array in the anti-gate array includes a first switch between the first end of the anti-gate string and the bit line or the reference line, and a second switch In this case, a second end of the gate string is connected to the bit line or the reference line, wherein the biasing comprises: turning on the first switching switch of the selected memory cell including the reverse gate sequence, and The switch applies a drain voltage to the first semiconductor body region, and turns on a second switch including the selected memory cell of the gate sequence, and applies a source terminal voltage to the second semiconductor body region via the second switch.

Alternatively, the embodiment of the anti-gate array in the anti-gate array includes a first switch between the first end of the anti-gate string and the bit line or the reference line, and a second The switch is between the second end of the reverse gate sequence and the bit line or the reference line, wherein the bias comprises: turning on the first switch of the selected memory cell including the reverse gate sequence, and The first switching switch applies a source terminal voltage to the first semiconductor body region, and turns on a second switching switch including the selected memory cell of the reverse gate sequence, and applies a threshold voltage to the second semiconductor via the second switching switch Body area.

The controller 834 can be configured to perform a biasing operation to prevent stylized interference by turning off one of the first or second switches on the at least one unselected AND gate train. In addition, the controller 834 can also be configured to perform a biasing operation by turning on the first and second switching switches on at least one of the unselected reverse gate trains to prevent stylized interference.

The stylized methods described herein include application to a conventional anti-gate array using a common source architecture, and a modified anti-gate array with a virtual ground-type architecture. For each array type, stylization can be achieved by current flowing in the first and second directions. According to the first current direction, the equivalent drain is located in the upper portion of the reverse gate train, and the equivalent source is located in the lower portion. For the second current direction, the equivalent source is located in the upper portion of the reverse gate train, and the equivalent drain is located in the lower portion. In addition, this stylized method uses three different biasing methods to suppress stylized interference. For the first direction bias method, the equivalent source and the equivalent drain of the unselected series can be grounded at the same time to suppress hot carrier injection. For the second direction biasing method, the stylization suppression condition can be achieved by coupling the equivalent 汲 terminal to a drain potential and decoupling the series from the current to allow the capacitor to boost the equivalent source terminal to Stimulated by the voltage at which the bungee potential is close, stylized interference is also suppressed. Furthermore, for any stylization using a current in the second direction, the equivalent 汲 extremes and the equivalent source terminals can be coupled to the same or close potentials to suppress stylized interference.

A new anti-polar gate flash memory stylization method is provided that suppresses stylized interference due to lower operating voltages. A new stylization can use a lower operating voltage depending on the use of switching potentials to achieve hot carrier injection. As a result of this lower operating voltage, the driver circuitry on this integrated circuit can be implemented using only a single MOSFET process without the need for an additional high voltage MOSFET process.

In addition, the word line voltage of this stylized method is also required to be lower than that of the conventional anti-gate flash memory FN. Therefore, a very high voltage drive is also not required. In addition, the vertical electric field passing through the tunneling oxide layer in the gate flash memory is also less than that required for FN stylization. The reliability of the device is also improved because of the lower electric field required.

Furthermore, the lower programming and turn-on VPASS voltage required for conventional FN operation results in a lower voltage of the inter-layer dielectric layer of the word line, and thus reduces the dielectric layer of the word line due to the narrowing of the word line spacing. Crash problem.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

7, 8. . . Gate dielectric layer

9. . . Charge trapping structure

10. . . Semiconductor body

11, 19. . . contact

12~18. . . node

twenty one. . . Ground selection line GSL

22~27. . . Word line

28. . . Serial selection line SSL

30, 105. . . Common source line CS

31. . . Bit line

32. . . Unselected bit line

40, 100, 156, 300, 320, 400, 420. . . Target memory cell

41, 112, 113, 114, 155, 304, 324. . . Switch memory cells

42. . . First switch

43. . . Second switch

50, 51. . . Area in the semiconductor body

52. . . Deficient area

101, 102, 103, 104, 201~207, 380~383, 480~483. . . Reverse gate train

111. . . Ground selection transistor

112. . . Tandem selection transistor

301, 321. . . First switching transistor

302, 322. . . Second switching transistor

310, 314, 315, 330~335. . . Area in the semiconductor body

180, 312. . . Equivalent source region

181, 313. . . Equivalent bungee region

395, 396, 428, 429. . . Common source line CS

398, 399. . . Shared contact

401~403. . . Memory cell

421~423. . . Memory cell

450, 451‧‧‧ bit line

500~503‧‧‧Source/Bungee series

810‧‧‧ integrated circuit

812‧‧‧Anti-gate flash memory (eg 3D)

814‧‧‧Word line/serial selection and ground selection decoder and driver

816‧‧‧ character line

818‧‧‧ bit line decoder

819‧‧‧Common source line decoder

820‧‧‧ bit line

822, 826‧‧ ‧ busbar

824‧‧‧Sense Amplifier/Data Entry Structure

830‧‧‧Other circuits

834‧‧‧ (hot carrier injection stylization and FN erase) controller

836‧‧‧ bias adjustment supply voltage

828‧‧‧ data input line

832‧‧‧ data output line

1106‧‧‧Sequence selection line

1160, 1161, 1162‧‧‧ wires

1170, 1171, 1172, 1173, 1174, 1175, 1182, 1184‧‧‧ memory cells

1190, 1191‧‧‧ Common source selection transistor

1196, 1197‧‧‧ tandem selection transistor

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figures 1A and 1B show a schematic cross-sectional view of one of the conventional FN tunneling stylization techniques for selecting a reverse gate train and a non-selected reverse gate train.

Figure 2 shows a simplified cross-sectional view of a selected NAND string and its channel current vs. stylized bias relationship, showing the attempt to induce a hot load in a NAND string using conventional techniques. Subinjection stylized problems.

Figure 3 shows a simplified cross-sectional view of a selected NAND string and its channel current versus programmed bias voltage, showing the program described herein for inducing hot carrier injection in a gate series. Bias conditions.

Figure 4 shows a layout of a common source type reverse gate mode memory array using the programmed bias conditions described herein.

Figure 5 shows an example timing diagram of the bit line and word line bias voltages for the hot carrier injection stylization operation described herein.

Figure 6 shows the hot-charge sub-injection using the bias voltage described here and the stylized potential used in conventional FN tunneling, similar to the stylized potential used for hot carrier injection, the change in threshold voltage and the programmed time. relation chart.

Figure 7 is a graph showing the relationship between the applied switching voltage V-SW and the change of the threshold voltage, the switching memory cell having a -3 V threshold voltage, and the switching memory cell having a threshold voltage of 1 V to display the operating interval of the switching voltage V-SW. .

Figure 8 is a graphical representation of the memory cell threshold voltage distribution of a reverse gate array having a switching voltage V-SW distributed at the center and edge of the memory cell threshold voltage distribution, the display determining the switching voltage V-SW operating interval described herein. One program.

Figure 9 shows a timing diagram using a step-switching, verifying, and retrying step mechanism for a stylized operation to set the switching voltage.

Figure 10 shows a timing diagram using an incremental slope triangle pulse during a stylized operation to set the switching voltage.

Figure 11 shows a timing diagram using a decreasing gradient triangle pulse during a stylized operation to set the switching voltage.

Figure 12 shows a timing diagram of a switching voltage pulse with a slope leading and trailing edge.

Figure 13 shows a schematic diagram of a common source-type inverse gate memory array using multiple switched memory cell word lines in accordance with an alternate embodiment using the programmed bias conditions described herein.

Figure 14 shows a schematic diagram of a common source-type inverted gate memory array using a ground bit line and applying a VD common source line and a bias voltage VD to an unselected bit line in accordance with another alternative embodiment. Stylized bias conditions as described by the location.

Figure 15 shows a common source using a ground bit line and applying a VD common source line and a bias voltage VD to a common source line end of the unselected bit line and a voltage boosting power at the bit line end according to another alternative embodiment. A schematic diagram of a pole-type inverse gate memory array using the programmed bias conditions described herein.

Figure 16 shows a simplified layout of a dummy word line adjacent and one of the two ends of the gate string opposite the gate array.

Figure 17 shows a schematic diagram of a virtual grounded and gated memory array for stylized operation using the programmed bias conditions described herein and having a programmed current flowing from the bottom to the top.

Figure 18 shows a schematic diagram of a virtual grounded and gated memory array for stylized operation using the programmed bias conditions described herein and having a programmed current flowing from the top to the bottom.

Figure 19 shows a simplified schematic of a multi-planar common source and gate type memory array for stylized operation using the programmed bias conditions described herein with shared bit lines and common source decoding.

Figure 20 shows a simplified schematic of a multi-planar common source and gate type memory array for stylized operation using the programmed bias conditions described herein with shared word lines and common source decoding.

Figure 21 shows a simplified schematic of a three-dimensional common source and gate type memory array for stylized operation using the programmed bias conditions described herein with shared word lines and common source decoding.

Fig. 22 is a block diagram showing an integrated circuit using the memory cell and the bias circuit of the embodiment of the present invention.

11, 19. . . contact

twenty one. . . Ground selection line GSL

28. . . Serial selection line SSL

30. . . Common source line CS

31. . . Bit line

40. . . Target memory cell

41. . . Switch memory cells

42. . . First switch

43. . . Second switch

50, 51. . . Area in the semiconductor body

52. . . Deficient area

Claims (25)

A memory comprising: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, wherein the word lines in the plurality of word lines are coupled to memory cells in the corresponding plurality of memory cells; And the control circuit is coupled to the plurality of bit lines to be adapted to program a selected one of the plurality of memory cells corresponding to a selected word line by using the following steps: biasing in a stylized interval One of the first and second sides of the plurality of memory cells to an extreme voltage, and biasing the other of the first and second sides to a source terminal voltage; applying a 导 extreme turn-on voltage during the stylized interval And a word line between the selected word line and one of the first and second sides; applying a source-level turn-on voltage to the selected word line and the first portion in the stylized interval a word line between the other of the first and second sides; applying a stylized voltage to the selected word line repeatedly in the stylized section; and switching a voltage pulse to the selected word line And corresponding corresponding word lines adjacent to the selected memory cell The corresponding memory cell, in order to control the conductance when the stylized section, having a subsequent verification and retry steps, wherein the magnitude of the switching voltage pulse in each iteration is increased or decreased. The memory of claim 1, wherein the switching voltage is varied during the stylized interval, such that a hot carrier injection occurs in the selected memory cell to set the location during a portion of the stylized interval Select the memory cell to a stylized critical class. The memory of claim 1, wherein the applying a switching voltage comprises a period of time comprising a series of pulses of increasing or decreasing magnitude. The memory of claim 1, wherein the plurality of memory cells are arranged in a reverse train sequence. The memory of claim 1, further comprising a first switch between a reference line and the first side of the plurality of memory cells, and a second switch in the first bit Between the line and the second side of the plurality of memory cells, and wherein the control circuit turns on the first switch and turns on the second switch in the stylized section. The memory of claim 5, further comprising a second plurality of memory cells coupled to the plurality of word lines, a corresponding first switch on the reference line and the second plurality of memory cells Between a first side, and a corresponding second switch between a second bit line and a second side of the second plurality of memory cells, and wherein the control circuit is via the first bit Applying the 汲 extreme voltage to the second side of the second plurality of memory cells, applying the source terminal voltage to the first side of the second plurality of memory cells via the reference line, and via the second bit The line applies a voltage that is the same as or close to the source extreme voltage to the second side of the second plurality of memory cells to inhibit hot carrier injection. The memory of claim 5, further comprising a second plurality of memory cells coupled to the plurality of word lines, a corresponding first switch on the reference line and the second plurality of memory cells Between the first sides, and a corresponding second switch between a second bit line and the second side of the second plurality of memory cells, and wherein the control circuit is via the first bit Applying the source terminal voltage to the second side of the second plurality of memory cells, applying the threshold voltage to the second complex via the reference line The first side of the plurality of memory cells, and applying a voltage that is the same as or close to the threshold voltage to the second side of the second plurality of memory cells via the second bit line to suppress hot carrier injection. The memory of claim 5, further comprising a second plurality of memory cells coupled to the plurality of word lines and a second bit line, wherein the control circuit line applies a voltage to the first The two bit line is used to suppress hot carrier injection. The memory of claim 1, further comprising a first switch between a reference line and the first side of the plurality of memory cells, and a second switch on the one bit line Between the second sides of the plurality of memory cells. The memory of claim 9, further comprising a second plurality of memory cells coupled to the plurality of word lines and a second bit line, wherein the control circuit line operates in the stylized interval Biasing the second bit line such that the first semiconductor body region of the second plurality of memory cells on a first side of the selected word line and the second side of one of the selected word lines The second semiconductor body region of one of the second plurality of memory cells is biased to be close to a given voltage level, such as the source terminal voltage or the threshold voltage, to suppress hot carrier generation. The memory of claim 1, wherein the plurality of memory cells are arranged in a common source and a gate sequence in the gate flash memory array. The memory of claim 1, wherein the plurality of memory cells are arranged in a virtual ground and a reverse gate sequence in the gate flash memory array. A memory comprising: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, wherein the word lines in the plurality of word lines are coupled to the corresponding memory cells in the plurality of memory cells; and the control circuit is coupled to the plurality of bit lines to be adapted to utilize the following steps Staging a selected one of the plurality of memory cells corresponding to a selected word line: biasing one of the first and second sides of the plurality of memory cells to an extreme voltage during a stylized interval And biasing the other of the first and second sides to a source terminal voltage; applying a 汲 extreme turn-on voltage to the selected word line and the first and second sides during the stylized interval a word line between one; applying a source-level turn-on voltage to the word line between the selected word line and the other of the first and second sides in the stylized interval; Applying a stylized voltage to the selected word line during the stylized interval, and switching a voltage pulse to a word line adjacent to the selected word line and its corresponding selected memory cell and its corresponding memory cell To control the conductance in the stylized interval, followed by a verification and retry step, wherein the size of the switching voltage pulse is increased or decreased at each iteration; a first switching transistor is located between a reference line and the first end of the plurality of memory cells, The second switch transistor is located between a second bit of the first bit line of the plurality of memory cells; the additional dummy memory cell is not used for data storage, and the additional dummy memory cell is connected to the plurality of memory cells in series And an additional dummy word line in the semiconductor body, and placed between the plurality of memory cells and one of the first and second switching switches, wherein the control circuit line is programmed and the additional dummy The switching voltage pulse is applied to the additional dummy word line when the word line is adjacent to one of the target memory cells. The memory of claim 13, wherein the switching is performed Pressing includes applying one or more pulses having at least one of a fast rising or fast falling edge. A memory comprising: a plurality of bit lines and a plurality of common source lines; a plurality of memory cells; a plurality of word lines coupled to corresponding memory cells of the plurality of memory cells; wherein the plurality of memories The cells are arranged to be coupled to a first bit line of the plurality of bit lines and a first common source line of the plurality of common source lines; a plurality of additional counters And the plurality of word lines, the plurality of bit lines, and the plurality of common source lines are coupled to each other, and wherein a second of the plurality of additional anti-gate sequences a column coupled to the word line shared by the first AND gate sequence in the plurality of word line lines, and a second common source line in the first bit line and the plurality of common source lines And the control circuit is coupled to the plurality of word lines to be adapted to program a selected memory cell in the first AND gate sequence corresponding to a selected word line by using the following steps; When the interval is programmed, the first and the first and second gate series are biased via the first common source line One of the two sides to an extreme voltage, and biasing the other of the first and second sides to a source terminal voltage via the first bit line; applying a 汲 extreme turn-on voltage to the stylized interval to a word line between the selected word line and one of the first and second sides; applying a source extreme on voltage to the selected word line and the first and a word line between the other of the two sides; applying a stylized voltage to the selected word line repeatedly in the stylized section, and switching a voltage pulse to the selected word line and corresponding thereto Selecting the word line adjacent to the memory cell and its corresponding memory cell to control the stylized interval The conductance is followed by a verification and retry step in which the magnitude of the switching voltage pulse is increased or decreased at each iteration. The memory of claim 15, wherein the first and second anti-gate trains are arranged adjacent to each other along a column direction. The memory of claim 15, wherein the first and second reverse gate trains are arranged adjacent to each other in a row direction. The memory of claim 15, wherein the plurality of memory cells are arranged in a plurality of layers, and the first and second gates are arranged in a layer of the plurality of layers and the second The gate string is arranged in another layer of the plurality of layers, and is coupled to the first bit line and a second common source line of the plurality of common source lines, and the plurality of memory cells have the complex number A third reverse gate sequence in the additional reverse gate train and the other one of the plurality of layers are coupled to the other bit line and the first common source line. A memory comprising: a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, wherein the word lines in the plurality of word lines are coupled to memory cells in the corresponding plurality of memory cells; And the control circuit is coupled to the plurality of bit lines to be adapted to program a selected one of the plurality of memory cells corresponding to a selected word line by using the following steps: biasing in a stylized interval One of the first and second sides of the plurality of memory cells to an extreme voltage, and biasing the other of the first and second sides to a source terminal voltage; Applying a maximum on-voltage to the word line between the selected word line and one of the first and second sides during the stylized interval; applying a source-to-peak voltage to the stylized interval to a word line between the selected word line and the other of the first and second sides; applying a stylized voltage to the selected word line repeatedly in the stylized interval; and Switching a voltage pulse to a word line adjacent to the selected word line and its corresponding selected memory cell and its corresponding memory cell to control the conductance in the stylized interval, followed by a verification and retry step Wherein the size of the switching voltage pulse is increased or decreased at each iteration; and wherein the control circuit applies the switching voltage pulse to more than one word line during the stylized interval, the switching voltage pulse is programmed The interval ranges from a blocking current level to a supporting hot carrier injection level. A memory comprising: a reverse gate sequence comprising a plurality of memory cells arranged in series in a semiconductor body; a plurality of word lines, the word lines in the plurality of word lines and the corresponding plurality of memory cells The memory cell is coupled; and the control circuit is coupled to the plurality of bit lines to be adapted to program a selected one of the plurality of memory cells corresponding to a selected word line by using the following steps: Controlling the conductance of the anti-gate string by applying a switching voltage pulse to a word line adjacent to the selected word line to induce an equivalent source to a side of the selected memory cell of the anti-gate string And a second semiconductor body region in one of the first semiconductor body regions and the other side of the selected memory cell that induces an equivalent drain; biasing the first semiconductor body region to a source Extreme voltage Biasing the second semiconductor body region to an extreme voltage; and repeatedly applying a stylized potential greater than a hot carrier injection barrier to a selected memory cell in a stylized interval, followed by a verification And a retry step, wherein the size of the switching voltage pulse is increased or decreased at each iteration. A method for inducing a hot carrier to be injected into a reverse gate array of a gate array to select a memory cell, comprising: applying a switching voltage pulse to a word line adjacent to the selected word line Controlling the conductance of the anti-gate sequence to induce an equivalent source in one of the first semiconductor body regions of one side of the selected memory cell of the reverse gate sequence and inducing an equivalent drain to the reverse gate Aligning one of the other sides of the selected memory cell in the second semiconductor body region; biasing the equivalent drain to a source extreme voltage; biasing the equivalent source to an extreme reference voltage; and repeating Applying a stylized potential greater than one hot carrier to the energy barrier to the selected memory cell in a stylized interval, followed by a verification and retry step, wherein the switching voltage pulse is performed at each iteration The size is increased or decreased. The method of claim 21, wherein the anti-gate sequence in the anti-gate array comprises a first switch in a bit line or a reference line and a line of the anti-gate column Between one side, and a second switch between a bit line or a reference line and a second side of the reverse gate train, and wherein the biasing comprises: turning on the reverse gate series The first switch includes the selected memory cell and the source terminal voltage applied to the first side of the reverse gate train via the first switch; Turning on the second switch in the reverse gate train includes selecting the memory cell and applying the drain voltage to the second side of the reverse gate train via the second switch. The method of claim 21, wherein the anti-gate sequence in the anti-gate array comprises a first switch in a bit line or a reference line and a line of the anti-gate column Between one side, and a second switch between a bit line or a reference line and a second side of the reverse gate train, and wherein the biasing comprises: turning on the reverse gate series The first switch includes the selected memory cell and the first side of the reverse gate sequence applied to the first switch via the first switch; and the second switch in the reverse gate train And including the selected memory cell and applying the source terminal voltage to the second side of the reverse gate train via the second switch. The method of claim 23, wherein the biasing further comprises turning off one of the first and second switches in the at least one unselected reverse gate train. The method of claim 23, wherein the biasing further comprises turning on the first and second switching switches in the at least one unselected reverse gate train.