TW201241992A - Method of unifying device performance within die - Google Patents

Method of unifying device performance within die

Info

Publication number
TW201241992A
TW201241992A TW100132670A TW100132670A TW201241992A TW 201241992 A TW201241992 A TW 201241992A TW 100132670 A TW100132670 A TW 100132670A TW 100132670 A TW100132670 A TW 100132670A TW 201241992 A TW201241992 A TW 201241992A
Authority
TW
Taiwan
Prior art keywords
device performance
die
multiple functional
unifying device
circuit blocks
Prior art date
Application number
TW100132670A
Other languages
English (en)
Inventor
Yu-Ho Chiang
Ming-Tsung Chen
Wai-Yi Lien
Chih-Kai Hsu
Chun-Liang Hou
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of TW201241992A publication Critical patent/TW201241992A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW100132670A 2011-04-08 2011-09-09 Method of unifying device performance within die TW201241992A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US201161473176P 2011-04-08 2011-04-08

Publications (1)

Publication Number Publication Date
TW201241992A true TW201241992A (en) 2012-10-16

Family

ID=46965441

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100132670A TW201241992A (en) 2011-04-08 2011-09-09 Method of unifying device performance within die

Country Status (3)

Country Link
US (1) US20120256273A1 (zh)
CN (1) CN102738057A (zh)
TW (1) TW201241992A (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093995B2 (en) 2013-05-29 2015-07-28 Qualcomm Incorporated Length-of-diffusion protected circuit and method of design
US10622461B1 (en) 2019-01-15 2020-04-14 United Microelectronics Corp. Manufacturing method of semiconductor device having replacement gate in trench

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323113B1 (en) * 1999-12-10 2001-11-27 Philips Electronics North America Corporation Intelligent gate-level fill methods for reducing global pattern density effects
JP3506645B2 (ja) * 1999-12-13 2004-03-15 Necエレクトロニクス株式会社 半導体装置及びその製造方法
JP2007250705A (ja) * 2006-03-15 2007-09-27 Nec Electronics Corp 半導体集積回路装置及びダミーパターンの配置方法

Also Published As

Publication number Publication date
CN102738057A (zh) 2012-10-17
US20120256273A1 (en) 2012-10-11

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