201240540 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及印刷電路板製作領域，特別涉及一種電路板 之製作方法。 【先前技術】 [0002] 印刷電路板因具有裝配密度高等優點而得到了廣泛之應 用。關於電路板之應用請參見文獻Takahashi, A.201240540 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to the field of printed circuit board manufacturing, and more particularly to a method of fabricating a circuit board. [Prior Art] [0002] Printed circuit boards have been widely used due to their high assembly density. For the application of the circuit board, please refer to the literature Takahashi, A.
Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima， M. Res. Lab, High density multilayer printed circuit board for HITAC M-880 5 IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992， 15(4): 418-425。 [0003] 於印刷電路板之製作過程中，需要於印刷電路板之外表 面形成防焊層，所述防焊層將外層導電線路中不需要與 外界連通之部分覆蓋，而將需要與外界連通之部分導電 線路從覆蓋膜中之開口中露出，以便後續處理中從防焊 層露出之導電線路之表面形成金等較緻密之金屬，以更 好之與外界連通，並防止從防焊層露出之導電線路被氧 化。為了防止外層線路之佈局被容易辨別，需要對電路 板之布圖設計進行保護。先前技術中，通常採用感光之 黑色油墨作為防焊層。由於防焊層之厚度覆蓋外層導電 線路，因此，形成之防焊層之厚度較大，且黑色油墨之 吸光能力較強，於對印刷之防焊層進行曝光時，遠離防 焊層表面與電路板表面相接觸之黑色油墨通常因為沒有 吸收到足夠之光能而產生聚合，這樣，於顯影過程中， 100112870 表單編號A0101 第4頁/共27頁 1002021433-0 201240540 [0004]Ο[0005][0006] Ο [0007] 100112870 沒有聚合之黑色油墨與顯影液反應從電路板表面脫離， 從而形成側姓。於後續化金之過程中，金形成於由於防 焊層側钱形成之空隙中’從而造成“金長角，，現象。這 樣之多餘之金容易與被防焊層覆蓋之導電線路相互導通 ’從而造成電路板產品之短路。 【發明内容】 有鑑於此，提供一種能夠有效地保證於進行化金過程中 ，避免出現“金長角”現象之電路板之製作方法實屬必 要。 以下將以實施例說明一種電路板之製作方法。 一種電路板之製作方法，包括步驟：提供具有線路圖形 之基板，所述線路圖形包括多個焊墊。於所述線路圖形 之表面形成第-油墨層，所述第一油墨層之厚度為 0.2〇1丨1至1.0„^1。於所述第—油墨層上印刷黑色油墨以 於第-油墨層表面形成第二油墨層，所述第二油墨層之 厚度為0,2mil至l.〇mU，所逃第—油墨層和第三油墨層 構成油墨疊層結構，烘烤所述油墨疊層結構。通過曝光 及顯影去除部分油墨疊層結構，以於油墨疊層結構中形 成多個開口，每個焊整均從一個開〇露出。於從多個開 口露出之多個焊墊表面形成金層。 相較於先前技術，本技術讀所之提供之電路板之製作 方法，於進行防焊層之製作過程中，通過兩次印刷油墨 之方式形成’既可㈣過黑“墨覆蓋外層導電線路， 又可以保證形成找焊祕光充分，避免了防焊層韻 現象之產生，進而避免了後續化金產生之“金長角，，現 表單編號A0101 第5頁/共27頁 1002021433-0 201240540 象，提高了電路板之製作良率。 【實施方式】 [0008] 下面結合附圖及實施例對本技術方案提供之電路板之製 作方法作進一步說明。 [⑽9] 本技術方案第一實施例提供之電路板之製作方法包括如 下步驟： [0010] 第一步，請參閱圖1，提供一個基板100。 [0011] 基板100包括基材層120及形成於基材層120上之線路圖 形110。線路圖形110包括多根導電線路111及多個用於 與外界相互電連通之焊墊112。每個焊墊11 2均與一根或 者多根導電線路111相互電連通。基板100可以為單面電 路板，也可以為雙面電路板或者多層電路板，亦即，基 材層120可以為絕緣層，也可以包括交替排列之導電層和 絕緣層。本實施例中，基板100為單面電路板，所述基材 層120為絕緣層。 [0012] 可以理解，當基板100為雙面電路板時，則電路板之相對 之兩面均形成有線路圖形。當基板100為多層電路板時， 則電路板之相對兩面均形成有線路圖形。 [0013] 第二步，請參閱圖2，於基板100之表面形成覆蓋所述線 路圖形110之第一油墨層130，並對所述第一油墨層130 進行預烤。 [0014] 於基板100之表面形成第一油墨層130之前，還包括對基 板100進行防焊前處理。具體為，通過對基板100之表面 進行噴砂、酸洗、超聲波水洗、水洗及烘乾等處理，使 100112870 表單編號Α0ΗΠ 第6頁/共27頁 1002021433-0 201240540 得基板100之表面之髒汙被去除，線路圖形表面上之 氧化層被去除，並達到粗化線路圖形1 10表面之目的，從 而增強基板100之表面與第一油墨層130之間之結合能力 。第一油墨層130印刷於基材層120暴露出之表面和線路 圖形110之表面。 [0015] Ο 本實施例中，第一油墨層130採用印刷透明顯影型油墨形 成。第一油墨層130採用絲網印刷之方式形成。於進行印 刷時，採用之網版為90T網版。印刷之第一油墨層！ 3〇之 厚度約為0. 2mil至1. Omil。第一油墨層13〇之厚度應與 線路圖形110之厚度大致相等或者略大於線路圖形11〇之 厚度。於印刷透明油墨之後，還需要對透明油墨進行預 烤，使得印刷之透明油墨中之部分溶劑揮發，從而使得 第一油墨層130處於不黏狀態，以防止於後續操作中產生 黏貼現象。本實施例中，對第一油墨層13〇進行預烤之溫 度約為75攝氏度，持續之時間約為5分鐘。 [0016] Ο 第三步，請參閱圖3，於所述第一油墨層13〇上印刷黑色 油墨形成第二油墨層140，第一油墨層130和第二油墨層 HO共同構成油墨疊層結構16〇，並對油墨疊層結構16〇 進行烘烤。 [0017] 於本步驟中，採用絲網印刷之方式印刷黑色之感光油墨 形成第二油墨層140。於印刷形成第二油墨層14〇時，採 用之網版為61T網版。第二油墨層140之厚度應小於 1. lmil。線路圖形11〇完全被第一油墨層13〇和第二油墨 層140覆蓋，第一油墨層130和第二油墨層14〇共同構成 油墨疊層結構160。 100112870 表單編號A0101 第7頁/共27頁 1002021433-0 201240540 [0018] 於印刷形成第二油墨層140之後，需要對第一油墨層130 和第二油墨層140共同構成之油墨疊層結構160進行烘烤 ，使得油墨疊層結構160中之溶劑揮發，以便後續處理。 本實施例中，烘烤之溫度為80攝氏度，烘烤持續之時間 為5 0分鐘。 [0019] 第四步，請參閱圖4，對油墨疊層結構160進行曝光和顯 影，從而於油墨疊層結構1 60中形成多個開口 1 50，每個 開口 150均與一個焊墊11 2相對應，使得每個焊墊11 2均 從對應之開口 15 0露出。 [0020] 採用具有與基板100之焊墊11 2之分佈相同圖形之底片對 油墨疊層結構160進行曝光，使得覆蓋於每個焊墊112上 之油墨疊層結構160未被紫外光照射，其他部分之油墨疊 層結構160被紫外光照射而發生聚合反應。於進行顯影時 ，當顯影液與第二油墨層140和第一油墨層130油墨疊層 結構160相接觸時，未發生聚合反應之部分油墨疊層結構 160被顯影液溶解，即於每個焊墊112上之油墨疊層結構 160形成開口 150。本實施例中，曝光時採用之紫外光之 能量為900mJ/cm2。於進行顯影時，設定顯影之線速度 為 3m/miη。 [0021] 於進行顯影之後，為了使得剩餘之油墨疊層結構160中之 溶劑進一步揮發，發生之聚合反應更加完全，還可以進 一步對油墨疊層結構160進行後烤處理。 [0022] 第五步，請參閱圖5，對基板100進行化金，於從油墨疊 層結構160之開口 150露出之焊墊112形成金層170。 100112870 表單編號Α0101 第8頁/共27頁 1002021433-0 201240540 [0023] [0024] Ο 將基板ιοο置於化金槽内，於從每個開口 15〇露出之焊墊 112上形成金層17〇。形成之金層17〇之厚度通過調整化 金時間之長短進行調解。 於本實施例中，油墨疊層結構16〇由第一油墨層13〇和第 二油墨層140共同組成。第—油墨層13〇採用透明油墨形 成，第二油墨層140採用黑色油墨形成，由於第二油墨層 140之厚度相比於只採用一次印刷黑色油墨之厚度小，於 進行曝光時，部分光線可以透過第二油墨層⑽照射至第 一油墨層130。而第一油墨層13〇採用透明油墨製成具 有良好之透光性。從而可以保證第一油墨層13〇和第二油 墨層14G均得到充分曝光，於進行顯料，油墨叠層結構 160不會產生側蝕。這樣，於化金時，金層17〇只形成於 焊墊112之表面，從而能夠有效地防止“金長角，，現象之 發生。 [0025] 〇 [0026] 本技術方案第二實施例也提供一種電路板之製作方去 所述電路板之製作方法包括如下步驟：.Ooki, N. Nagai, A. Akahoshi, H. Mukoh, A. Wajima, M. Res. Lab, High density multilayer printed circuit board for HITAC M-880 5 IEEE Trans, on Components, Packaging, and Manufacturing Technology, 1992, 15(4): 418-425. [0003] In the manufacturing process of the printed circuit board, it is required to form a solder resist layer on the outer surface of the printed circuit board, and the solder resist layer covers a portion of the outer conductive line that does not need to communicate with the outside, and needs to communicate with the outside. A part of the conductive line is exposed from the opening in the cover film, so that a dense metal such as gold is formed on the surface of the conductive line exposed from the solder resist layer in the subsequent process to better communicate with the outside and prevent exposure from the solder resist layer. The conductive lines are oxidized. In order to prevent the layout of the outer layer from being easily distinguished, the layout design of the board needs to be protected. In the prior art, a photosensitive black ink is usually used as a solder resist layer. Since the thickness of the solder resist layer covers the outer conductive line, the thickness of the solder resist layer formed is large, and the light absorption capability of the black ink is strong, and the surface of the solder resist layer and the circuit are away when the printed solder resist layer is exposed. The black ink that is in contact with the surface of the board usually generates polymerization because it does not absorb enough light energy. Thus, during development, 100112870 Form No. A0101 Page 4 / Total 27 Page 1002021433-0 201240540 [0004]Ο[0005][ 0006] [0007] 100112870 A black ink that does not polymerize reacts with a developer to detach from the surface of the board, thereby forming a side surname. In the process of subsequent gold refining, gold is formed in the void formed by the side of the solder mask layer, thereby causing a "golden long angle," phenomenon. Such excess gold is easily conductive to the conductive line covered by the solder resist layer. Therefore, a short circuit of the circuit board product is caused. [Invention] In view of the above, it is necessary to provide a circuit board capable of effectively ensuring the phenomenon of "golden long angle" during the process of performing gold plating. The embodiment describes a method for fabricating a circuit board, comprising the steps of: providing a substrate having a circuit pattern, the circuit pattern comprising a plurality of pads; forming a first ink layer on a surface of the circuit pattern, The thickness of the first ink layer is from 0.2〇1丨1 to 1.0°^1. Printing a black ink on the first ink layer to form a second ink layer on the surface of the first ink layer, the second ink layer having a thickness of 0, 2 mil to 1. 〇mU, the escaped ink layer and the first The three ink layers constitute an ink laminate structure, and the ink laminate structure is baked. A portion of the ink laminate structure is removed by exposure and development to form a plurality of openings in the ink laminate structure, each of which is exposed from an opening. A gold layer is formed on the surface of the plurality of pads exposed from the plurality of openings. Compared with the prior art, the circuit board provided by the technical reading method is formed by the two printing inks in the process of manufacturing the solder resist layer, and the outer conductive track is covered by the ink. It can also ensure that the formation of the welding secret light is sufficient, avoiding the occurrence of the anti-welding layer rhyme phenomenon, and thus avoiding the "golden long angle" generated by the subsequent gold, now Form No. A0101 Page 5 / 27 pages 1002021433-0 201240540 , improve the production yield of the board. [Embodiment] The method for manufacturing a circuit board provided by the present technical solution will be further described below with reference to the accompanying drawings and embodiments. [(10)9] The manufacturing method of the circuit board provided by the first embodiment of the present technical solution includes the following steps: [0010] In the first step, referring to FIG. 1, a substrate 100 is provided. [0011] The substrate 100 includes a substrate layer 120 and a wiring pattern 110 formed on the substrate layer 120. The line pattern 110 includes a plurality of conductive lines 111 and a plurality of pads 112 for electrically interconnecting the outside. Each pad 11 2 is in electrical communication with one or more of the conductive traces 111. The substrate 100 may be a single-sided circuit board, or a double-sided circuit board or a multi-layer circuit board, that is, the substrate layer 120 may be an insulating layer, or may include alternating conductive layers and insulating layers. In this embodiment, the substrate 100 is a single-sided circuit board, and the substrate layer 120 is an insulating layer. [0012] It can be understood that when the substrate 100 is a double-sided circuit board, circuit patterns are formed on opposite sides of the circuit board. When the substrate 100 is a multilayer circuit board, circuit patterns are formed on opposite sides of the circuit board. [0013] In the second step, referring to FIG. 2, a first ink layer 130 covering the line pattern 110 is formed on the surface of the substrate 100, and the first ink layer 130 is pre-baked. [0014] Before the first ink layer 130 is formed on the surface of the substrate 100, the substrate 100 is further subjected to pre-solder treatment. Specifically, the surface of the substrate 100 is subjected to sand blasting, pickling, ultrasonic washing, water washing, and drying, so that the surface of the substrate 100 is smeared by the surface number of the substrate 100 870 0 ΗΠ 6 page / page 27 1002021433-0 201240540 After removal, the oxide layer on the surface of the wiring pattern is removed and the purpose of roughening the surface of the wiring pattern 1 10 is achieved, thereby enhancing the bonding ability between the surface of the substrate 100 and the first ink layer 130. The first ink layer 130 is printed on the exposed surface of the substrate layer 120 and the surface of the wiring pattern 110. [0015] In the present embodiment, the first ink layer 130 is formed using a printing transparent developing type ink. The first ink layer 130 is formed by screen printing. For printing, the screen version is 90T screen. The first ink layer printed! Omil. The thickness is about 0. 2mil to 1. Omil. The thickness of the first ink layer 13 should be substantially equal to or slightly larger than the thickness of the line pattern 110. After printing the transparent ink, it is also necessary to pre-bake the transparent ink so that a part of the solvent in the printed transparent ink is volatilized, so that the first ink layer 130 is in a non-stick state to prevent sticking in subsequent operations. In this embodiment, the temperature of the first ink layer 13 is pre-baked at about 75 degrees Celsius for a period of about 5 minutes. [0016] Ο In the third step, referring to FIG. 3, a black ink is printed on the first ink layer 13A to form a second ink layer 140, and the first ink layer 130 and the second ink layer HO together constitute an ink lamination structure. 16〇, and the ink laminate structure 16〇 was baked. [0017] In this step, the black photosensitive ink is printed by screen printing to form the second ink layer 140. When the second ink layer 14 is formed by printing, the screen used is a 61T screen. The thickness of the second ink layer 140 should be less than 1. lmil. The line pattern 11 is completely covered by the first ink layer 13A and the second ink layer 140, and the first ink layer 130 and the second ink layer 14A together constitute the ink layer structure 160. 100112870 Form No. A0101 Page 7 of 27 1002021433-0 201240540 [0018] After the second ink layer 140 is formed by printing, it is necessary to perform the ink lamination structure 160 which is formed by the first ink layer 130 and the second ink layer 140. Baking causes the solvent in the ink laminate structure 160 to volatilize for subsequent processing. In this embodiment, the baking temperature is 80 degrees Celsius, and the baking duration is 50 minutes. [0019] In a fourth step, referring to FIG. 4, the ink lamination structure 160 is exposed and developed to form a plurality of openings 150 in the ink lamination structure 160, each opening 150 and a pad 11 2 Correspondingly, each of the pads 11 2 is exposed from the corresponding opening 150. [0020] The ink laminate structure 160 is exposed using a negative film having the same pattern as the distribution of the pads 11 2 of the substrate 100 such that the ink laminate structure 160 overlying each of the pads 112 is not exposed to ultraviolet light, and the others A portion of the ink laminate structure 160 is irradiated with ultraviolet light to cause polymerization. When developing, when the developer comes into contact with the second ink layer 140 and the first ink layer 130 ink laminate structure 160, a portion of the ink laminate structure 160 that has not undergone polymerization is dissolved by the developer, that is, for each soldering. The ink laminate structure 160 on the pad 112 forms an opening 150. In this embodiment, the energy of ultraviolet light used for exposure is 900 mJ/cm2. At the time of development, the developing linear velocity was set to 3 m/miη. [0021] After the development, in order to further volatilize the solvent in the remaining ink laminate structure 160, the polymerization reaction occurs more completely, and the ink laminate structure 160 may be further post-baked. [0022] In a fifth step, referring to FIG. 5, the substrate 100 is subjected to gold, and a gold layer 170 is formed on the pads 112 exposed from the openings 150 of the ink laminate structure 160. 100112870 Form No. 1010101 Page 8 of 27 1002021433-0 201240540 [0024] Ο Place the substrate ιοο in the gold bath to form a gold layer 17 on the pad 112 exposed from each opening 15〇 . The thickness of the formed gold layer 17〇 is adjusted by adjusting the length of the gold time. In the present embodiment, the ink laminate structure 16 is composed of a first ink layer 13A and a second ink layer 140. The first ink layer 13 is formed by using a transparent ink, and the second ink layer 140 is formed by using a black ink. Since the thickness of the second ink layer 140 is smaller than the thickness of the black ink which is printed only once, part of the light may be exposed during exposure. The first ink layer 130 is irradiated through the second ink layer (10). The first ink layer 13 is made of a transparent ink and has good light transmittance. Thereby, it is ensured that both the first ink layer 13A and the second ink layer 14G are sufficiently exposed, and the ink laminate structure 160 does not cause side etching. Thus, in the case of gold, the gold layer 17 is formed only on the surface of the pad 112, so that the "golden long angle" phenomenon can be effectively prevented. [0025] [0026] The second embodiment of the present technical solution is also A method for manufacturing a circuit board to the circuit board includes the following steps:
[0027] 第一步，請參閱圖6，提供一個已經形成有線路圖形 之基板2 0 0。 基板200包括基材層220及形成於基材層22〇上之線 形210。線路圊形210包括多根導電線路211及多個硌圖 與外界相互電連通之焊墊212 ^每個焊墊212岣與—用於 者多根導電線路211相互電連通。基板2〇〇可以為單根或 路板，也可以為雙面電路板或者多層電路板，亦即面電 材層220可以為絕緣層，也可以包括交替排列之 基 等電層承 21〇 100112870 表單編號Α0101 第9頁/共27頁 201240540 絕緣層。本實施例中，基板200為單面電路板，所述基材 層220為絕緣層。基板200基板200基板200第二步，請參 閱圖7及圖8，於基板200之表面形成覆蓋所述線路圖形 210之第一油墨層230，並對所述第一油墨層230進行預 烤及曝光。 [0028] 可以理解，於基板200之表面形成第一油墨層230之前， 還包括對基板200進行防焊前處理。具體為，通過對基板 200之表面進行喷砂、酸洗、超聲波水洗、水洗及烘乾等 處理，使得基板200之表面之髒汙被去除，線路圖形210 表面上之氧化層被去除，並達到粗化線路圖形210表面之 目之，從而增強基板200之表面與第一油墨層230之間之 結合能力。 [0029] 第一油墨層230印刷於基材層220暴露出之表面和線路圖 形210之表面。本實施例中，第一油墨層230採用印刷黑 色顯影型油墨形成。第一油墨層230採用網印之方式形成 。於進行印刷時，採用之網版為120T網版。印刷之第一 油墨層230之厚度約為0. 2mil至1. Omil。於印刷黑色油 墨之後，還需要對透明油墨進行預烤，使得印刷之透明 油墨中之部分溶劑揮發，從而使得第一油墨層230處於不 黏狀態，以防止於後續操作中產生黏贴現象。本實施例 中，對第一油墨層230進行預烤之溫度約為75攝氏度，持 續之時間約為5分鐘。 [0030] 於進行預烤之後，需要對第一油墨層230進行曝光。採用 具有與基板200之焊墊212之分佈相同之圖形之底片對第 一油墨層230進行曝光，使得覆蓋於每個焊墊212上之第 100112870 表單編號A0101 第10頁/共27頁 1002021433-0 201240540 [0031] [0032] Ο [0033] [0034] [0035] 一油墨層230未被紫外光照射，其他部分之第一油墨層 230被紫外光照射而發生聚合反應。本實施例中，於對第 一油墨層230進行曝光時採用之曝光能量為900mJ/cm2。 第三步，請參閱圖9，於所述第一油墨層230上印刷黑色 油墨形成第二油墨層240，第一油墨層230和第二油墨層 240共同構成油墨疊層結構260，並對油墨疊層結構260 進行烘烤。 於本步驟中，採用絲網印刷之方式印刷黑色之感光油墨 形成第二油墨層240。於印刷形成第二油墨層240時，採 用之網版為61T網版。第二油墨層140之厚度也應小於 1.〇111丨1，優選為0.2111丨1至1.〇111丨1。線路圖形210完全被 油墨疊層結構260覆蓋。 於印刷形成第二油墨層240之後，需要對油墨疊層結構 260進行烘烤，使得油墨疊層結構260中之溶劑揮發，以 便後續處理。本實施例中，烘烤之溫度為80攝氏度，烘 烤持續之時間為50分鐘。 第四步，請參閱圖10，採用相同之底片對油墨疊層結構 260進行曝光及顯影，從而於油墨疊層結構260内形成多 個開口 25 0，每個開口 250均與一個焊墊212相對應，使 得每個焊墊212均從對應之開口 250露出。 採用相同之底片對油墨疊層結構260進行曝光，使得覆蓋 於每個焊墊212上之油墨疊層結構2 6 0未被紫外光照射， 其他部分之油墨疊層結構2 6 0被紫外光照射而發生聚合反 應。於進行顯影時，當顯影液與油墨疊層結構260相接觸 100112870 表單編號A0101 第11頁/共27頁 1002021433-0 201240540 時，未發生聚合反應之部分油墨疊層結構260被顯影液溶 解，即於每個焊墊21 2上之油墨疊層結構260形成開口 2 50。本實施例中，曝光時採用之紫外光之能量為 1 000mJ/cm2。於進行顯影時，設定顯影之線速度為 4. 1 m/miη。 [0036] 於進行顯影之後，為了使得剩餘之油墨疊層結構260中之 溶劑進一步揮發，發生之聚合反應更加完全，還可以進 一步對油墨疊層結構260進行後烤處理。 [0037] 第五步，請參閱圖11，對基板100進行化金，於從油墨疊 層結構260之開口 21 50露出之焊墊212形成金層270。 [0038] 將基板200置於化金槽内，於從每個開口 250露出之焊墊 212上形成金層270。形成之金層270之厚度通過調整化 金時間之長短進行調解。 [0039] 於本實施例中，油墨疊層結構260由第一油墨層230和第 二油墨層240共同組成。第一油墨層230採用黑色油墨形 成，第二油墨層240也採用黑色油墨形成，由於第一油墨 層230和第二油墨層240之厚度均相比於只採用黑色油墨 一次印刷厚度小，並且第一油墨層230和第二油墨層240 分別進行曝光，從而可以保證第一油墨層130和第二油墨 層140均得到充分曝光，於進行顯影時，油墨疊層結構 260不會產生侧蝕。這樣，於化金時，金層270只形成於 焊墊212之表面，從而能夠有效地防止“金長角”現象之 發生。 [0040] 上述兩個實施例提供之方法製作之電路板之防焊層，能 100112870 表單編號Α0101 第12頁/共27頁 1002021433-0 201240540 夠順利通過本技術領域中之信賴性測試，如硬度、附著 性、財焊錫性、耐溶解性、耐酸性、对驗性、对化金、 冷熱沖積極恒溫恒濕測試，均無脫落、剝離、軟化或者 起泡等現象產生。 [0041] 惟，以上所述者僅為本發明之較佳實施方式，自不能以 此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士 援依本發明之精神所作之等效修飾或變化，皆應涵蓋於 以下申請專利範圍内。 0 【圖式簡單說明】 [0042] 圖1係本技術方案第一實施例提供之電路板之剖視圖。 [0043] 圖2係圖1之線路圖形表面形成第一油墨層後之剖視圖。 [0044] 圖3係圖2之第一油墨層上形成第二油墨層後之剖視圖。 [0045] 圖4係圖3之第一油墨層和第二油墨層被曝光及顯影後之 剖視圖。 [0046] 圖5係圖4中之焊墊上形成金層後之剖視圖。 〇 [0047] 圖6係本技術方案第二實施例提供之電路板之剖視圖。 [0048] 圖7係圖6之線路圖形表面形成第一油墨層後之剖視圖。 [0049] 圖8係圖7中之第一油墨層被曝光後之剖視圖。 [0050] 圖9係圖8之第一油墨層上形成第二油墨層後之剖視圖。 [0051] 圖1 0係圖9之第一油墨層和第二油墨層被曝光及顯影後之 剖視圖。 [0052] 圖11係圖10中之焊墊上形成金層後之剖視圖。 100112870 表單編號A0101 第13頁/共27頁 1002021433-0 201240540 【主要元件符號說明】 [0053] 基板：100，200 [0054] 線路圖形：110，210 [0055] 導電線路：111，211 [0056] 焊墊：11 2，21 2 [0057] 基材層：120，220 [0058] 第一油墨層：130，230 [0059] 第二油墨層：140，240 [0060] 開口 ： 1 5 0，2 5 0 [0061] 油墨疊層結構：160，260 [0062] 金層：170，2 70 1002021433-0 100112870 表單編號A0101 第14頁/共27頁[0027] In the first step, referring to FIG. 6, a substrate 200 having a line pattern formed thereon is provided. The substrate 200 includes a substrate layer 220 and a line 210 formed on the substrate layer 22A. The circuit profile 210 includes a plurality of conductive traces 211 and a plurality of pads 212 electrically connected to the outside of each other. Each of the pads 212 and the plurality of conductive traces 211 are in electrical communication with each other. The substrate 2 〇〇 may be a single or a circuit board, or may be a double-sided circuit board or a multi-layer circuit board, that is, the surface electrical material layer 220 may be an insulating layer, or may include an alternately arranged base isoelectric layer 21 〇 100112870 form No. 101 0101 Page 9 / Total 27 pages 201240540 Insulation. In this embodiment, the substrate 200 is a single-sided circuit board, and the substrate layer 220 is an insulating layer. Substrate 200 substrate 200 substrate 200, in the second step, referring to FIG. 7 and FIG. 8, a first ink layer 230 covering the circuit pattern 210 is formed on the surface of the substrate 200, and the first ink layer 230 is pre-baked and exposure. [0028] It can be understood that before the first ink layer 230 is formed on the surface of the substrate 200, the pre-soldering treatment of the substrate 200 is further included. Specifically, by performing sandblasting, pickling, ultrasonic washing, water washing, and drying on the surface of the substrate 200, the surface of the substrate 200 is removed, and the oxide layer on the surface of the circuit pattern 210 is removed. The surface of the line pattern 210 is roughened to enhance the bonding ability between the surface of the substrate 200 and the first ink layer 230. [0029] The first ink layer 230 is printed on the exposed surface of the substrate layer 220 and the surface of the line pattern 210. In the present embodiment, the first ink layer 230 is formed by printing a black developing type ink. The first ink layer 230 is formed by screen printing. When printing, the screen version used is 120T screen. 2mil至1. Omil。 The thickness of the first ink layer 230 is about 0. 2mil to 1. Omil. After printing the black ink, it is also necessary to pre-bake the transparent ink to volatilize part of the solvent in the printed transparent ink, so that the first ink layer 230 is in a non-stick state to prevent sticking in subsequent operations. In this embodiment, the temperature at which the first ink layer 230 is pre-baked is about 75 degrees Celsius, and the duration is about 5 minutes. [0030] After the pre-baking, the first ink layer 230 needs to be exposed. The first ink layer 230 is exposed using a negative film having the same pattern as that of the bonding pads 212 of the substrate 200 so that the first ink layer 230 is overlaid on each of the pads 212. Form No. A0101 Page 10/27 pages 1002021433-0 [0035] [0035] [0035] An ink layer 230 is not irradiated with ultraviolet light, and other portions of the first ink layer 230 are irradiated with ultraviolet light to cause polymerization. In this embodiment, the exposure energy used for exposing the first ink layer 230 is 900 mJ/cm2. In a third step, referring to FIG. 9, a black ink is printed on the first ink layer 230 to form a second ink layer 240. The first ink layer 230 and the second ink layer 240 together constitute an ink laminate structure 260, and the ink The laminate structure 260 is baked. In this step, a black photosensitive ink is printed by screen printing to form a second ink layer 240. When the second ink layer 240 is formed by printing, the screen used is a 61T screen. The thickness of the second ink layer 140 should also be less than 1.〇111丨1, preferably 0.2111丨1 to 1.〇111丨1. The line pattern 210 is completely covered by the ink laminate structure 260. After printing to form the second ink layer 240, the ink laminate structure 260 needs to be baked such that the solvent in the ink laminate structure 260 is volatilized for subsequent processing. In this embodiment, the baking temperature was 80 ° C and the baking duration was 50 minutes. In the fourth step, referring to FIG. 10, the ink laminate structure 260 is exposed and developed by using the same negative film, thereby forming a plurality of openings 25 0 in the ink laminate structure 260, each opening 250 being associated with a solder pad 212. Correspondingly, each of the pads 212 is exposed from the corresponding opening 250. The ink laminate structure 260 is exposed by the same negative film, so that the ink layer structure 206 covered on each of the pads 212 is not irradiated with ultraviolet light, and the other portions of the ink layer structure 206 are irradiated with ultraviolet light. The polymerization reaction takes place. When developing, when the developer comes into contact with the ink laminate structure 260, 100112870, Form No. A0101, page 11 / page 27, 1002021433-0 201240540, part of the ink lamination structure 260 that has not undergone polymerization is dissolved by the developer, that is, The ink laminate structure 260 on each of the pads 21 2 forms an opening 2 50. In this embodiment, the energy of the ultraviolet light used for the exposure is 1 000 mJ/cm 2 . When developing, the developing linear velocity was set to 4. 1 m/miη. [0036] After the development, in order to further volatilize the solvent in the remaining ink laminate structure 260, the polymerization reaction takes place more completely, and the ink laminate structure 260 can be further post-baked. [0037] In a fifth step, referring to FIG. 11, the substrate 100 is subjected to gold, and a gold layer 270 is formed on the pads 212 exposed from the openings 21 50 of the ink laminate structure 260. [0038] The substrate 200 is placed in a gold bath to form a gold layer 270 on the pads 212 exposed from each of the openings 250. The thickness of the formed gold layer 270 is adjusted by adjusting the length of the gold time. In the present embodiment, the ink laminate structure 260 is composed of a first ink layer 230 and a second ink layer 240. The first ink layer 230 is formed by black ink, and the second ink layer 240 is also formed by black ink, since the thicknesses of the first ink layer 230 and the second ink layer 240 are both smaller than that of the black ink alone, and the thickness is small. An ink layer 230 and a second ink layer 240 are respectively exposed, so that both the first ink layer 130 and the second ink layer 140 are sufficiently exposed, and the ink laminate structure 260 does not cause side etching during development. Thus, in the case of gold, the gold layer 270 is formed only on the surface of the pad 212, so that the "golden long angle" phenomenon can be effectively prevented. [0040] The solder resist layer of the circuit board produced by the method provided by the above two embodiments can be successfully passed through the reliability test in the technical field, such as hardness. 100112870 Form No. 1010101 Page 12/27 Page 1002021433-0 201240540 Adhesion, chemical soldering, solvent resistance, acid resistance, resistance, chemical, cold and hot positive constant temperature and humidity test, no shedding, peeling, softening or foaming. [0041] However, the above description is only a preferred embodiment of the present invention, and the scope of the patent application of the present invention cannot be limited thereby. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0042] FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present technical solution. 2 is a cross-sectional view showing the surface of the line pattern of FIG. 1 after forming a first ink layer. 3 is a cross-sectional view showing a second ink layer formed on the first ink layer of FIG. 2. 4 is a cross-sectional view showing the first ink layer and the second ink layer of FIG. 3 after exposure and development. [0046] FIG. 5 is a cross-sectional view showing a gold layer formed on the pad of FIG. 4. 6 is a cross-sectional view of a circuit board provided by a second embodiment of the present technical solution. 7 is a cross-sectional view showing the surface of the line pattern of FIG. 6 after forming a first ink layer. 8 is a cross-sectional view of the first ink layer of FIG. 7 after being exposed. 9 is a cross-sectional view showing the second ink layer formed on the first ink layer of FIG. 8. 10 is a cross-sectional view showing the first ink layer and the second ink layer of FIG. 9 after exposure and development. 11 is a cross-sectional view showing a gold layer formed on the pad of FIG. 10. 100112870 Form No. A0101 Page 13 of 27 1002021433-0 201240540 [Description of main component symbols] [0053] Substrate: 100, 200 [0054] Line pattern: 110, 210 [0055] Conductive line: 111, 211 [0056] Pad: 11 2, 21 2 [0057] Substrate layer: 120, 220 [0058] First ink layer: 130, 230 [0059] Second ink layer: 140, 240 [0060] Opening: 1 5 0, 2 5 0 [0061] Ink Laminated Structure: 160, 260 [0062] Gold Layer: 170, 2 70 1002021433-0 100112870 Form No. A0101 Page 14 of 27