201240017 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種微機 是有關於一種微機電裝置的製、1、、、°構的製造方法，且特別 方法。 【先前技術】 隨著半導體製程技術的進步， (MEMS)的蓬勃發展。在傳統微機 _，，已推動微機電系統 動元件製程與微機電製裎是械系統的製造方法中，主 件電路與微機電裝置後，再將二，仃，在分別完成主動元 成微機電系統。上述的製造方法又稱整=在同—基材上而完 7 成又稱為「System In Package」 (SIP)。 另一種習知的製造方式是在形成主動元件電路中諸如 金屬氧化物半導體元件（MOS)及雙載子接面電晶體(BJT)等 半導體元件後，再進行形成微機電結構的製程，然後再進 行主動元件電路的金屬化製程而完成晶圓層級(wafer level) 的微機電系統。隨後將晶圓切割成晶片（Die)，最後再進行 晶片的封裝。 在微機電裝置的製造過程中，通常採用諸如反應性離 子蝕刻（RIE)之電漿蝕刻方式來形成微機電裝置中可移動 的構件或部分。但是，以上述方式所形成的微機電裝置的 輪廓(profile)並不理想。因此，目前亟需一種新的製造方 法，期能改善上述問題。 【發明内容】 201240017 根據本發明之一態樣，係提供一種在半導體電路層之 一區域形成一貫穿空間之方法，其包含以下步驟。形成一 半導體電路層，此半導體電路層包含一特徵結構填充於此 區域；其中特徵結構包含一介電結構以及一金屬結構，介 電結構貫穿半導體電路層，金屬結構貫穿半導體電路層並 環繞介電結構。然後，移除特徵結構以形成貫穿空間；其 中移除特徵結構包含依序以乾式蝕刻移除介電結構以及濕 式蝕刻移除金屬結構。 在一實施方式中，上述金屬結構為一多層結構。在一 實施例中，多層結構包含一第一金屬層以及一第二金屬 廣，第二金屬層位於第一金屬層上方，且第二金屬層之面 積小於第一金屬層之面積。在另一實施例中，多層結構中 的每一層具有大致相同之一寬度。 在一另實施方式，介電結構包含一底部以及一頂部， 且底部之寬度小於頂部之寬度。 根據本發明之另一態樣，係提供一種製造微機電裝置 之方法，其包括以下步驟。形成一電路層於一基材之上表 面，電路層包含一特徵結構以及一微結構；其中特徵結構 圍繞微結構之周邊的一部分並貫穿電路層。此特徵結構包 含一介電結構以及一金屬結構，介電結構貫穿電路層，金 屬結構貫穿電路層並環繞介電結構。接著、移除特徵結構 以露出基材，移除特徵結構包含依序以乾式蝕刻移除介電 結構以及濕式蝕刻移除金屬結構。然後、使用非等向性蝕 刻移除露出基材之一部分。隨後，由基材之下表面一側移 除基材的部分，以釋放微結構。 201240017 在一實施方式中’形成電路層之步驟包括形成一互補 式金屬氧化物半導體元件。 根據本發明之又一態樣，係提供一種微機電裝置，其 係由上述製造微機電裝置之方法所製成，且微機電裝置中 的微結構的側壁與基材表面之間的夾角為約85度至約95 度。 【實施方式】 請參照第1圖，其為本發明一實施方式之微機電裝置 的上視示意圖。微機電裝置可應用在例如加速度偵測器 (accelerometer)或陀螺儀（gyroscope)等之微機電慣性感測 裝置。第1圖係繪示一微機電加速度偵測器，但本發明以 下所揭露的製造方法可適用在其他的微機電裝置中，並不 限於微機電加速度偵測器。 如第1圖所示，微機電加速度偵測器1〇〇主要包括可 動的微結構110、半導體電路120以及複數個連接墊13〇 以及電路層140。半導體電路120大致配置在可動的微結 構110之外圍。連接墊130通常可配置在半導體電路12〇 的外圍。 微結構110容置在電路層140的貫穿空間142中，且 微結構包括中心部112、至少一彈性支撐件114以及至少一 凸出物116。彈性支撐件114連接中心部Π2與電路層140, 且使中心部112呈現可移動狀態。凸出物116由中心部112 向外延伸，且與電路層140延伸出的另一凸出物144形成 一電容。 201240017 半導體電路120電性連接凸出物144及凸出物116， 以量測兩凸出物116、144之間的電容值，並將所量測的電 容訊號轉變為一電壓或電流訊號。半導體電路12〇可包括 一互補式金屬氧化物半導體裝置。半導體電路120可經由 連接墊130而電性連接一外部電路（未繪示）。 在操作時’當微機電加速度偵測器10〇受到一加速度 時，凸出物144與凸出物116之間的距離改變，使其間二 電容值發生變化。半導體電路12〇量測上述電容值或電容 值的變化量，而得以估算微機電加速度偵測器1〇〇所受到 的加速度。 上述微機電加速度偵測器100僅為示範性例子，以易 於瞭解本發明下文揭露的製造方法，本發明並不限於製造 微機電加速度偵測器。此外，上述各元件以及各元件之間 的連接關係及相對關係，僅為說明之目的，不應被解釋為 本發明的限制。以下所揭露的各實施例，在有^的情料 可相互組合或取代，也可在一實施例中附加其他的實施 例，而無須進一步的記載或說明。 、第2A圖為本發明一實施方式之製造微機電裝置之方 法200的流程圖。第3圖至8圖係繪示本發明一實施方式 之製造方法中各製程階段的剖面示意圖，其大致為第i圖 中線段3-3’的剖面示意圖。 進行步驟201，形成電路層32〇於基材31〇的上表面， 如第3A圖所示。基材31〇可例如為砍晶圓或其他適合用 以製造半導體元件的基材。電路層32()包含微結構別以 及特徵結構340，特徵結構34〇圍繞微結構33Q之周邊的 201240017 一部分，並貫穿電路層320。在後續的步驟中，特徵結構 340將會被移除而形成第1圖繪示的貫穿空間142的一部 分。換言之，特徵結構340填充的貫穿空間142的區域中。 特徵結構340包含介電結構342以及金屬結構344。 介電結構342貫穿電路層320，並接觸下方的基材310。介 電結構342可包含例如為氧化矽或氮化矽，或由氧化矽及 氮化矽堆疊而構成。金屬結構344也同樣貫穿電路層320， 並且環繞介電結構342。換言之，金屬結構344形成在特 徵結構340的外緣。更詳細而言，金屬結構344可包含344a 及344b兩部分。金屬結構的344a部分實體連接電路層320 與介電結構342;金屬結構的344b部分實體連接微結構330 與介電結構342。 在一實施方式中，形成電路層320的步驟包括形成一 互補式金屬氧化物半導體元件(CMOS) 322。在CMOS元件 的標準製程中，可包括4道的金屬化製程以及2道的多晶 矽化製程(2P4M製程），亦可包括5道的金屬化製程以及1 道的多晶矽化製程(5M1P製程）。因此，在一實施例中，當 形成CMOS元件322時，可藉由適當的光罩設計，同時形 成特徵結構340。詳言之，當形成CMOS元件322的金屬 層時，可同時形成特徵結構340中部分的金屬結構344， 當形成CMOS元件322中的介電層時，可同時形成特徵結 構340的介電結構342。因此，可以在形成CMOS元件322 時，逐步形成特徵結構340。以上僅以CMOS為例說明， 並非用以限制本發明，其他例如BiCMOS結構或類似結構 亦可適用於本發明。 201240017 在一實施方式中，當填充金屬於CMOS元件的連接孔 (via)時，可同時形成金屬結構344的一部分。例如，填充 在CMOS元件通孔的金屬為鎢，CMOS元件322的金屬層 為鋁。因此，形成由鋁及鎢所堆疊而成的金屬結構344。 亦即，金屬結構344為多層結構，且至少由兩種金屬材料 所構成。 在一實施例中，上述多層結構包含第一金屬層345以 及第二金屬層346，第二金屬層346位於第一金屬層345 上方，且第二金屬層346的面積小於第一金屬層345的面 積。在一特定實施例中，金屬結構344具有一階梯狀的剖 面輪廓，如第3A圖所示。在此實施例中，介電結構342 可具有上寬下窄的剖面。詳言之，介電結構342包含一底 部342B以及一頂部342T，底部342B的寬度小於頂部342T 的寬度。在另一實施例中，金屬結構344同樣為多層結構， 但是金屬結構344中的每一金屬層具有大致相同的寬度， 如第3B圖所示。在此實施例中，介電結構342的底部與頂 部大致具有相同的寬度。 在一實施方式中，電路層320更包含一連接墊324以 及保護層326。保護層覆蓋在連接墊324上，用以在後續 的蝕刻製程中保護連接墊324。連接墊324電性連接CMOS 元件322，並用以連接至一外部電路。可以在適當的步驟 中，移除連接墊324上方的保護層326,而露出連接墊324。201240017 VI. Description of the Invention: [Technical Field] The present invention relates to a microcomputer, a manufacturing method for a system, a 1, and a structure of a microelectromechanical device, and a special method. [Prior Art] With the advancement of semiconductor process technology, (MEMS) has flourished. In the traditional microcomputer _, has promoted the micro-electromechanical system dynamic component process and micro-electromechanical system is the manufacturing method of the mechanical system, after the main component circuit and the micro-electromechanical device, then the second, 仃, in the completion of the active element into the micro-electromechanical system. The above manufacturing method is also referred to as "system in package" (SIP). Another conventional manufacturing method is to form a microelectromechanical structure after forming semiconductor elements such as a metal oxide semiconductor device (MOS) and a bipolar junction transistor (BJT) in an active device circuit, and then A wafer level MEMS is performed by performing a metallization process of the active device circuit. The wafer is then diced into wafers and finally wafers are packaged. In the fabrication of microelectromechanical devices, a plasma etch such as reactive ion etching (RIE) is typically employed to form movable components or portions of the microelectromechanical device. However, the profile of the microelectromechanical device formed in the above manner is not ideal. Therefore, there is a need for a new manufacturing method that will improve the above problems. SUMMARY OF THE INVENTION 201240017 In accordance with an aspect of the present invention, a method of forming a through space in a region of a semiconductor circuit layer is provided, which includes the following steps. Forming a semiconductor circuit layer, the semiconductor circuit layer including a feature structure filled in the region; wherein the feature structure comprises a dielectric structure and a metal structure, the dielectric structure penetrates the semiconductor circuit layer, the metal structure penetrates the semiconductor circuit layer and surrounds the dielectric structure. The feature structure is then removed to form a through space; wherein the removing the feature comprises sequentially removing the dielectric structure by dry etching and removing the metal structure by wet etching. In one embodiment, the metal structure is a multilayer structure. In one embodiment, the multilayer structure includes a first metal layer and a second metal layer, the second metal layer being over the first metal layer, and the area of the second metal layer being smaller than the area of the first metal layer. In another embodiment, each of the layers of the multilayer structure has a width that is substantially the same. In another embodiment, the dielectric structure includes a bottom and a top, and the width of the bottom is less than the width of the top. In accordance with another aspect of the present invention, a method of fabricating a microelectromechanical device is provided that includes the following steps. A circuit layer is formed on a surface of a substrate, the circuit layer comprising a feature structure and a microstructure; wherein the feature structure surrounds a portion of the periphery of the microstructure and extends through the circuit layer. The feature structure includes a dielectric structure and a metal structure. The dielectric structure extends through the circuit layer, and the metal structure extends through the circuit layer and surrounds the dielectric structure. Next, the features are removed to expose the substrate, and the removal features include sequential removal of the dielectric structure by dry etching and wet etching to remove the metal structure. Then, an anisotropic etch is used to remove a portion of the exposed substrate. Subsequently, a portion of the substrate is removed from the side of the lower surface of the substrate to release the microstructure. 201240017 In an embodiment, the step of forming a circuit layer includes forming a complementary metal oxide semiconductor device. According to still another aspect of the present invention, there is provided a microelectromechanical device produced by the above method of fabricating a microelectromechanical device, and an angle between a sidewall of the microstructure in the microelectromechanical device and a surface of the substrate is about 85 degrees to about 95 degrees. [Embodiment] Please refer to Fig. 1, which is a top view of a microelectromechanical device according to an embodiment of the present invention. The microelectromechanical device can be applied to a microelectromechanical inertial sensing device such as an accelerometer or a gyroscope. Fig. 1 is a diagram showing a microelectromechanical acceleration detector, but the manufacturing method disclosed in the present invention can be applied to other microelectromechanical devices, and is not limited to a microelectromechanical acceleration detector. As shown in Fig. 1, the microelectromechanical acceleration detector 1A mainly includes a movable microstructure 110, a semiconductor circuit 120, and a plurality of connection pads 13A and a circuit layer 140. The semiconductor circuit 120 is disposed substantially at the periphery of the movable microstructures 110. The connection pads 130 are typically configurable on the periphery of the semiconductor circuit 12A. The microstructures 110 are received in the through spaces 142 of the circuit layer 140, and the microstructures include a central portion 112, at least one resilient support member 114, and at least one protrusion 116. The elastic support member 114 connects the central portion Π2 and the circuit layer 140, and causes the central portion 112 to assume a movable state. The projection 116 extends outwardly from the central portion 112 and forms a capacitance with another projection 144 extending from the circuit layer 140. The semiconductor circuit 120 is electrically connected to the protrusion 144 and the protrusion 116 to measure the capacitance between the two protrusions 116 and 144 and convert the measured capacitance signal into a voltage or current signal. The semiconductor circuit 12A may include a complementary metal oxide semiconductor device. The semiconductor circuit 120 can be electrically connected to an external circuit (not shown) via the connection pad 130. In operation, when the MEMS acceleration detector 10 is subjected to an acceleration, the distance between the projection 144 and the projection 116 changes, causing the value of the capacitance between the two to change. The semiconductor circuit 12 measures the amount of change in the capacitance value or the capacitance value to estimate the acceleration received by the MEMS acceleration detector 1〇〇. The above-described microelectromechanical acceleration detector 100 is merely an illustrative example to facilitate understanding of the manufacturing method disclosed herein below, and the present invention is not limited to the fabrication of a microelectromechanical acceleration detector. In addition, the above-described components and the connection relationships and relative relationships between the components are for illustrative purposes only and should not be construed as limiting the invention. The embodiments disclosed in the following may be combined with or substituted for each other, and other embodiments may be added to an embodiment without further description or explanation. 2A is a flow chart of a method 200 of fabricating a microelectromechanical device according to an embodiment of the present invention. 3 to 8 are schematic cross-sectional views showing respective process stages in the manufacturing method of an embodiment of the present invention, which is roughly a schematic cross-sectional view of the line segment 3-3' in the i-th figure. Step 201 is performed to form the circuit layer 32 on the upper surface of the substrate 31A as shown in FIG. 3A. The substrate 31 can be, for example, a chopped wafer or other substrate suitable for use in the fabrication of semiconductor components. The circuit layer 32() includes a microstructure and a feature structure 340 that surrounds a portion of 201240017 surrounding the microstructure 33Q and extends through the circuit layer 320. In a subsequent step, feature structure 340 will be removed to form a portion of through space 142 depicted in FIG. In other words, the feature structure 340 fills the area of the through space 142. Feature structure 340 includes a dielectric structure 342 and a metal structure 344. Dielectric structure 342 extends through circuit layer 320 and contacts underlying substrate 310. The dielectric structure 342 may comprise, for example, tantalum oxide or tantalum nitride, or may be composed of a stack of tantalum oxide and tantalum nitride. Metal structure 344 also extends through circuit layer 320 and surrounds dielectric structure 342. In other words, the metal structure 344 is formed on the outer edge of the feature structure 340. In more detail, the metal structure 344 can include two portions 344a and 344b. The portion 344a of the metal structure physically connects the circuit layer 320 with the dielectric structure 342; the portion 344b of the metal structure physically connects the microstructure 330 with the dielectric structure 342. In one embodiment, the step of forming circuit layer 320 includes forming a complementary metal oxide semiconductor device (CMOS) 322. In the standard process of CMOS components, it can include 4 metallization processes and 2 polysilicon processes (2P4M process), and can also include 5 metallization processes and 1 channel polysilicon process (5M1P process). Thus, in one embodiment, when CMOS component 322 is formed, feature 340 can be formed simultaneously by a suitable reticle design. In detail, when the metal layer of the CMOS device 322 is formed, a portion of the metal structure 344 of the feature structure 340 can be simultaneously formed. When the dielectric layer in the CMOS device 322 is formed, the dielectric structure 342 of the feature structure 340 can be simultaneously formed. . Therefore, the feature structure 340 can be formed step by step when the CMOS element 322 is formed. The above description is made by taking only CMOS as an example, and is not intended to limit the present invention, and other, for example, a BiCMOS structure or the like may be applied to the present invention. 201240017 In one embodiment, a portion of the metal structure 344 can be formed simultaneously when filling the metal with a via of the CMOS device. For example, the metal filled in the via hole of the CMOS element is tungsten, and the metal layer of the CMOS element 322 is aluminum. Therefore, a metal structure 344 in which aluminum and tungsten are stacked is formed. That is, the metal structure 344 is a multilayer structure and is composed of at least two metal materials. In an embodiment, the multi-layer structure includes a first metal layer 345 and a second metal layer 346. The second metal layer 346 is located above the first metal layer 345, and the area of the second metal layer 346 is smaller than that of the first metal layer 345. area. In a particular embodiment, the metal structure 344 has a stepped profile profile as shown in Figure 3A. In this embodiment, the dielectric structure 342 can have an upper width and a lower profile. In particular, the dielectric structure 342 includes a bottom portion 342B and a top portion 342T having a width that is less than the width of the top portion 342T. In another embodiment, metal structure 344 is also a multilayer structure, but each metal layer in metal structure 344 has substantially the same width, as shown in FIG. 3B. In this embodiment, the bottom of the dielectric structure 342 has substantially the same width as the top. In an embodiment, the circuit layer 320 further includes a connection pad 324 and a protective layer 326. A protective layer overlies the bond pads 324 for protecting the bond pads 324 during subsequent etching processes. The connection pad 324 is electrically connected to the CMOS component 322 and is connected to an external circuit. The protective layer 326 over the connection pads 324 can be removed in a suitable step to expose the connection pads 324.
在步驟202中，移除特徵結構340，以露出基材310。 在一實施方式中，可先形成一光阻層350於電路層320及 微結構330上，如第4A及4B圖所示（第4A圖對應第3A 201240017 圖的實施例，第4B圖對應第3B圖的實施例），光阻層350 具有開口 352，以露出特徵結構340。 移除特徵結構340的步驟包含兩階段。第一階段先以 乾式蝕刻移除介電結構342，第二階段再以濕式蝕刻移除 金屬結構344，以下將詳述之。 進行第一階段的乾式蝕刻，以移除介電結構342，如 第5A及5B圖所示（第5A圖對應第4A圖的實施例，第5B 圖對應第4B圖的實施例）。在一實施例中，可使用諸如反 應性離子触刻（reactive ion etching，RIE)之乾式非等向性触 刻來移除介電結構342。反應性離子蝕刻僅會蝕刻諸如氧 化矽及氮化矽之介電材料，不會蝕刻金屬材料。在進行反 應性離子蝕刻的過程中，由於微結構330的側壁以及電路 層320的側壁被金屬結構344覆蓋，所以反應性離子蝕刻 不會傷害或蝕刻微結構330及電路層320的側壁，而使微 結構330及電路層320的側壁得以保持原本的輪廓外觀。 隨後進行第二階段的濕式蝕刻，以移除金屬結構344， 如第6圖所示。移除金屬結構344後，微結構330可與電 路層320形成一間隙d，並使間隙d中的基材310暴露出 來。換言之，可以形成一個貫穿電路層320的空間。在一 實施例中，間隙d之寬度為約1微米至約5微米，例如可 為2微米或3微米。在濕式蝕刻中，所採用的蝕刻劑對於 金屬材料與氧化物材料（或氮化物）具有高的蝕刻選擇比， 例如高於15 : 1或高於20 : 1或高於30 : 1或更高。因此， 在移除金屬結構344時，幾乎不會損害微結構330及電路 層320原本的側壁輪廓外觀。在一實施例中，姓刻劑中包 201240017 氫’硫酸與過氧化氫的重量比可例如為約 在金屬㈣劑也可刺於本發明中。 將光阻居^ 當進行濕式㈣時，㈣劑可同時一併 能。 除。換s之，蝕刻劑兼具光阻剝離液的功 =發明上述之方法，可使微結構330的側壁與基 之間的夹角'為約85度至約95度。此外， '犧微結構330側壁及電路層32〇 可哺升微機電裝置雜能以及品質穩定性。 中的技術Γ是直接使用RIE製程來形成電路層320 、、以1^方法所製造的微結構的側壁與基材上表 角通常為約70度至约80度，且所侧 電裝置性能不穩定。因此，根據本發明之=方 式了有效改善習知技術的缺點。 〜除=之外’中華民國專利申請號99111316與本發明為 样其全部内容在此併為本發明的參考資料。就 ^實施1、樣而言，本發明可視為上述專利巾請案的改 <具體而吕，當金屬結構344包含鎢，且間隙d的寬度 :於約2…寺’本發明所揭露的製造方法優於上述專二 :請案所揭露方法。詳言之，當間_的寬度大於約2㈣ 時’在形成金屬結構344中的鶴層時，很難形成平整的鎢 層表面，而造成後續製程的困擾。從此觀點而言，太 發明一實施方式，金屬結構344中的最大寬度w(如第5A 圖所示）小於約3/zm。 201240017 在步驟203中，使用非等向性蝕刻移除露出的基材310 的一部分，而形成凹陷312,如第7圖所示。在一實施方 式中，電路層上方形成有氧化矽層326，且微結構330上 方亦形成有一氧化矽層。因此，在非等向性蝕刻過程中， 氧化矽層可作為遮罩而保護下方的電路層及微結構。在一 實施例中，非等向性蝕刻包括一深式反應離子蝕刻（Deep Reactive Ion Etching，DRIE)步驟。在又一實施例中，凹陷 部314可形成如第1圖繪示之貫穿空間142的一部分。 在步驟204中，由基材310之下表面一側移除基材310 的部分，以釋放微結構330,如第8圖所示。在本文中，「釋 放微結構」係指使微機電裝置產生具有可相對移動的構造 或部件。舉例而言，可先進行研磨基材310下表面的步驟， 使基材310的厚度減少。隨後再以DRIE對基材310的下 表面進行蝕刻，以在基材310的下表面形成凹槽314。凹 槽314與凹陷312連通，因此讓微結構330發生可相對電 路層320移動的功能。 根據本發明之另一態樣，係提供一種微機電裝置。此 微機電裝置係以如上所述之任一方法所製成。在微機電裝 置中，微結構330的側壁與基材310上表面之間的夾角Θ 為約85度至約95度。 根據本發明之又一態樣，係揭露一種在半導體電路層 之一區域形成一貫穿空間的方法。第2B圖為本發明一實施 方式之在半導體電路層形成貫穿空間的方法290的流程 圖。 在步驟291中，形成一半導體電路層320，半導體電In step 202, feature 340 is removed to expose substrate 310. In one embodiment, a photoresist layer 350 may be formed on the circuit layer 320 and the microstructure 330 as shown in FIGS. 4A and 4B (the fourth embodiment corresponds to the third embodiment of FIG. 3A 201240017, and the fourth embodiment corresponds to the fourth embodiment. In the embodiment of FIG. 3B, the photoresist layer 350 has an opening 352 to expose the features 340. The step of removing feature structure 340 involves two phases. The first stage first removes the dielectric structure 342 by dry etching, and the second stage removes the metal structure 344 by wet etching, as will be described in more detail below. The first stage of dry etching is performed to remove the dielectric structure 342 as shown in Figs. 5A and 5B (Fig. 5A corresponds to the embodiment of Fig. 4A, and Fig. 5B corresponds to the embodiment of Fig. 4B). In one embodiment, the dielectric structure 342 can be removed using a dry anisotropic lithography such as reactive ion etching (RIE). Reactive ion etching only etches dielectric materials such as hafnium oxide and tantalum nitride without etching the metal material. During the reactive ion etching process, since the sidewalls of the microstructure 330 and the sidewalls of the circuit layer 320 are covered by the metal structure 344, the reactive ion etching does not damage or etch the sidewalls of the microstructure 330 and the circuit layer 320. The sidewalls of the microstructures 330 and circuit layers 320 maintain their original contoured appearance. A second stage of wet etching is then performed to remove the metal structure 344, as shown in FIG. After the metal structure 344 is removed, the microstructures 330 can form a gap d with the circuit layer 320 and expose the substrate 310 in the gap d. In other words, a space penetrating the circuit layer 320 can be formed. In one embodiment, the gap d has a width of from about 1 micron to about 5 microns, such as 2 microns or 3 microns. In wet etching, the etchant used has a high etching selectivity for the metal material and the oxide material (or nitride), for example, above 15:1 or above 20:1 or above 30:1 or more. high. Therefore, when the metal structure 344 is removed, the original sidewall profile appearance of the microstructures 330 and the circuit layer 320 is hardly impaired. In one embodiment, the weight ratio of 201240017 hydrogen 'sulfuric acid to hydrogen peroxide in the surname can be, for example, about the metal (tetra) agent can also be stabbed in the present invention. When the photoresist is applied to the wet type (four), the (four) agent can be used together at the same time. except. In other words, the etchant combines the work of the photoresist stripper. In the above method, the angle between the sidewalls of the microstructure 330 and the substrate can be 'about 85 degrees to about 95 degrees. In addition, the 'small structure 330 sidewall and circuit layer 32〇 can support the MEMS physics and quality stability. The technique is to directly form the circuit layer 320 by using the RIE process, and the sidewall of the microstructure manufactured by the method is usually about 70 degrees to about 80 degrees, and the performance of the side electrical device is not stable. Therefore, the disadvantages of the prior art are effectively improved in accordance with the present invention. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; In the case of the first embodiment, the present invention can be regarded as a modification of the above-mentioned patent towel claim. Specifically, when the metal structure 344 contains tungsten, and the width of the gap d is about 2...the temple is disclosed. The manufacturing method is better than the above-mentioned special two: the method disclosed in the case. In particular, when the width of the interlayer _ is greater than about 2 (four), it is difficult to form a flat surface of the tungsten layer in forming the layer of the metal layer 344, which causes troubles in subsequent processes. From this point of view, in one embodiment, the maximum width w (as shown in Figure 5A) in the metal structure 344 is less than about 3/zm. 201240017 In step 203, a portion of the exposed substrate 310 is removed using an anisotropic etch to form a recess 312, as shown in FIG. In one embodiment, a hafnium oxide layer 326 is formed over the circuit layer, and a hafnium oxide layer is also formed over the microstructures 330. Therefore, during the anisotropic etching process, the yttrium oxide layer acts as a mask to protect the underlying circuit layers and microstructures. In one embodiment, the anisotropic etch includes a Deep Reactive Ion Etching (DRIE) step. In yet another embodiment, the recess 314 can form a portion of the through space 142 as depicted in FIG. In step 204, portions of the substrate 310 are removed from the lower surface side of the substrate 310 to release the microstructures 330, as shown in FIG. As used herein, "release microstructure" means that the microelectromechanical device produces a structure or component that is relatively movable. For example, the step of grinding the lower surface of the substrate 310 may be performed to reduce the thickness of the substrate 310. The lower surface of the substrate 310 is then etched by DRIE to form a recess 314 on the lower surface of the substrate 310. The recess 314 is in communication with the recess 312, thus allowing the microstructure 330 to function as a function of movement relative to the circuit layer 320. According to another aspect of the present invention, a microelectromechanical device is provided. This MEMS device is made in any of the methods described above. In the microelectromechanical device, the angle Θ between the sidewall of the microstructure 330 and the upper surface of the substrate 310 is from about 85 degrees to about 95 degrees. According to still another aspect of the present invention, a method of forming a through space in a region of a semiconductor circuit layer is disclosed. Fig. 2B is a flow chart showing a method 290 of forming a through space in a semiconductor circuit layer according to an embodiment of the present invention. In step 291, a semiconductor circuit layer 320 is formed, and the semiconductor is electrically
S 12 201240017 路層320包含一特徵結構340填充於區域A中，如第3A 圖所示。特徵結構340包含介電結構342以及金屬結構 344。介電結構342貫穿半導體電路層320。金屬結構344 貫穿半導體電路層320並環繞介電結構342。 在步驟292中，移除特徵結構340,以形成貫穿空間B， 如第6圖所示。移除特徵結構340包含依序以乾式蝕刻移 除介電結構342以及濕式蝕刻移除金屬結構344。 在步驟291及步驟292所述的特徵結構340、介電結 構342以及金屬結構344的特徵、形成方法及移除方法可 與上述第2A圖之方法200所述的相同，於此不再重述。 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係繪示本發明一實施方式之微機電裝置的上視 圖。 第2A圖係繪示本發明一實施方式之製造微機電裝置 之方法的流程圖。 第2B圖係繪示本發明一實施方式之繪示本發明一實 施方式之在半導體電路層形成貫穿空間之方法的流程圖。 第3A至8圖係繪示本發明一實施方式之製造方法中 各製程階段的剖面示意圖 13 201240017 【主要元件符號說明】 100微機電加速度偵測器 110微結構 112中心部 114彈性支撐件 116凸出物 120半導體電路 130連接墊 140基材 142貫穿空間 144凸出物 200方法 2(H、202、203、204 步驟 290方法 291、292 步驟 310基材 312凹陷 314凹槽 320電路層 322互補式金屬氧化物半導體元件 330微結構 340特徵結構 342介電結構 14 201240017 342T介電結構頂部 342B介電結構底部 344金屬結構 345第一金屬層 346第二金屬層 350光阻層 352 開口 d間隙 W寬度 Θ角度 A區域 B慣穿空間S 12 201240017 The road layer 320 includes a feature structure 340 that is filled in the area A as shown in FIG. 3A. Feature structure 340 includes a dielectric structure 342 and a metal structure 344. The dielectric structure 342 extends through the semiconductor circuit layer 320. Metal structure 344 extends through semiconductor circuit layer 320 and surrounds dielectric structure 342. In step 292, feature structure 340 is removed to form through space B, as shown in FIG. The removal feature 340 includes sequentially removing the dielectric structure 342 and the wet etch removal metal structure 344 by dry etching. The features, formation methods, and removal methods of the feature structure 340, the dielectric structure 342, and the metal structure 344 described in steps 291 and 292 may be the same as those described in the method 200 of FIG. 2A above, and are not repeated herein. . Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top plan view showing a microelectromechanical device according to an embodiment of the present invention. Fig. 2A is a flow chart showing a method of manufacturing a microelectromechanical device according to an embodiment of the present invention. 2B is a flow chart showing a method of forming a through-space in a semiconductor circuit layer according to an embodiment of the present invention. 3A to 8 are schematic cross-sectional views showing various process stages in a manufacturing method according to an embodiment of the present invention. 201240017 [Major component symbol description] 100 microelectromechanical acceleration detector 110 microstructure 112 center portion 114 elastic support member 116 convex Output 120 semiconductor circuit 130 connection pad 140 substrate 142 through space 144 protrusion 200 method 2 (H, 202, 203, 204 step 290 method 291, 292 step 310 substrate 312 recess 314 groove 320 circuit layer 322 complementary Metal oxide semiconductor device 330 microstructure 340 feature structure 342 dielectric structure 14 201240017 342T dielectric structure top 342B dielectric structure bottom 344 metal structure 345 first metal layer 346 second metal layer 350 photoresist layer 352 opening d gap W width Θ angle A area B customary space