201236059 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具有金屬閘極(metal gate)之半導體元件之 製作方法。 【先前技術】 在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金 氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的 閘極材料選擇。然而，隨著M0S電晶體尺寸持續地微縮，傳統多 晶矽閘極因硼穿透(boronpenetration)效應導致元件效能降低，及其 難以避免的空乏效應(d印letion effect)等問題，使得等效的閘極介電 層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困 境。因此，半導體業界更嘗以新的閘極材料，例如利用功函數~〇也 function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數 (High-K)閘極介電層的控制電極。 而在互補式金氧半導體(complementary metai_〇x^je semiconductor，CMOS)元件中，雙功函數金屬閘極一需與NM〇s元 件搭配，一則需與PMOS元件搭配，因此使得相關元件的整合技術 以及製程控制更形複雜，且各材料的厚度與成分控制要求亦更形嚴 苛。雙功函數金屬閘極之製作方法係可概分為前閘極(gatefirst)製程 及後閘極(gate last)製程兩大類。其中前閘極製程會在形成金屬閘極 201236059 後$進仃雜/祕峨接面活細火以及形成金屬雜物等高熱 預程’因此使得材料的選擇與調㈣對較多的挑戰。為避免上 述向熱預算環境並獲得較寬的材料選擇，業界係提出以後閘極製程 取代前閘極製程之方法。 而習知後閘極製程中，係先形成一犧牲閘極(sacrifice_或取 代閘極㈣acementgate)，並在完成一般腦電晶體的製作後，將 參犧牲/取代閘極移除而形成一間極凹槽_t職h)，再依電性需求於 閘極凹槽内填入不同的金屬。但由於後閘極製程相當複雜，需要多 道製程才能完成，因此目前廠商皆致力精簡化形成金屬閘極之製程。 【發明内容】 本發明於是提供-種製作具有金顧極之铸體元件 可得到較佳的製程可靠度。 / 艮據-較佳實施例，本發明提供一種製作具有金 ::方法。此方法首先提供一基底。基底包含一第一= 第一導電型電晶體。第一導電型電晶體包含一第— ::第二導電型電晶體包含一第二犧牲閘極。接著移除 : 以形成一第一溝渠，並於第一溝渠内形成—第一金 第-物質層。然後平坦化第-金屬層以及第—物質層以及. 二犧牲閘極’以形成-第二溝渠，並於第二溝渠内形成移除」 層以及-第二物㈣。最後’平坦化第二金屬層以及第二物 201236059 本發明由於使用了旋塗式聚合物層等材料作第—物質層或第二 物質層，因此可崎顺佳的填观力以及麟的cMp處理效果。 此外，本發明於形成第—溝渠以及第二溝渠時，亦分別提供了新穎 的製程設計，可大大增加製程的可靠度。 【實施方式】 為使熟習本發明賴技術領域之-般技藝者能更進—步了解本 發月下文特列舉本發明之數個較佳實施例，並配合所附圖式，詳 細說明本發明的構成内容及所欲達成之功效。 明參考第1圖至第I2圖，所繪示為本發明第一實施例中製作具 有金屬閘極之半導體元件的方法之示賴。魏，提供—基底3〇〇， 例如是-絲底、切基底切覆絕緣㈣·_基 底等。基底30()上具有複數鑛賴隔離(shalbw STI)302。藉由淺溝渠隔離302所包圍的區域，可定義出彼此電性絕 緣的-第-主動區域400以及一第二主動區域·。接著分別於第 -主動區域400與第二主動區域5〇〇之基底上形成一第一導電 型電晶體402與-第二導電型電晶體5()2。在本發明較佳實施例中， 第-導電型電晶體402係為-P型電晶體，而第二導電型電晶體5〇2 則為- N型電晶體。但本領域技藝人士應可了解兩者亦可相反，例 如第一導電型電晶體402為N型電晶體時，第二導電型電晶體5〇2 則為P型電晶體。 201236059 的侧停止層，例如包含氮⑽層或金職化物層如氮化鈦或氮化 鈕。第一蓋層408則是一選擇性膜層，例如是一氮化矽層或氧化層 或此兩者的複合層。第一侧壁子410可為一複合膜層之結構，其可 包含咼溫氧化石夕層(high temperature oxide，HTO)、氮化石夕、氧化石夕 或使用六氣二石夕烧(hexachlorodisilane，Si2Cl6)形成的氮化石夕 (HCD-SiN)。於一實施例中，第一側壁子41〇亦可部份或完全被移 除，使得接觸洞姓刻停止層(contact etch stop layer，CESL) 306對於 • 第一導電型電晶體402以及第二導電型電晶體502能具有較佳應 力。第一輕摻雜汲極412以及第一源極/汲極414則以適當濃 度的摻質加以形成。 第一導電型電晶體502包含一第二閘極介電層504、一第二犧 牲閘極506、一第二蓋層508、一第二側壁子510、一第二輕摻 雜汲極512以及一第二源極/沒極514。第二導電型電晶體502 中各元件的實施方式大致與第一導電型電晶體402相同，在 胃此不加以贅述。此外，雖然第1圖中未明白繪出，但第一導 電型電晶體402與第二導電型電晶體502仍可包含其他半導 體結構，例如金屬矽化物層（salicide)、以選擇性磊晶成長 (selective epitaxial growth，SEG)而形成具有六面體(hexagon， 又叫sigma Σ)或八面體(octangon)截面形狀的源極/汲極或是其他 一層或多層之保護膜。在形成了第一導電型電晶體402與第 二導電型電晶體502後，接著於基底300上依序形成一接觸 洞餘刻停止層（contact etch stop layer，CESL) 306 與一内層 201236059 如第1圖所示，第一導電型電晶體402包含一第一閘極介電層 404、一第一犧牲閘極4〇6、一第一蓋層4〇8、一第一側壁子41〇、 一第一輕摻雜沒極（Hght d〇pe(} drain，LDD) 412 以及一第一 源極/汲極414。於本發明較佳實施例中，第一閘極介電層4〇4可 為一二氧化矽層，亦可為一高介電常數(high_K)閘極介電層。高介電 常數閘極介電層的材㈣如城⑽(siN)、氮氧化鄉趣)或者金 屬氧化物所組成之一群組，其中金屬氧化物可以是稀土金屬氧化物 層’例如是氧化铪伽加腿0?(也，册02)、矽酸铪氧化合物伽脇111 silicon oxide，HfSi〇4)、石夕酸铪氮氧化合物(hafnium siiic〇n oxyj^de， HfSiON)氧化銘(aiumjnum 〇xjde，a12〇3)、氧化鋼(ianthanum oxide， La2〇3)、I呂酸鑭(lanthanum aluminum oxide，LaAlO)、氧化组(tantalum oxide，Ta2〇5)、氧化錯(zirconium oxide，Zr02)、石夕酸錯氧化合物 (zirconium silicon oxide，ZrSi04)、錯酸铪(hafhium zirconium oxide， HfZr0)、銘絲组氧化物(strontium bismuth tantalate，SrBi2Ta209， SBT)、鍅鈦酸鉛(iea(j zirconate titanate，pbZrxTii χ〇3, pzT)或鈦酸鋇 勰(barium strontium titanate，BaxSr丨-xTi〇3，BST)等。第一閘極介電層 404亦可為一複合層，包含上述之任意組合，較佳地由下而上包含 二氧化矽層及高介電常數閘極介電層》第一犧牲閘極406則例如是 多晶矽閘極’但也可以是由多晶矽層、非晶石夕(am〇rph〇us Si)或者錯 層所組合的複合閘極，或者，於其他實施例中，第一犧牲閘極406 會具有傾斜側壁，而具有「上大下小」的形狀。在第一犧牲閘極4〇6 與第一閘極介電層404之間可選擇性地增加一匹配層或後續製程用 201236059 介電層（inter-layer dielectric ’ ILD)308，覆蓋在第一導電变電 晶體402與第二導電型電晶體502上。於一實施例中，接觸洞 钱刻停止層306具有一應力(stress)，以作為一選擇性應力系統 (selective strain scheme，SSS);接觸洞蝕刻停止層306可為單一層或 複合層’在第一導電型電晶體402上施加壓縮應力而在第二導電裂 電晶體502上施加伸張應力。 ⑩ 如第2圖所示，接著進行一平坦化製程，例如一化學機 械平坦化（chemical mechanical polish，CMP)製程或者一回蚀 刻製程或兩者的組合’以依序移除部份的内層介電層308、 部份的接觸洞餘刻停止層306，部份的第一側壁子41 〇、部 份的第二側壁子510，並完全移除第一蓋層4〇8、第二蓋層 508，直到暴露出第一犧牲閘極4〇6與第二犧牲閘極_5〇6 之頂面。 如第3圖所示，接著於基底300上全面沈積一遮罩層312以及 選擇性的一輔助層314。於本發明較佳實施例中，遮罩層312為一 氮化鈦(TiN)層’而輔助層314貝ij為-氧化石夕(si〇2)層。輔助層314 可提供後續第一圖案化之光阻層316較佳的附著力。遮罩層312之 厚度為60〜150埃(angstrom) ’較佳為100埃(angstr〇m)，而輔助層 314之厚度為15〜50埃(angstrom) ’較佳為2〇埃。接著，於基底300 上形成-第-圖案化光阻層316,其覆蓋於至少第二主動區域5〇〇。 201236059 接著利用第圖案化光阻層316為遮罩，以移除未被第一圖 案化光阻層316覆蓋之遮罩層312、輔助層314以及第一犧牲閑極 4〇6。上述步驟係先將第一圖案化光阻層训之圖形轉印至遮罩層 312後’再以遮罩層312為遮罩來移除第-犧牲閘極.然而，第 -犧牲閘極406的材質例如是多晶梦，而使用遮罩層312為遮罩來 移除下方之多晶石夕材質時，濕餘刻雖有較佳姓刻選擇比，能完美地 停结第-間極介電層彻上，但會有嚴重的側向崎_⑽ :k樣的問題在形成其他半導體結構，例如靜態隨機存取記憶 體（RAM)中具有連通PM_NM〇s的閘極等介面的半導體裝置 =，更容易會發生。相反地，乾_較無側向侧，但無法停止在 電層•上’而有過酬題，因此，一實施例是先以 部分第—犧牲閘極明6後’再以_刻移除最後的第 一犧牲閘極406，而停止在第一閘極介電層撕上。本發明之另一 實施例是在移除多晶石夕之第一犧牲閘極4〇6時，提供了如下文的步 ^ ^第4a，4b圖至第7a，7b圖，其中第处圖與第几圖所代 $的疋具有PMOS以及NM0S間極接面的铸體結構，可分別對 第^圖之橫剖面圖，而剖面係對應於第二犧牲閉極 之位置。第4b _第％圖之她即代表了由 之接面位置，虛線1之右側代表p财導體，左側代表N型半導體。 第騎示，縣特—魏職糾移除未被 第=案化光阻層316覆蓋的遮罩層312以及輔助層314，以及部 刀的第一犧牲閘極406。接著如第5圖所示，對第一圖案化光阻316 201236059 進仃-修整步驟(trimmed)，例如使用氧氣(ο!)、臭氧(a)、四氣化碳 防則化氫(HBr)等的電漿氣體以對第一圖案化光阻層316的側 壁進行修整，而稱微減少第一圖案化光阻層316的寬度，使得第一 圖案化光阻層3丨6大體上均勻地向内縮小，而形成一第二圖案化光 阻層爪。可以理解的是，若以上視圖的角度來看，第二圖案化光 ，層317的覆蓋面積會小於第一圖案化光阻層316的覆蓋面積。接 著如第6圖所示’以第二圖案化光阻層317為遮罩，移除 #圖案化光阻層317覆蓋之遮罩層犯以及輔助層似。最後，如^ 7a圖以及第7b圖所示，移除第二圖案化光阻層317後，進行一澄 敍刻步驟’以徹底移除第-犧牲閘極4G6。如第7a圖所示，移除第 -犧牲閘極406後，會在第-導電型電晶體4〇2中形成一第一溝渠 (*_6 ^如第7b圖所示’經_後的多晶石夕侧壁可以較準確 地位於虛線I處。 而在移除了第-犧牲閘極406而形成第一溝渠416後，接著如 #第8圖所示’於基底300上全面形成一第一金屬層318以及一第一 物質層32〇。第-金屬層318會共形地沿著第一溝渠416之表面形 成但不會完全填滿第-溝渠416 ’而第-物質層32〇會形成於第一 金屬層318上並填滿第一溝渠416。於本實施例中，第一金屬層318 為-滿足P型電晶體所需功函數要求的金屬，例如是氮化鈦⑽:咖 nitride，TiN)或碳化鈕(tantalum carbide，TaC)等，但不以上述為限。而 第一物質層320為一填洞能力良好的有機犧牲層，例如是一旋塗式 聚合物層(spin-on polymer layer)、一抗反射底層(b〇tt〇m ami reflective 201236059 coa ing layer，BARC layer)、-含碳介電層(娜加⑺她丨血g dide— ㈣的、-光吸收犧牲層(sac咖al喻論灿㈣咖 或一光阻層等，但不以上述為限。 接著如第9圖所示’進行一平坦化製程，例如一 CMp製程或 者-回触刻製程或者兩者的結合，以移除位於層内介電層3〇8上之 第-物質層32〇、第-金屬層训以及遮罩層犯，並暴露出第二導 電型電晶體5〇2之第二犧牲閘極5〇6。接著，移除第二導電型電晶 體502之第二犧牲閘極506，而於第二主動區域5〇〇中形成一第二籲 溝渠516。值得注意的是，本實施例中移除第二犧牲閘極5〇6之步 驟時，由於第一溝渠416已填入第一物質層32〇，故可直接使用一 全面性的蝕刻製程來移除第二犧牲閘極5〇6，而無須形成額外的光 阻層來保護第一導電型電晶體4〇2。 接著如第10圖所示，於基底300上全面形成一第二金屬層324 以及一第二物質層326。第二金屬層324會共形地沿著第二溝渠516 φ 之表面形成但不會完全填滿第二溝渠516，而第二物質層326會形 成於第一金屬層324上並填滿第二溝渠516。於本發明較佳實施例 中’第二金屬層324為一滿足N型電晶體所需功函數要求的金屬， 例如是紹化鈦(titanium aluminides，TiAl)、I呂化結(aluminum zirconium，ZrAl)、紹化鎢(aluminum tungsten，WA1)、!呂化组(aiuminum tantalum，TaAl)或紹化給(aluminum hafnium，HfAl)，但不以上述為 限。第二物質層326包含旋塗式聚合物層、抗反射底層、含碳介電 12 201236059 數大致上介於3.9eV與4.3eV之間。 在凡成了第一金屬閘極418以及第二金屬閘極518之後，即可 形成後續另一内層介電層（圖未示)及接觸插拴(c〇ntact plug)之製 作。或者，於接觸插拴形成前，還可以先完全移除内層介電層3〇6 以及接觸_刻停止層3〇8後，於基底3⑻上再次形成另一接觸洞 蝕刻停止層（圖未示），並且藉由施加紫外線或者熱能之步驟，以使 #新的接觸刻停止層產纟一應力而作為選擇性應力系統㈣如 strain scheme，SSS)，以提升第一導電型電晶體4〇2與第 二導電型電 晶體502之效能。接著再次形成另一内層介電層（圖未示），並於其 中形成所需之接觸插拴，此接觸插拴亦可具有適當的應力。 凊參考第η圖至第μ gj，所繪示為本發明中第二實施例中製 作具有金屬閘極之半導體元件的方法之示意圖。第二實施例之前半 鲁丰又Y驟與第實％例的第i圖至第9圖相同，可參考前文說明，在 此不加以贅述。而在如第9圖中形成第二溝渠516後接著請參考 第13圖’於基底3〇〇上依序形成一第二金屬層By以及一第三導體 層328。第二金屬層324會沿著第二溝渠516之表面形成，而第三 導體層328會填滿第二溝渠516。第二金屬層324與第三導體層似 的材料與第一實施例相同，在此不加以贅述。 接著如第U圖所不，進行-平坦化製程，以雜位於内層介電 層308上的第二金屬層似以及第三導體層似，並暴露出位於第 201236059 層、光吸收犧牲層或光阻層等，其材質與第一物質層32〇可以相同 也可以不同。 如第11圖所示，進行一平坦化製程，例如一 CMp製程或者一 回蝕刻製程，以移除位於内層介電層308上的第二金屬層324以及 第二物質層326’直到暴露出位於第一溝渠416中的第一物質層32〇 以及位於第二溝渠516中的第二物質層326。然後，移除位於第一 溝渠416中的第一物質層32〇以及位於第二溝渠516中的第二物質 層326,此時第一溝渠416以及第二溝渠516表面分別形成有1;型 · 的第一金屬層318以及第二金屬層324。 最後’如第12圖所示’於基底300上全面形成具低電阻值的第 三導體層328，使其填入於第一溝渠416以及第二溝渠516中。於 本發明較佳實施例中’第三導體層328包含例如是鋁(A1)、鈦(Ti)、 組(Ta)、鎢(W)、銳(Nb)、钥(Mo)、銅(Cu)、說化鈦〇1]^)、碳化鈦(TiC)、 氮化鈕(TaN)、鈦鎢(Ti/W)或鈦與氮化鈦(Ti/TiN)等複合金屬層料，或籲 者也可以包含奈米碳管(carbon nanotube)。接著進行一平坦化製程以 移除位於内層介電層308上的第三導體層328，而獲得一約略平坦 之表面。如此一來，位於第一溝渠416内的第一金屬層^30318以及 第三導體層328會形成第一導電型電晶體402(P型電晶體)中的第一 金屬閘極418，且其功函數大致上介於4.8eV與5.2eV之間；而位 於第二溝渠518内的第二金屬層324以及第三導體層328會形成第 二導電型電晶體502(N型電晶體)中的第二金屬閘極518，且其功函 13 201236059 一溝渠416中的第一物質層320。 在移除位於第一溝渠416中的第一物質層320之後，如第15 圖所示，於基底300上形成第四導體層329，使其至少填入第一溝 渠416中。第四導體層329的材質例如是鋁(A1)、鈦(Ti)、鈕(Ta)、 鎢(W)、鈮(Nb)、鉬(Mo)、銅(Cu)、氮化鈦(顶）、碳化欽(沉）、氮 化鈕(TaN)、鈦鎢(Ti/W)或鈦與氮化鈦(1¥1^)等複合金屬層料，或者 也可以包含奈米碳管(carb〇n nanotube)，較佳者第四導體層329和第 二導體層328為相同材質。接著進行一平坦化製程以移除位於内層 ”電層308上的第四金屬層329，即可以得到類似於第12圖之結 構即具有第-金屬閘極418之第一導電型電晶體4〇2，以及具有 第二金屬閘極518之第二導電型電晶體5〇2。 i考第16圖至第19圖，所繪示為本發明中第三實施例中 作具有金屬閘極之半導體元件 段步驟與第一實施·:方法之不思圖第二實施例之前半 W、實&例的第圖至第7a圖相同，可參考前述說明，在 叫贅返。如第7a圖中形成了第一溝渠416後，接著 成—Η， 三導體層328 ;滿第1、=沿著第一溝渠416之表面形成，而第 -一實施：：::：8與一 接著如第17圖所示，進行一平坦化製程，例如-CMP製程， 15 201236059 以移除位於層内介電層308上之第三導體層328、第一金屬層318 以及遮罩層312，並暴露出第二導電型電晶體5〇2之第二犧牲閘極 506。 如第18圖所示，移除第二導電型電晶體5〇2之第二犧牲閘極 506，而於第二主動區域5〇〇内形成一第二溝渠516。本實施例之一 特點在於，移除第二犧牲閘極5〇6的步驟係完全利用一溼蚀刻步 骤。此溼触刻步驟包含使用一強鹼溶液，例如含有丨〜4%體積百分 比的氮氧化四甲基銨(Tetramethylammonium hydroxide，TMAH)以及 臭氧(〇3)之溶液來徹底移除第二犧牲閘極5〇6。相較於習知以乾蝕刻 來移除第二犧牲閘極5〇6 ’本實施例之題刻步驟對於第一導電型 電晶體402或第二導電型電晶體5G2之第二介電層5()4較不易造成 損害。 接著如第19圖所示’於基底3⑻上依序形成—第二金屬層324 以及一第四導體層329，第二金屬層324以及第四導體層329會填 入於第二溝渠516中。第二金屬層324以及第四導體層329的材料 和第-實翻姻，在此不加哺述。職進行-平坦化製程，例 如- CMP製程，以移除位於内層介電層3〇8上的第二金屬層似 以及第四導體層329，而獲得—約略平坦之表面，而可以得到類似 於第12圖之結構。亦可得到具有第—金制極418之第一導電型電 日曰體402 ’以及具有第二金屬閘極518之第二導電型電晶體撕。 201236059 值得注意的是’前述實施方式係先形成高介電常數之間極八 層為例(high-Kfirst) ’而本領域技藝人士應當了解，本發明亦可二電 成金屬閘極之前，先移除閘極介電層，並再次形成㈣之高介= 數之閘極介電層(high-Kiast)，例如在第一溝渠内416形成第二: 層318之別，可先移除第一閘極介電層4〇4,之後再在第— 之表面上形成高介電常數之閘極介電層(離_〖_ ;同樣的16 二溝渠516内形成第二金屬層324之前，也可先移除第二閘極 =’之後再在第二溝渠516之表面上形成高介電常數之間極介 ^ 饮1 一種形成具有金屬閘極半導體，士爐 方法。她㈣知需分別使用不同的光罩來分別移除第-犧^201236059 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of fabricating a semiconductor element having a metal gate. [Prior Art] In the conventional semiconductor industry, polycrystalline germanium is widely used in semiconductor elements such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to the boron penetrating effect, and an unavoidable dipping effect, which makes the equivalent gate The thickness of the dielectric layer increases, and the gate capacitance decreases, which leads to the dilemma of component drive capability degradation. Therefore, the semiconductor industry has adopted a new gate material, such as the work function, which replaces the conventional polysilicon gate to replace the high dielectric constant (High-K) gate dielectric layer. Control electrode. In a complementary meta-method (CMOS) component, the dual-function metal gate needs to be paired with the NM〇s component, and the other must be matched with the PMOS component, thus integrating the related components. Technology and process control are more complex, and the thickness and composition control requirements of each material are more stringent. The manufacturing method of the double work function metal gate can be roughly divided into two categories: a front gate (gatefirst) process and a gate last process (gate last) process. Among them, the front gate process will create a metal gate 201236059, and then enter the noisy/secret joints to form a fine fire and form a high-heat schedule such as metal debris, thus making the selection and adjustment of materials (4) more challenging. In order to avoid the above-mentioned hot budget environment and to obtain a wider material selection, the industry has proposed a method of replacing the front gate process by the gate process. In the latter post-gate process, a sacrificial gate (sacrifice_ or replacement gate (4) acementgate) is formed first, and after the completion of the general EEG crystal, the sacrificial/replacement gate is removed to form a The pole groove _t job h), and then fill different metal in the gate groove according to electrical requirements. However, since the post-gate process is quite complicated and requires multiple processes to complete, the manufacturers are now striving to simplify the process of forming metal gates. SUMMARY OF THE INVENTION The present invention thus provides a process for producing a cast component having a gold matrix which provides better process reliability. / According to a preferred embodiment, the invention provides a method of making a gold with:. This method first provides a substrate. The substrate comprises a first = first conductivity type transistor. The first conductivity type transistor includes a first -> second conductivity type transistor including a second sacrificial gate. Then removing: to form a first trench, and forming a first gold-thick layer in the first trench. The first metal layer and the first material layer and the second sacrificial gate are then planarized to form a second trench, and a removal layer and a second material (four) are formed in the second trench. Finally, the second metal layer and the second material are flattened. 201236059 The present invention uses a material such as a spin-on polymer layer as the first material layer or the second material layer, so that the smooth filling power and the cMp of the lining are possible. Processing effect. In addition, the present invention also provides a novel process design when forming the first trench and the second trench, which can greatly increase the reliability of the process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to enable those skilled in the art of the present invention to further understand the present invention, the present invention will be described in detail below with reference to the accompanying drawings. The composition of the content and the desired effect. Referring to Figures 1 through 12, there is shown a method of fabricating a semiconductor device having a metal gate in a first embodiment of the present invention. Wei, provides - substrate 3 〇〇, for example, - silk bottom, cut substrate cutting insulation (four) · _ base and so on. The substrate 30() has a plurality of shalbs STIs 302. By the area surrounded by the shallow trench isolation 302, a first-active region 400 and a second active region can be defined which are electrically insulated from each other. Then, a first conductive type transistor 402 and a second conductive type transistor 5() 2 are formed on the substrates of the first active region 400 and the second active region 5A, respectively. In a preferred embodiment of the invention, the first conductivity type transistor 402 is a -P type transistor, and the second conductivity type transistor 5"2 is an -N type transistor. However, those skilled in the art will appreciate that the two can also be reversed. For example, when the first conductivity type transistor 402 is an N type transistor, the second conductivity type transistor 5 〇 2 is a P type transistor. The side stop layer of 201236059, for example, contains a nitrogen (10) layer or a gold layer such as titanium nitride or a nitride button. The first cap layer 408 is a selective film layer such as a tantalum nitride layer or an oxide layer or a composite layer of the two. The first sidewall sub-410 may be a composite film layer structure, which may include a high temperature oxide (HTO), a nitride rock, a oxidized oxide or a hexachlorodisilane. Nitride (HCD-SiN) formed by Si2Cl6). In one embodiment, the first sidewalls 41 can also be partially or completely removed, such that the contact etch stop layer (CESL) 306 is for the first conductive transistor 402 and the second Conductive transistor 502 can have better stress. The first lightly doped drain 412 and the first source/drain 414 are formed with a dopant of a suitable concentration. The first conductive type transistor 502 includes a second gate dielectric layer 504, a second sacrificial gate 506, a second cap layer 508, a second sidewall 510, and a second lightly doped drain 512. A second source/no pole 514. The embodiment of each element in the second conductivity type transistor 502 is substantially the same as that of the first conductivity type transistor 402, and will not be described in detail in the stomach. In addition, although not clearly depicted in FIG. 1, the first conductive type transistor 402 and the second conductive type transistor 502 may still include other semiconductor structures, such as a metal salicide layer, for selective epitaxial growth. (Selective epitaxial growth, SEG) forms a source/drain with a hexagonal (also known as sigma Σ) or octangon cross-sectional shape or another protective film of one or more layers. After the first conductive type transistor 402 and the second conductive type transistor 502 are formed, a contact etch stop layer (CESL) 306 and an inner layer 201236059 are sequentially formed on the substrate 300. As shown in FIG. 1 , the first conductive type transistor 402 includes a first gate dielectric layer 404 , a first sacrificial gate 4 〇 6 , a first cap layer 4 〇 8 , and a first sidewall sub-port 41 . a first light doped gate (Hght d〇pe (} drain, LDD) 412 and a first source/drain 414. In a preferred embodiment of the invention, the first gate dielectric layer 4〇4 It can be a ruthenium dioxide layer or a high dielectric constant (high_K) gate dielectric layer. The material of the high dielectric constant gate dielectric layer (4) is such as (10) (siN), nitrogen oxides, or A group of metal oxides, wherein the metal oxide may be a rare earth metal oxide layer 'for example, yttrium oxide gamma plus leg 0? (also, 02), bismuth oxylate oxime 111 silicon oxide, HfSi 〇4), hafnium siiic〇n oxyj^de, HfSiON oxidation (aiumjnum 〇xjde, a12〇3), oxidized steel (ianthanum o Xide, La2〇3), lanthanum aluminum oxide (LaAlO), oxidation group (tantalum oxide, Ta2〇5), zirconium oxide (Zr02), zirconium silicon oxide (zirconium silicon oxide, ZrSi04), hafhium zirconium oxide (HfZr0), strontium bismuth tantalate (SrBi2Ta209, SBT), lead zirconate titanate (jzirconate titanate, pbZrxTii χ〇3, pzT) or titanic acid Barium strontium titanate (BaxSr丨-xTi〇3, BST), etc. The first gate dielectric layer 404 can also be a composite layer, including any combination of the above, preferably containing cerium oxide from bottom to top. Layer and High Dielectric Constant Gate Dielectric Layer ” The first sacrificial gate 406 is, for example, a polysilicon gate” but may also be a combination of a polycrystalline germanium layer, an amorphous germanium (am〇rph〇us Si) or a split layer. The composite gate, or in other embodiments, the first sacrificial gate 406 will have a slanted sidewall with a "upper and lower" shape. The first sacrificial gate 4 〇 6 and the first gate A matching layer or subsequent process can be selectively added between the electrical layers 404. 36059 An inter-layer dielectric '' ILD' 308 overlies the first conductive transistor 402 and the second conductive transistor 502. In one embodiment, the contact hole stop layer 306 has a stress as a selective strain scheme (SSS); the contact hole etch stop layer 306 can be a single layer or a composite layer A compressive stress is applied to the first conductive type transistor 402 and a tensile stress is applied to the second conductive split crystal 502. 10, as shown in FIG. 2, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process or a combination of the two is performed to sequentially remove portions of the inner layer. The electrical layer 308, a portion of the contact hole residual stop layer 306, a portion of the first sidewall portion 41, a portion of the second sidewall spacer 510, and completely remove the first cap layer 4〇8, the second cap layer 508, until the top surface of the first sacrificial gate 4〇6 and the second sacrificial gate_5〇6 are exposed. As shown in FIG. 3, a mask layer 312 and a selective auxiliary layer 314 are then deposited over the substrate 300. In a preferred embodiment of the invention, the mask layer 312 is a titanium nitride (TiN) layer and the auxiliary layer 314 is a oxidized stone (si〇2) layer. The auxiliary layer 314 can provide better adhesion of the subsequent first patterned photoresist layer 316. The thickness of the mask layer 312 is 60 to 150 angstroms, preferably 100 angstroms, and the thickness of the auxiliary layer 314 is 15 to 50 angstroms, preferably 2 angstroms. Next, a -first patterned photoresist layer 316 is formed on the substrate 300 to cover at least the second active region 5A. 201236059 Next, the patterned photoresist layer 316 is used as a mask to remove the mask layer 312, the auxiliary layer 314, and the first sacrificial idle electrodes 4〇6 that are not covered by the first patterned photoresist layer 316. The above steps first transfer the first patterned photoresist layer pattern to the mask layer 312 and then remove the first-sacrificial gate with the mask layer 312 as a mask. However, the first-sacrificial gate 406 The material is, for example, a polycrystalline dream, and when the mask layer 312 is used as a mask to remove the polycrystalline stone material underneath, the wet residual has a better surname selection ratio, and can perfectly stop the first-pole. The dielectric layer is clear, but there is a serious lateral smear _(10) : k-like problem in the formation of other semiconductor structures, such as static random access memory (RAM) with a gate connected to the gate of PM_NM〇s interface Device =, it is easier to happen. On the contrary, the dry_has no lateral side, but can't stop on the electric layer. There is a reward problem. Therefore, in one embodiment, the first part is sacrificed after the first part of the sacrifice gate. The last first sacrificial gate 406 stops being torn on the first gate dielectric layer. Another embodiment of the present invention provides the following steps for removing the first sacrificial gate 4〇6 of the polycrystalline spine, as shown in the following paragraphs 4a, 4b to 7a, 7b, where the The cast structure having the PMOS and NM0S junctions with the 疋 of the graph of the first graph can be respectively applied to the cross-sectional view of the second graph, and the cross-section corresponds to the position of the second sacrificial closed pole. In the 4th_%th figure, she represents the junction position, the right side of the dotted line 1 represents the p-conductor, and the left side represents the N-type semiconductor. In the first riding, the county special-wei job removes the mask layer 312 and the auxiliary layer 314 which are not covered by the first photoresist layer 316, and the first sacrificial gate 406 of the blade. Next, as shown in FIG. 5, the first patterned photoresist 316 201236059 is trimmed, for example, using oxygen (ο!), ozone (a), and four gasification carbon to prevent hydrogen (HBr). The plasma gas of the first is trimmed to the sidewall of the first patterned photoresist layer 316, and the width of the first patterned photoresist layer 316 is reduced to be such that the first patterned photoresist layer 3丨6 is substantially uniformly Zooming inward to form a second patterned photoresist layer. It can be understood that, if viewed from the perspective of the above view, the coverage area of the second patterned light, layer 317 will be smaller than the coverage area of the first patterned photoresist layer 316. Next, as shown in Fig. 6, the second patterned photoresist layer 317 is used as a mask, and the mask layer covered by the patterned photoresist layer 317 is removed and the auxiliary layer is similar. Finally, as shown in Fig. 7a and Fig. 7b, after the second patterned photoresist layer 317 is removed, a sculpt step is performed to completely remove the first sacrificial gate 4G6. As shown in FIG. 7a, after the first-sacrificial gate 406 is removed, a first trench is formed in the first-conductivity type transistor 4〇2 (*_6^ as shown in FIG. 7b) The spar side wall can be located more accurately at the dotted line I. After the first-sacrificial gate 406 is removed to form the first trench 416, then a full surface is formed on the substrate 300 as shown in FIG. a metal layer 318 and a first material layer 32. The first metal layer 318 is conformally formed along the surface of the first trench 416 but does not completely fill the first trench 416' and the first material layer 32 Formed on the first metal layer 318 and filled with the first trench 416. In this embodiment, the first metal layer 318 is a metal that satisfies the required work function of the P-type transistor, such as titanium nitride (10): Nitrile, TiN) or tantalum carbide (TaC), etc., but not limited to the above. The first material layer 320 is an organic sacrificial layer with good hole filling ability, such as a spin-on polymer layer and an anti-reflective bottom layer (b〇tt〇m ami reflective 201236059 coa ing layer) , BARC layer), - carbon-containing dielectric layer (Naga (7) her blood g dide- (four), - light absorption sacrificial layer (sac coffee al-feasible (four) coffee or a photoresist layer, etc., but not above Then, as shown in FIG. 9, a planarization process, such as a CMp process or a touchback engraving process or a combination of the two, is performed to remove the first substance layer located on the dielectric layer 3〇8 in the layer. 32〇, the first metal layer training and the mask layer, and expose the second sacrificial gate 5〇6 of the second conductivity type transistor 5〇2. Then, the second layer of the second conductivity type transistor 502 is removed. The gate 506 is sacrificed, and a second channel 516 is formed in the second active region 5〇〇. It is noted that in the embodiment, the step of removing the second sacrificial gate 5〇6 is due to the first trench. 416 has been filled in the first material layer 32〇, so the second sacrificial gate 5〇6 can be removed directly using a comprehensive etching process. An additional photoresist layer is formed to protect the first conductive type transistor 4〇2. Next, as shown in Fig. 10, a second metal layer 324 and a second material layer 326 are integrally formed on the substrate 300. The second metal The layer 324 is conformally formed along the surface of the second trench 516 φ but does not completely fill the second trench 516, and the second material layer 326 is formed on the first metal layer 324 and fills the second trench 516. In the preferred embodiment of the present invention, the second metal layer 324 is a metal that satisfies the required work function of the N-type transistor, such as titanium aluminides (TiAl) and aluminum zirconium (ZrAl). ), aluminium tungsten (WA1), aiuminum tantalum (TaAl) or aluminum hafnium (HfAl), but not limited to the above. The second material layer 326 comprises spin-on polymerization The number of layers, anti-reflective underlayer, and carbon-containing dielectric 12 201236059 is roughly between 3.9 eV and 4.3 eV. After the first metal gate 418 and the second metal gate 518 are formed, a subsequent An inner dielectric layer (not shown) and a contact plug (c〇ntact plug) Alternatively, before the contact plug is formed, the inner dielectric layer 3〇6 and the contact/stop layer 3〇8 may be completely removed, and another contact hole etch stop layer is formed on the substrate 3(8) again. Show), and by applying ultraviolet or thermal energy steps, so that the #new contact inscription stop layer generates a stress as a selective stress system (4) such as a strain scheme (SSS) to enhance the first conductivity type transistor 4〇 2 and the performance of the second conductivity type transistor 502. Next, another inner dielectric layer (not shown) is formed again, and the desired contact plug is formed therein, and the contact plug can also have an appropriate stress. Referring to the ηth diagram to the μgj, a schematic diagram of a method of fabricating a semiconductor device having a metal gate in the second embodiment of the present invention is shown. The first half of the second embodiment is the same as the first to the ninth diagrams of the actual example, and can be referred to the foregoing description, and will not be described herein. After the second trench 516 is formed as shown in Fig. 9, a second metal layer By and a third conductor layer 328 are sequentially formed on the substrate 3A with reference to Fig. 13'. The second metal layer 324 is formed along the surface of the second trench 516, and the third conductor layer 328 fills the second trench 516. The material of the second metal layer 324 and the third conductor layer is the same as that of the first embodiment, and will not be described herein. Then, as shown in FIG. U, a planarization process is performed to disperse the second metal layer on the inner dielectric layer 308 and the third conductor layer, and expose the layer at the 201236059 layer, the light absorbing sacrificial layer or the light. The material of the resist layer or the like may be the same as or different from the first material layer 32A. As shown in FIG. 11, a planarization process, such as a CMp process or an etch process, is performed to remove the second metal layer 324 and the second material layer 326' on the inner dielectric layer 308 until exposed. The first material layer 32〇 in the first trench 416 and the second material layer 326 in the second trench 516. Then, the first material layer 32〇 located in the first trench 416 and the second material layer 326 located in the second trench 516 are removed, and the first trench 416 and the second trench 516 are respectively formed with a surface; The first metal layer 318 and the second metal layer 324. Finally, as shown in Fig. 12, a third conductor layer 328 having a low resistance value is formed on the substrate 300 to be filled in the first trench 416 and the second trench 516. In the preferred embodiment of the invention, 'the third conductor layer 328 comprises, for example, aluminum (A1), titanium (Ti), group (Ta), tungsten (W), sharp (Nb), molybdenum (Mo), copper (Cu). ), said titanium bismuth 1] ^), titanium carbide (TiC), nitride button (TaN), titanium tungsten (Ti / W) or titanium and titanium nitride (Ti / TiN) composite metal layer, or A carbon nanotube can also be included. A planarization process is then performed to remove the third conductor layer 328 on the inner dielectric layer 308 to obtain an approximately flat surface. As a result, the first metal layer 30318 and the third conductor layer 328 located in the first trench 416 form the first metal gate 418 of the first conductive type transistor 402 (P-type transistor), and the work thereof The function is substantially between 4.8 eV and 5.2 eV; and the second metal layer 324 and the third conductor layer 328 located in the second trench 518 form the second of the second conductivity type transistor 502 (N type transistor) The second metal gate 518, and its work function 13 201236059, a first material layer 320 in a trench 416. After removing the first substance layer 320 located in the first trench 416, as shown in Fig. 15, a fourth conductor layer 329 is formed on the substrate 300 so as to be filled in at least the first trench 416. The material of the fourth conductor layer 329 is, for example, aluminum (A1), titanium (Ti), button (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (top). , metal carbide (sink), nitride button (TaN), titanium tungsten (Ti / W) or titanium and titanium nitride (1 ¥ 1 ^) composite metal layer, or may also contain carbon nanotubes (carb n nanotube), preferably, the fourth conductor layer 329 and the second conductor layer 328 are made of the same material. Then, a planarization process is performed to remove the fourth metal layer 329 on the inner layer "electric layer 308", that is, a structure similar to the structure of FIG. 12, that is, the first conductive type transistor 4 having the first metal gate 418 can be obtained. 2, and a second conductive type transistor 5〇2 having a second metal gate 518. i is shown in FIGS. 16 to 19, which is a semiconductor having a metal gate in the third embodiment of the present invention. The component segment step is the same as the first embodiment. The method is the same as the second embodiment. The first half of the second embodiment is the same as the first to the seventh embodiment. Referring to the foregoing description, it can be called back. As shown in Fig. 7a. After the first trench 416 is formed, the triple-conductor layer 328 is formed, and the first and the second sides are formed along the surface of the first trench 416, and the first implementation: :::::8 and one subsequent as the 17th As shown, a planarization process, such as a -CMP process, 15 201236059, is performed to remove the third conductor layer 328, the first metal layer 318, and the mask layer 312 on the interlayer dielectric layer 308, and expose the The second sacrificial gate 506 of the second conductivity type transistor 5〇2. As shown in FIG. 18, the second conductivity type electric crystal is removed a second sacrificial gate 506 of 5.2, and a second trench 516 formed in the second active region 5A. One of the features of this embodiment is that the step of removing the second sacrificial gate 5〇6 is completely complete. Using a wet etching step, the wet etching step comprises using a strong alkaline solution, such as a solution containing 丨 4% by volume of Tetramethylammonium hydroxide (TMAH) and ozone (〇3). In addition to the second sacrificial gate 5 〇 6. The second sacrificial gate 5 〇 6 ' is removed by dry etching as compared to the conventional one. The inscribed step of this embodiment is for the first conductive type transistor 402 or the second conductive type. The second dielectric layer 5() 4 of the transistor 5G2 is less likely to cause damage. Next, as shown in Fig. 19, 'the second metal layer 324 and the fourth conductor layer 329 are formed sequentially on the substrate 3 (8), and the second metal The layer 324 and the fourth conductor layer 329 are filled in the second trench 516. The materials of the second metal layer 324 and the fourth conductor layer 329 and the first-in-one sacred marriage are not referred to here. a process, such as a CMP process, to remove the second metal on the inner dielectric layer 3〇8 Like the fourth conductor layer 329, a substantially flat surface is obtained, and a structure similar to that of Fig. 12 can be obtained. A first conductive type electric corona body 402' having the first gold pole 418 can also be obtained and The second conductive type transistor of the second metal gate 518 is torn. 201236059 It is worth noting that 'the foregoing embodiment is to form a high-Kfirst between high dielectric constants first' and those skilled in the art should It is understood that the present invention can also remove the gate dielectric layer before forming the metal gate, and again form a high dielectric layer (high) of (4), for example, in the first trench. 416 is formed as a second: layer 318, first removing the first gate dielectric layer 4〇4, and then forming a high dielectric constant gate dielectric layer on the surface of the first surface (from _ _ _ ; Before the second metal layer 324 is formed in the same 16 trenches 516, the second gate can be removed first and then a high dielectric constant is formed on the surface of the second trench 516. It has a metal gate semiconductor and a furnace method. She (4) knows that they need to use different masks to remove the first - sacrifice ^
以及第一犧牲閘極，本發明在移除第二犧牲間極時，第一溝槽已 入了物質層或者金屬層(請參考第9圖或第18圖），故可直接^ 2渠内之第二犧牲閘極而毋義外_案化光阻層 二 件’故僅需要一次的微影步驟即可達成。此外，本 二物質層。由於有機材料具有較作=-物質㈣ 謝式移除’故相當適合作為填人第渠二 二而有機材料時，再—併形成作_二第=導 ==度。另外，本發明於形成第-溝上 -縣時，》別提供了新_製程設 … 用了光阻修整製程’以及形成第-溝竿時’爾一溝渠時，使 弟一溝鱗，使用了厘_製程，皆 201236059 可增加製㈣可靠度而提高產品良率。 X上所述僅為本發明之較佳實施例，凡依本發明申請專利範 所做之均㈣倾舞1顧本發明之涵蓋範圍。 【圖式簡單說明】And the first sacrificial gate, when the second sacrificial interpole is removed, the first trench has entered the material layer or the metal layer (refer to FIG. 9 or FIG. 18), so that the channel can be directly The second sacrificial gate is the same as the two-piece photoresist layer, so it only takes one lithography step to achieve. In addition, the two material layers. Since the organic material has a comparatively--substance (4) Xie-type removal, it is quite suitable as an organic material for filling the second channel, and then formed into a _2==== degree. In addition, the present invention provides a new process for the formation of the first ditch-county, "the use of the photoresist trimming process" and the formation of the first ditch when the "er-ditch", the brother of a ditch scale, used PCT _ process, both 201236059 can increase the system (four) reliability and improve product yield. The above description of X is only a preferred embodiment of the present invention, and all of the above-mentioned patent applications are based on the scope of the present invention. [Simple description of the map]
min T 第1圖至第12圖所繪示為本發明第 極之半導體元件的方法之示意圖。 第13圖至第ls圖所纷示為本發明第二實施例中製作具有金屬 間極之半物元件財法之示意圖。 $ 16 19 __示為本發 施例中製作具有金 間極之半導航件的方法之示意圖。 300 302 306 308 312 314 316 317 318 【主要元件符號說明】 基底 淺溝渠隔離 接觸洞姓刻停止層 層内介電層 遮罩層 輔助層 第一圖案化光隍層 第二圖案化光阻層 第一金屬層 406 第一犧牲閘極 408 第一蓋層 410 第一側壁子 412 第一輕摻雜汲極 414 第一源極/汲極 416 第一溝渠 418 第一金屬閘極 500 第二主動區域 502 第二導電型電晶體 201236059 320 第一物質層 504 第二閘極介電層 324 第二金屬層 506 第二犧牲閘極 326 第二物質層 508 第二蓋層 328 第三導體層 510 第二側壁子 329 第四導體層 512 第二輕摻雜汲極 400 第一主動區域 514 第二源極/汲極 402 第一導電型電晶體 516 第二溝渠 404 第一閘極介電層 518 第二金屬閘極 19Min T Fig. 1 to Fig. 12 are schematic views showing a method of the semiconductor element of the first embodiment of the present invention. 13 to ll are schematic views showing a method of manufacturing a half-element component having an inter-metal pole in the second embodiment of the present invention. $16 19 __ is a schematic diagram showing a method of making a half-navigation member having a gold interpole in the present embodiment. 300 302 306 308 312 314 316 317 318 [Description of main component symbols] Base shallow trench isolation contact hole name stop layer inner dielectric layer mask layer auxiliary layer first patterned aperture layer second patterned photoresist layer a metal layer 406 first sacrificial gate 408 first cap layer 410 first sidewall sub-412 first lightly doped drain 414 first source/drain 416 first trench 418 first metal gate 500 second active region 502 second conductivity type transistor 201236059 320 first material layer 504 second gate dielectric layer 324 second metal layer 506 second sacrificial gate 326 second material layer 508 second cap layer 328 third conductor layer 510 second Sidewall sub-329 fourth conductor layer 512 second lightly doped drain 400 first active region 514 second source/drain 402 first conductivity type transistor 516 second trench 404 first gate dielectric layer 518 second Metal gate 19