201234496 六、發明說明： 【發明所屬之技術領域】 本1發明係關於薄膜電晶體之技術領域，特別是關於薄 膜電晶體的閘極電極層之技術領域。 【先前技術】 以往，於LTPS製程中，由於高溫製程爲必需，因此 採用有於配線使用高熔點金屬的技術。但是，於代表高熔 點金屬的Ta、Ti、Mo、W中，並無在以濕蝕刻所致之加 工性、電阻、耐蝕性以及耐熱性（突起耐性）之所有特性 皆良好的材料，故市場上，企求可解決上述問題之閘極電 極層的材料。 就記載有高熔點金屬之靶材的文獻而言，係例如有下 述專利文獻。 [先前技術文獻] [專利文獻] [專利文獻1]日本特開2 003 -3 3 8465號公報 【發明內容】 [發明所欲解決之課題] 本發明係爲了解決上述先前技術之缺陷而創作者，其 目的爲提供可進行高溫加熱之閘極電極層的材料。 201234496 [用以解決課題之手段] 由於W及Mo係熔點高，且熱膨脹係數與_ 板相近，因此耐熱性優異。此外，亦有不會擴_ 氧化膜中的優點。但是，W係有電阻率高，又不 的缺點，而Mo雖係電阻率低且可濕蝕刻，但有 ，且蝕刻速率過快的缺點。 本發明之發明者等發現：由一定比例的W劈 成之MoW薄膜，係可藉由濕蝕刻而進行圖案 MoW薄膜可得到能耐高溫的閘極電極層、和連 電極層的配線層一事，而完成本發明。 亦即，本發明係一種電極膜，其係由含有鉬 鎢薄膜所形成之電極膜，其特徵爲：鎢係以8.0 上未達20.0原子％的比例被含有。 此外，本發明係一種濺鍍靶材，其係含有鉬 鍍靶材，其特徵爲：鎢係以8.0原子％以上未達 子％的比例被含有。 本發明係一種薄膜電晶體，其係具有：半導 極區域與源極區域；位於前述汲極區域與前述源 間的通道區域；與前述通道區域接觸的閘極絕緣 接觸到前述閘極絕緣層的閘極電極層，該薄膜電 特徵爲：前述閘極電極層，係爲以8.0原子％ 2 0 · 0原子％的比例含有鎢之鉬鎢薄膜。 本發明係如申請專利範圍第3項所記載之薄 ，其中，前述閘極絕緣層係Si02薄膜。 底玻璃基 到矽或矽 能濕蝕刻 耐蝕性差 I Mo所形 化，且由 接於閘極 和鎢的組 原子％以 和鎢之濺 :20.0 原 體層之汲 極區域之 層；以及 晶體，其 以上未達 膜電晶體 201234496 本發明係一種薄膜電晶體製造方法，其係製造薄膜電 晶體之薄膜電晶體製造方法，該薄膜電晶體係具有：半導 體層之汲極區域與源極區域；位於前述汲極區域與前述源 極區域之間的通道區域；與前述通道區域接觸的閘極絕緣 層；以及接觸到前述閘極絕緣層的閘極電極層，該薄膜電 晶體製造方法’其特徵爲：前述閘極電極層，係將以8原 子％以上未達20.0原子％的比例而含有鎢之鉬鎢薄膜， 形成於前述閘極絕緣層表面，且藉由含有磷酸、硝酸、醋 酸和水的蝕刻液來將前述鉬鎢薄膜圖案化而形成。 此外，本發明係如申請專利範圍第5項所記載之薄膜 電曰日體之製ia方法’其中，在形成目ij述間極電極層之後，· 將摻雜物植入半導體層，並加熱至400。(：以上800。(：以下 的溫度範圍，而形成前述源極區域與前述汲極區域。 [發明效果] 本發明所使用之MoW薄膜及閘極電極層，係即使對 於450°C以上的高溫活性化退火也不會變形或熔融，且不 會形成突起。此外，不會在閘極絕緣層中或半導體中擴散 。又，電阻率較W薄膜之閘極電極層（15#Q.cm)更 小。 此外，本發明之MoW薄膜，係可藉由將磷酸、硝酸 、醋酸和水作混合所得之蝕刻液來進行蝕刻，故耐蝕性較 Mo薄膜之閘極電極層更強。 201234496 【實施方式】 第1圖（a)之符號10，係形成有本發明之閘極電極 層的玻璃基板，於其表面上，係形成有底塗層π，其係 用以防止玻璃基板1 0內部的雜質，擴散到玻璃基板1 〇表 面上的薄膜》於本實施例中，底塗層11係Si02膜。 將玻璃基板10搬入矽膜形成裝置內，並在真空環境 中’將化學結構中具有Si之原料氣體供給到矽膜形成裝 置的內部，且於底塗層11的表面，在低溫下使矽膜成長 ，之後，藉由雷射照射裝置等之加熱手段使矽膜結晶化， 如第1圖（b)所示，於底塗層11的表面形成多晶矽膜 12 ° 接著，於多晶矽膜12之表面配置已圖案化的光阻膜 ，並藉由乾蝕刻法或濕蝕刻法，一邊讓位於光阻膜底面之 多晶矽膜1 2殘留，一邊對位於光阻膜的開口底面之多晶 矽膜12進行蝕刻而去除，之後，將光阻膜去除，如第1 圖（c)所示，於底塗層11的表面，形成複數個由已圖案 化之多晶矽膜1 2所形成之半導體層1 3。 在該狀態下，於玻璃基板10上，底塗層11之表面與 半導體層13之表面會露出，藉由CVD方法等之成膜方法 ，於玻璃基板10上露出的部分之表面，如第1圖（d)所 示，形成絕緣膜1 4。於本實施例中，絕緣膜1 4係Si02膜 〇 於該絕緣膜14之表面，形成已圖案化的光阻膜，並 藉由乾蝕刻法或濕蝕刻法，一邊讓光阻膜所覆蓋的部分殘 -8 - 201234496 留，一邊對露出於光阻膜之開口底面的部分之絕緣膜14 進行蝕刻去除，然後，將光阻膜去除，如第1圖（e)所 示，於各半導體層13上，分別形成由已圖案化之絕緣膜 1 4所形成之閘極絕緣層1 5。 閘極絕緣層1 5，係分別位於一個半導體層1 3的寬度 方向中央，且於半導體層13之寬度方向的兩端，係並不 配置閘極絕緣層15，而是分別形成有使半導體層13從閘 極絕緣層15突出而露出的部分19s、19d。 在該狀態下，於玻璃基板1 0上，係露出：閘極絕緣 層15之表面、底塗層11之未配置有半導體層13的部分 之表面、以及半導體層13之從閘極絕緣層15突出的部分 之表面，若將該等露出的面設爲成膜面，則將玻璃基板 10搬入已設爲真空環境的濺鍍裝置之內部的真空環境中 ，並將成膜面朝向靶材地作配置。 在此所使用之靶材，係以特定比例含有Mo與W，且 將Ar氣體作爲濺鍍氣體而導入濺鍍裝置之內部的真空環 境中，並藉由Ar氣體來對靶材進行濺鎪。 藉由濺鍍而從靶材飛出的Mo與W會到達成膜面，且 如第1圖（f)所示，於玻璃基板10之露出面，即成膜面 上，形成有含有Mo與W之MoW薄膜（鉬鎢薄膜）16。 接著，將已圖案化之MoW薄膜用光阻膜形成於MoW 薄膜1 6上。 第1圖（g)之符號17，係配置於MoW薄膜16上之 MoW薄膜用光阻膜，且配置成至少覆蓋閘極絕緣層1 5之 201234496 上方位置的MoW薄膜16。 在該狀態下，將玻璃基板10浸漬於特定的蝕刻液中 ，並使Mow薄膜16的表面當中，從Mow薄膜用光阻膜 1 7露出的部分接觸到蝕刻液而蝕刻去除，接著，若將 M〇W薄膜用光阻膜1 7去除，則如第2圖（a )所示， MoW薄膜16會被圖案化，且形成有：由已圖案化的 MoW薄膜16所形成之閘極電極層18與不圖示的配線層 。閘極電極層1 8，係接觸到閘極絕緣層1 5，且配線膜係 連接到閘極電極層1 8。201234496 VI. Description of the Invention: [Technical Field] The present invention relates to the technical field of thin film transistors, and more particularly to the technical field of gate electrode layers of thin film transistors. [Prior Art] Conventionally, in the LTPS process, since a high-temperature process is necessary, a technique of using a high-melting-point metal for wiring is employed. However, in Ta, Ti, Mo, and W, which represent a high-melting-point metal, there is no material which is excellent in all properties such as workability, electrical resistance, corrosion resistance, and heat resistance (protrusion resistance) by wet etching, so the market In the above, the material of the gate electrode layer which can solve the above problem is sought. For the literature describing a target of a high melting point metal, for example, the following patent documents are available. [Prior Art] [Patent Document 1] [Patent Document 1] Japanese Laid-Open Patent Publication No. 2 003 -3 3 8465 [Problem to be Solved by the Invention] The present invention is made to solve the defects of the prior art described above. The purpose is to provide a material for a gate electrode layer that can be heated at a high temperature. 201234496 [Means for Solving the Problem] Since W and Mo have high melting points and a thermal expansion coefficient close to the _ plate, they are excellent in heat resistance. In addition, there are advantages in the expansion of the oxide film. However, the W system has a disadvantage of high resistivity and no disadvantage, and Mo has a disadvantage that the resistivity is low and wet etching is possible, and the etching rate is too fast. The inventors of the present invention have found that a MoW film formed by a certain ratio of W can be obtained by patterning a MoW film by wet etching to obtain a gate electrode layer capable of withstanding high temperatures and a wiring layer of a connecting electrode layer. The present invention has been completed. That is, the present invention is an electrode film which is an electrode film formed of a film of molybdenum and tungsten, characterized in that tungsten is contained in a ratio of less than 20.0 atom% on 8.0. Further, the present invention is a sputtering target comprising a molybdenum plating target, characterized in that tungsten is contained in a proportion of 8.0 atom% or more and less than 5% by weight. The present invention is a thin film transistor having a semiconducting region and a source region; a channel region between the drain region and the source; and a gate in contact with the channel region insulatingly contacting the gate insulating layer The gate electrode layer is characterized in that the gate electrode layer is a tungsten-molybdenum tungsten film containing tungsten at a ratio of 8.0 at% 2 0 · 0 atom%. The present invention is as described in claim 3, wherein the gate insulating layer is a SiO 2 film. The bottom glass base to the tantalum or niobium can be wet-etched with poor corrosion resistance I Mo, and consists of a group of atoms connected to the gate and tungsten and a layer of tungsten: 20.0 of the drain layer of the precursor layer; and a crystal The above-mentioned film-free transistor 201234496 is a method for manufacturing a thin film transistor, which is a method for manufacturing a thin film transistor of a thin film transistor having a drain region and a source region of a semiconductor layer; a channel region between the drain region and the source region; a gate insulating layer in contact with the channel region; and a gate electrode layer contacting the gate insulating layer, the thin film transistor manufacturing method is characterized by: The gate electrode layer is formed by depositing a tungsten-molybdenum-tungsten film of tungsten at a ratio of 8 at% or more and less than 20.0 at%, on the surface of the gate insulating layer, and etching by containing phosphoric acid, nitric acid, acetic acid, and water. The liquid is formed by patterning the molybdenum-tungsten film. Further, the present invention is the method for producing a thin film electroporation body according to the fifth aspect of the invention, wherein after the formation of the interelectrode electrode layer, the dopant is implanted into the semiconductor layer and heated. To 400. (: the above 800: (the following source range is formed to form the source region and the drain region. [Effect of the invention] The MoW film and the gate electrode layer used in the present invention are at a high temperature of 450 ° C or higher. The activation annealing does not deform or melt, and no protrusions are formed. Further, it does not diffuse in the gate insulating layer or in the semiconductor. Moreover, the resistivity is higher than that of the gate electrode layer of the W film (15#Q.cm) Further, the MoW film of the present invention can be etched by an etching solution obtained by mixing phosphoric acid, nitric acid, acetic acid and water, so that the corrosion resistance is stronger than that of the gate electrode layer of the Mo film. MODE FOR CARRYING OUT THE INVENTION A symbol 10 of Fig. 1(a) is a glass substrate on which a gate electrode layer of the present invention is formed, and an undercoat layer π is formed on the surface thereof to prevent the inside of the glass substrate 10 from being formed. Impurity, film diffused onto the surface of the glass substrate 1 In the present embodiment, the undercoat layer 11 is a SiO 2 film. The glass substrate 10 is carried into a ruthenium film forming apparatus, and has a Si in a chemical structure in a vacuum environment. The raw material gas is supplied to the ruthenium film The inside of the device is formed, and the ruthenium film is grown on the surface of the undercoat layer 11 at a low temperature, and then the ruthenium film is crystallized by a heating means such as a laser irradiation device, as shown in FIG. 1(b). A polycrystalline germanium film 12 is formed on the surface of the undercoat layer 11 . Next, a patterned photoresist film is disposed on the surface of the polysilicon film 12, and the polysilicon layer located on the bottom surface of the photoresist film is disposed by dry etching or wet etching. The film 12 remains, and the polysilicon film 12 located on the bottom surface of the opening of the photoresist film is removed by etching, and then the photoresist film is removed, and is formed on the surface of the undercoat layer 11 as shown in FIG. 1(c). A plurality of semiconductor layers 13 formed of the patterned polycrystalline germanium film 12. In this state, on the glass substrate 10, the surface of the undercoat layer 11 and the surface of the semiconductor layer 13 are exposed, by a CVD method or the like. In the film forming method, the insulating film 14 is formed on the surface of the portion exposed on the glass substrate 10 as shown in Fig. 1(d). In the present embodiment, the insulating film 14 is a SiO2 film bonded to the insulating film. The surface of 14 forms a patterned photoresist film and is dry etched Or the wet etching method, while leaving the portion -8 - 201234496 covered by the photoresist film, the insulating film 14 exposed on the bottom surface of the opening of the photoresist film is etched and removed, and then the photoresist film is removed, such as As shown in Fig. 1(e), a gate insulating layer 15 formed of a patterned insulating film 14 is formed on each of the semiconductor layers 13. The gate insulating layer 15 is located in a semiconductor layer. In the center of the width direction of the semiconductor layer 13, the gate insulating layer 15 is not disposed at both ends in the width direction of the semiconductor layer 13, but a portion 19s in which the semiconductor layer 13 is protruded from the gate insulating layer 15 is formed. In this state, on the glass substrate 10, the surface of the gate insulating layer 15, the surface of the portion of the undercoat layer 11 where the semiconductor layer 13 is not disposed, and the gate of the semiconductor layer 13 are exposed. When the surface on which the insulating layer 15 protrudes is a film formation surface, the glass substrate 10 is carried into a vacuum environment inside a sputtering apparatus which is a vacuum environment, and the film formation surface is oriented. The target is configured. The target used herein contains Mo and W in a specific ratio, and Ar gas is introduced as a sputtering gas into a vacuum environment inside the sputtering apparatus, and the target is sputtered by Ar gas. Mo and W which are ejected from the target by sputtering are brought to the film surface, and as shown in FIG. 1(f), Mo is formed on the exposed surface of the glass substrate 10, that is, on the film formation surface. W MoW film (molybdenum tungsten film) 16. Next, a patterned photoresist film for MoW film was formed on the MoW film 16. The symbol 17 of Fig. 1(g) is a photoresist film for a MoW film disposed on the MoW film 16, and is disposed so as to cover at least the MoW film 16 at a position above the 201234496 of the gate insulating layer 15. In this state, the glass substrate 10 is immersed in a specific etching liquid, and a portion of the surface of the Mow film 16 exposed from the photoresist film 17 of the Mow film is exposed to the etching liquid to be etched and removed, and then, if The M〇W film is removed by the photoresist film 17 , and as shown in FIG. 2( a ), the MoW film 16 is patterned, and a gate electrode layer formed of the patterned MoW film 16 is formed. 18 and wiring layers not shown. The gate electrode layer 18 is in contact with the gate insulating layer 15 and the wiring film is connected to the gate electrode layer 18.
MoW薄膜1 6之蝕刻中所使用的蝕刻液，係磷酸、硝 酸、醋酸、水之混合液，在此，係使用關東化學（股）之 商品名「Mo/Al/Mo飽刻液（假）j 。 閘極電極層1 8並不與半導體層1 3接觸，且於閘極絕 緣層15之寬度方向兩端的外側，係分別存在有讓半導體 層13之表面露出的部分19s、19d。 在該狀態下，藉由離子植入裝置，而從露出的部分 19s、19d之上方，朝向半導體層13照射離子，且將閘極 電極層18作爲光罩，並將p型或η型之摻雜物離子植入 半導體層13之露出的表面19s、19d。 接著，若是對半導體層13進行加熱並作退火處理， 而將摻雜物活性化，則如第2圖（b )所示般，半導體層 13當中，露出吟表面19s、19d之下方位置的部分會藉由 已活性化的摻雜物而成爲可與電極歐姆接觸（Ohmic contact)的源極區域20s與汲極區域20d，且源極區域 -10- 201234496 20s與汲極區域20d之間的部分，係成爲通道區域20c。 在源極區域20s與汲極區域20d露出的狀態下，於玻 璃基板10上的露出之表面，如第2圖（c)所示，形成由 絕緣物質所形成之保護膜22。 接著，形成於保護膜22當中之各源極區域20s上的 位置、各汲極區域20d上的位置、以及分別連接到各閘極 電極層1 8的配線層上的位置處而作開口的光阻膜，且藉 由蝕刻來將露出於開口底面的部分之保護膜22進行蝕刻 ，之後，若將該光阻膜去除，則會在保護膜22中，於源 極區域20s上、汲極區域20d上、及配線層上形成有接觸 孔，且於該底面上，源極區域20s與汲極區域20d及配線 層會分別露出。 第2圖（d )之符號23s、23d，係表示在分別形成在 源極區域20s上之保護膜22與汲極區域2 0d上之保護膜 22的接觸孔。形成在配線層上之保護膜22處的接觸孔係 不圖示。 接著，形成至少涵蓋接觸孔23s、23d之底面與保護 膜22表面之連續的金屬膜，且於該金屬膜上形成已圖案 化的光阻膜，並將露出於該光阻膜之開口底面的金屬膜蝕 刻去除，若將光阻膜去除，則如第2圖（e )所示，會分 別形成有分別接觸到位於各接觸孔23 s、23 d之底面的源 極區域23s的表面與汲極區域23d的表面之源極電極層 24s與汲極電極層24d，而得到複數個薄膜電晶體25。 於此等薄膜電晶體25中，一個薄膜電晶體25中之源 -11 - 201234496 極電極層24s與汲極電極層24d和閘極電極層18係互不 接觸，且在源極電極層24s與汲電極層24d之間施加有電 壓的狀態下，藉由控制施加於閘極電極層1 8的電壓大小 ，而控制通區域20c之內部表面的電荷，並藉此控制源極 區域20s與汲極區域20d之間的導通與阻斷，而使電晶體 25 ON、OFF。 爲了使電晶體25以高速ON、OFF，係期望使閘極電 極層18與其所連接的配線層爲低電阻，因此，構成閘極 電極層18與其所連接的配線層之MoW薄膜16之電阻係 以較低爲理想。 [實施例] 變更Mo與W的比例而製作複數個MoW靶材，並藉 由Ar氣體來將各MoW靶材進行濺鍍，且將W之含有率 爲0〜100 at %之範圍的MoW薄膜（在此，也將W之含有 率爲0%和100%的情況，設爲被包含在MoW薄膜或 MoW靶材中），形成在試驗用之玻璃基板上。MoW薄膜 之組成，係與MoW薄膜形成中所使用的靶材相同。 將各MoW薄膜的蝕刻速率與電阻率之測定結果顯示 於下述表1 β -12- 201234496 [表1] 表1 MoW薄膜之蝕刻速率、電阻率The etching liquid used for the etching of the MoW film 16 is a mixed solution of phosphoric acid, nitric acid, acetic acid, and water. Here, the trade name "Mo/Al/Mo full solution (false) of Kanto Chemical Co., Ltd. is used. j. The gate electrode layer 18 is not in contact with the semiconductor layer 13 and the portions 19s and 19d exposing the surface of the semiconductor layer 13 are present outside the gate insulating layer 15 in the width direction. In the state, ions are irradiated toward the semiconductor layer 13 from above the exposed portions 19s and 19d by the ion implantation apparatus, and the gate electrode layer 18 is used as a mask, and the p-type or n-type dopant is used. The ions are implanted into the exposed surfaces 19s and 19d of the semiconductor layer 13. Next, if the semiconductor layer 13 is heated and annealed to activate the dopant, the semiconductor layer is as shown in Fig. 2(b). In the portion 13 which is exposed below the surface 19s, 19d, the source region 20s and the drain region 20d which are in ohmic contact with the electrode, and the source region are formed by the activated dopant. -10- 201234496 20s and the part between the bungee area 20d The channel region 20c is formed. In the state where the source region 20s and the drain region 20d are exposed, the exposed surface on the glass substrate 10 is protected by an insulating material as shown in Fig. 2(c). The film 22 is formed at a position on each of the source regions 20s in the protective film 22, a position on each of the drain regions 20d, and a position on the wiring layer of each of the gate electrode layers 18, respectively. The photoresist film is opened, and the protective film 22 exposed to the bottom surface of the opening is etched by etching. Then, when the photoresist film is removed, the protective film 22 is on the source region 20s. Contact holes are formed in the drain region 20d and on the wiring layer, and the source region 20s, the drain region 20d, and the wiring layer are respectively exposed on the bottom surface. The symbols 23s and 23d of Fig. 2(d) are A contact hole is formed in the protective film 22 formed on the source region 20s and the protective film 22 on the drain region 20d. The contact hole formed in the protective film 22 on the wiring layer is not shown. Covering at least the bottom surfaces of the contact holes 23s, 23d and the protective film 2 a continuous metal film on the surface, and a patterned photoresist film is formed on the metal film, and the metal film exposed on the bottom surface of the opening of the photoresist film is etched away. If the photoresist film is removed, 2 (e), the source electrode layer 24s and the drain electrode which are respectively in contact with the surface of the source region 23s on the bottom surface of each of the contact holes 23s, 23d and the surface of the drain region 23d are formed. The layer 24d is obtained to obtain a plurality of thin film transistors 25. In the thin film transistors 25, the source -11 - 201234496 electrode layer 24s and the gate electrode layer 24d and the gate electrode layer 18 in one thin film transistor 25 are used. The electrodes on the inner surface of the pass region 20c are controlled by controlling the magnitude of the voltage applied to the gate electrode layer 18 in a state where no voltage is applied between the source electrode layer 24s and the drain electrode layer 24d. Thereby, the conduction and blocking between the source region 20s and the drain region 20d are controlled to turn the transistor 25 ON and OFF. In order to turn the transistor 25 at a high speed, it is desirable to make the gate electrode layer 18 and the wiring layer to which it is connected low in resistance. Therefore, the resistance of the MoW film 16 constituting the gate electrode layer 18 and the wiring layer to which it is connected is formed. It is ideal for lower. [Examples] A MoW film in which a plurality of MoW targets were produced by changing the ratio of Mo to W, and each MoW target was sputtered by Ar gas, and a content ratio of W was 0 to 100 at % (Here, the case where the content ratio of W is 0% and 100% is included in the MoW film or the MoW target), and it is formed on the glass substrate for testing. The composition of the MoW film is the same as that used in the formation of the MoW film. The measurement results of the etching rate and the resistivity of each MoW film are shown in the following Table 1 β -12 - 201234496 [Table 1] Table 1 Etching rate and resistivity of the MoW film
MoW膜中W 含有率（atJ〇 蝕刻速度 (入/秒） 電阻率 (μ Ω cm) 0 (Pure Mo) 74.9 11.1 6.0 36.5 η.6 11.4 18.0 11.8 16.7 11.0 12.6 21.9 5.2 12.9 25.0 1.9 13.7 37.0 0 15.6 100 (Pure W) 0 16.6 將各MoW靶材濺鍍時的Ar壓力爲0.3Pa，玻璃基板 溫度爲l〇〇°C，且所形成之MoW薄膜的厚度爲300nm。 第3圖、第4圖，係表1之測定結果的圖表，第3圖 係展示W含有率與電阻率之關係，且第4圖係展示W含 有率與蝕刻速度之關係。 由於蝕刻速率在3 0A/秒以上係過快，而難以控制配 線形狀，且5A/秒以下係蝕刻時間過長，因此依據上述表 1、第3圖、第4圖，W含有率（Mow薄膜中，相對於 Mo原子與W原子之合計個數之W原子的個數）爲8at% 以上未達20.0at%係適用於本發明，特別是11.4at%以上 16.7at%以下之範圍爲可得到最適當的蝕刻速度。 相較於MoW薄膜爲l〇〇at%之W薄膜，若MoW薄膜 在該W含有率的範園內，則電阻率會充分地縮小，此外 ，由於MoW薄膜係熔點高，因此可於形成閘極電極層18 -13- 201234496 後，離子植入摻雜物，並加熱使摻雜物活性化，而形成源 極區域20s與汲極區域20d »由此可知：MoW薄膜係亦可 使用於高速動作的薄膜電晶體。 另外，關於所形成之W含有率爲0%〜100%之各 MoW薄膜’在N2氣體環境中以675 °C、進行1小時的熱 處理之後，經顯微鏡觀察，於各MoW薄膜中未見突起的 發生。 【圖式簡單說明】 [第1圖](a )〜（g):用以說明本發明之電晶體製 造方法的圖式。 [第2圖](a)〜（e):係接續第1圖的圖式。 [第3圖]係展示W含有率與電阻率之關係的圖表》 [第4圖]係展示W含有率與蝕刻速度之關係的圖表。 【主要元件符號說明】 13 :半導體層 1 5 :閘極絕緣層 1 6 :鉬鎢薄膜 1 8 :閘極電極層 2 0d :汲極區域 20s :源極區域 20c :通道區域 25 :薄膜電晶體 -14-W content in MoW film (atJ 〇 etch rate (in / sec) resistivity (μ Ω cm) 0 (Pure Mo) 74.9 11.1 6.0 36.5 η.6 11.4 18.0 11.8 16.7 11.0 12.6 21.9 5.2 12.9 25.0 1.9 13.7 37.0 0 15.6 100 (Pure W) 0 16.6 The Ar pressure at the time of sputtering each MoW target was 0.3 Pa, the glass substrate temperature was 10 ° C, and the thickness of the formed MoW film was 300 nm. Fig. 3 and Fig. 4 The graph of the measurement results of Table 1, the third graph shows the relationship between the W content and the resistivity, and the fourth graph shows the relationship between the W content and the etching rate. Since the etching rate is above 30 A/sec. It is difficult to control the wiring shape, and the etching time is less than 5 A/sec. Therefore, according to Table 1, Figure 3, and Figure 4, the W content (in the Mow film, the total of Mo atoms and W atoms) The number of W atoms in the number is 8 at% or more and less than 20.0 at% is suitable for the present invention, and particularly in the range of 11.4 at% or more and 16.7 at% or less, the most suitable etching rate can be obtained. Compared with the MoW film. Is a W film of l〇〇at%, if the MoW film is in the range of the W content, the resistivity will be sufficient Further, since the MoW film has a high melting point, after the gate electrode layer 18 -13 - 201234496 is formed, the dopant is ion-implanted, and the dopant is activated by heating to form the source region 20s and In the drain region 20d», it can be seen that the MoW film can also be used for a film transistor that operates at a high speed. Further, each of the MoW films having a W content of 0% to 100% formed is 675 in an N2 gas atmosphere. After the heat treatment for 1 hour at ° C, no protrusion was observed in each MoW film by microscopic observation. [Simplified illustration] [Fig. 1] (a) to (g): for explaining the present invention [Fig. 2] (a) to (e): a diagram following the first graph. [Fig. 3] is a graph showing the relationship between the W content and the resistivity. 4] shows a graph showing the relationship between the W content rate and the etching rate. [Main component symbol description] 13: Semiconductor layer 1 5: Gate insulating layer 16: Molybdenum tungsten film 18: Gate electrode layer 2 0d : 汲Polar region 20s: source region 20c: channel region 25: thin film transistor-14-