TW201233279A - Copper or palladium-copper wire package process and structure thereof - Google Patents

Copper or palladium-copper wire package process and structure thereof Download PDF

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Publication number
TW201233279A
TW201233279A TW100102660A TW100102660A TW201233279A TW 201233279 A TW201233279 A TW 201233279A TW 100102660 A TW100102660 A TW 100102660A TW 100102660 A TW100102660 A TW 100102660A TW 201233279 A TW201233279 A TW 201233279A
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Taiwan
Prior art keywords
palladium
layer
copper wire
pad
copper
Prior art date
Application number
TW100102660A
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Chinese (zh)
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TWI409014B (en
Inventor
Cai-Tong Guo
Kun-Zheng Liu
Ying-Jie Li
guo-bin Qiu
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Taiwan Uyemura Co Ltd
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=47069855&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW201233279(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Taiwan Uyemura Co Ltd filed Critical Taiwan Uyemura Co Ltd
Priority to TW100102660A priority Critical patent/TW201233279A/en
Priority to CN2011101925171A priority patent/CN102605359A/en
Priority to JP2011229483A priority patent/JP2012153974A/en
Priority to US13/326,370 priority patent/US20120186852A1/en
Priority to KR1020120005470A priority patent/KR20120086253A/en
Publication of TW201233279A publication Critical patent/TW201233279A/en
Application granted granted Critical
Publication of TWI409014B publication Critical patent/TWI409014B/zh

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

The present invention provides a copper wire or palladium-copper wire package process and structure thereof. The structure includes a solder pad; a palladium coating layer on the solder pad; a gold coating layer on the palladium coating layer; and a wire bonding coupled to the copper wire or palladium-copper wire on the gold plating. The present invention use thicker palladium plating to replace the use of a conventional nickel layer, to increase the wire binding strength between the copper or palladium-copper wires and the solder pad.

Description

201233279 六、發明說明： 【發明所屬之技術領域】 特別是指-軸線或細線的 本發明係有關一種封裝製程及其結構 封裝製程及其結構。 【先前技術】201233279 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates in particular to an axis or a thin wire. The present invention relates to a packaging process and a structure thereof, a packaging process and a structure thereof. [Prior Art]

^圓、麵示瞻'嶋板郁板、^板與印刷電路板 子工業零件的封裝製程上，需於構成電性連接的焊塾表面上形成一化 錄金層，以提升打線與雜掷接上的接合性與耐難。但在焊塾上形成 鎳層後進彳刺謝爾刪，繼輪刪中所析 出粒子的粒界部分進行難的選擇性攻擊，導致金層下方形賴缺部分而 產生敍孔，姉的鎳層·的脆弱，在焊接時將無法確保充 強度。 顿设口 因此，新的化錦把金製程被提出，以藉她層來解決金對錦強烈攻擊 現象，化_金製程雜可啸決上制題，但顧的存在卻導致硬度增 加，使得後續無法順利打線接合銅線或者銅鈀線。 有鑑於此，本發明遂針對上述習知技術之缺失，提出—種勒新的銅線 或把銅線的封裝製程及其結構，以有效克服上叙該等問題。 【發明内容】 本發明之主要目的在提供一種銅線或纪銅線的封褒製程及其纟士構 無使用鎳層，能提升銅線或銅I巴線與焊墊的接合可靠度，並可減低成本、 本發明之另一目的在提供一種銅線或鈀銅線的封裝製程及其結構其 能應用於較為低階但線路密集度高之電子產品封裝製程上。 201233279 本發明之另一目的在提供銅線或鈀銅線封裝製程產品一種可作業之新 表面處理。 為達上述之目的’本發明提供一種銅線或鈀銅線的封裝結構，其包含 有一焊墊；一位於焊墊上的鈀鍍層；一位於鈀鍍層上的金鍍層；以及一打 線接合於金鑛層上的銅線或把銅線。 本發明尚提供一種銅線或鈀銅線的封裝製程，其步驟包含有先提供一 焊墊；接續，於焊墊上形成一鈀鍍層；然後，於鈀鍍層上形成一金鍍層； 最後’於金鑛層上打線接合一銅線或把銅線。 其中，上述之鈀鍍層可以是利用置換反應、或者置換反應與還原反應 二階段來形成，或者是使用單一藥水，同步進行置換與還原反應所形成。 底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術内 谷、特點及其所達成之功效。 【實施方式】 首先，請參閱第1圖，其係本發明之銅線或鈀銅線的封裝結構示意圖。 如圖所示，本創作之銅線或鈀銅線的封裝結構10，包含有一焊墊12，其材 質可以為銅；一位於焊墊12上且緊鄰焊墊12之鈀鍍層14; 一位於鈀鍍層 14上且緊鄰鈀鍍層14之金鍍層16 ;以及一接合於金鍍層16上以與焊墊 12形成電性連接之銅線18或者把銅線。 上述之把鑛層14的厚度為〇.〇3〜〇.2微米，金鍍層16之厚度為〇.〇3〜 〇·2微米。 在製程上，本發明係於欲進行銅線或銅鈀線封裝製程之焊墊12表面先 進行表面處理’以直接在焊墊12表面依序形成—緻密性高的域層14與 201233279 -金錢層i6 ’以在無使用錄層的情況下’増加接合於金鑛層i6上之銅線 18或銅鈀線的打線接合強度。 本發明在形成織層14與金鍵層16時的操作溫度大騎在坑〜％ °C，酸鹼值都是在ph4〜9之間。 - 上述之鈀鍍層14是利用電化學反應所形成。鈀鍍層Μ可以是純鈀鍍 層或者是鈀磷合金鍍層。本發明之銅線18或鈀銅線的封裝製程可依照把鍵 層14的形成方式進一步區分為下列三種： 鲁請參閱第2圖’其係第-種方法的步驟流程圖。首先如步驟Sl所述， 提供一焊墊12。接續，如步驟S2所述，先進行置換反應於焊墊12表面形 成一置換型鈀鍍層141。再如步驟S3所述，以還原反應增厚形成一位於置 換型#巴鍍層141上之還原型把鑛層142。然後，如步驟S4所述，以置換型 或還原型或半置換半還原型反應形成一覆蓋於還原型鈀鍍層14上之金鍍層 16。最後，如步驟S5所述，於焊墊10上之金鍍層16打線接合一銅線18 或把銅線，形成如第3圖所示之結構。 ® 在此方式下，鈀鍍層14是由一置換型鈀鍍層141與還原型鈀鍍層142 所組合而成。 請參閱第4圖，其係第二種方法的步驟流程圖。首先，如步驟su所 述，提供一焊墊12。接續，如步驟S12所述，利用一道藥水來進行作業， 此藥水兼具觸媒鈀與化學鈀效用，因此，可同時進行置換及還原反應來於 焊墊12上形成鈀鍍層14。如步驟S13所述，再以置換型或還原型或半置換 半還原型反應於鈀鍍層14上形成一金鍍層16。最後，如步驟Sl4所述，於 焊墊12之金鍍層16上打線接合一銅線18或鈀銅線，形成如第丨圖所示之 201233279 結構。 請參閱第5圖，其係第三種方法的步驟流裎圖。首先如步驟S21所述， 提供一焊墊12。接續，如步驟S22所述，先進行置換反應於焊墊12表面形 成一置換型鈀鍍層141。再如步驟幻〗所述，以置換型或還原型或半置換半 還原型反應形成一覆蓋於置換型鈀鍍層141上之金锻層16。最後，如步驟 S24所述，於焊塾1〇之金鍍層16上打線接合一銅線π或把銅線，形成如 第6圖所示之結構。 本發明藉由強化鈀鍍層的緻密性，來取代鎳層的存在，以避免鎳存在 時所產生的各種問題，提供銅線或者銅纪線封裝製程產品一種可作業的新 表面處理。再者，本發明之技術時的最佳施行範例是應用於較為低階但線 路密集度鬲之電子產品封裝製程上。因為低階電子產品所需的迴銲次數較 低’因此銅原子的移純少’並不會大财賴散魏顯内。再者，當 元件整體體積縮小且線路密集度高時，焊墊體積也會縮小，而本發明無使 用鎳層的特性上，有利於銅焊墊與銅線或她線的打線，不僅不會影響可 靠度，更可減低成本。 唯以上所述者’僅林㈣讀佳倾_已，並_來蚊本發明 貫施之範@。故即凡依本發日种請範騎述之特徵及精神所為之均等變化 或修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 第1圓係本發明之銅線或鈀銅線的封裝結構的示意圖。 第2圖是本㈣之銅線或__織製程㈣—種製作步驟流程圖。 第3圓是第2圖之步驟所製得之銅線錢銅_封裝結構示意圖。 201233279 第4圖係本發明之銅線雜銅線麟裝製程的第二觀作步驟流程圖 第5圖是本發明之銅線或鈀銅線的封裝製程的第三種製作步驟流程圖 第6圖是第5圖之步驟所製得之銅線或鈀銅線的封裝結構示意圖。 【主要元件符號說明】 10 封裝結構 12 焊塾 14 鈀鍍層 141置換型鈀鍍層 142還原型鈀鍍層 16 金鍍層 18 鋼線^In the packaging process of the industrial parts of the slabs, the slabs and the printed circuit boards, a gold layer is formed on the surface of the solder joints that constitute the electrical connections to enhance the wire bonding and the miscellaneous throwing. Bonding and durability. However, after the formation of the nickel layer on the soldering iron, the spurs are removed, and the grain boundary portion of the particles precipitated in the subsequent rounds is subjected to a difficult selective attack, resulting in the underlying part of the gold layer being deviated to form a hole, and the nickel layer of the crucible · The fragility will not ensure the filling strength during welding. Therefore, the new Huajin puts the gold process on the way to solve the strong attack of Jin Jinjin by her layer, and the _ gold process can be used to make the problem, but the existence of Gu leads to an increase in hardness, which makes Subsequent failure to wire the copper wire or copper palladium wire. In view of the above, the present invention has been directed to the lack of the above-mentioned prior art, and proposes a new copper wire or a copper wire packaging process and its structure to effectively overcome the above problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide a copper wire or copper wire sealing process and a gentleman structure without using a nickel layer, which can improve the bonding reliability of the copper wire or copper I bar wire and the bonding pad, and Another object of the present invention is to provide a copper wire or palladium copper wire packaging process and structure thereof that can be applied to a relatively low-order but high-dense electronic product packaging process. 201233279 Another object of the present invention is to provide a new operational surface treatment for copper wire or palladium copper wire package process products. For the above purposes, the present invention provides a copper wire or palladium copper wire package structure comprising a pad; a palladium plating layer on the pad; a gold plating layer on the palladium plating layer; and a bonding line bonding to the gold ore Copper wire on the layer or copper wire. The invention further provides a copper or palladium copper wire packaging process, the method comprising the steps of: first providing a solder pad; connecting, forming a palladium plating layer on the solder pad; and then forming a gold plating layer on the palladium plating layer; Wire the copper wire or copper wire on the seam. Here, the palladium plating layer may be formed by a substitution reaction, a substitution reaction or a reduction reaction in two stages, or a single syrup may be used, and a substitution and a reduction reaction may be simultaneously performed. The details of the present invention, the characteristics of the technology, the characteristics, and the effects achieved by the present invention will be more readily understood by the detailed description of the specific embodiments. [Embodiment] First, referring to Fig. 1, a schematic diagram of a package structure of a copper wire or a palladium copper wire of the present invention. As shown in the figure, the copper or palladium copper wire package structure 10 of the present invention comprises a solder pad 12 which may be made of copper; a palladium plating layer 14 on the pad 12 adjacent to the pad 12; A gold plating layer 16 on the plating layer 14 and adjacent to the palladium plating layer 14; and a copper wire 18 or copper wire bonded to the gold plating layer 16 to form an electrical connection with the pad 12. The thickness of the above-mentioned ore layer 14 is 〇.〇3~〇.2 μm, and the thickness of the gold plating layer 16 is 〇.〇3~ 〇·2 μm. In the process, the present invention is to perform surface treatment on the surface of the pad 12 for the copper wire or copper palladium wire packaging process to form directly on the surface of the pad 12 - the dense layer layer 14 and 201233279 - money The layer i6' is used to join the bonding strength of the copper wire 18 or the copper palladium wire bonded to the gold ore layer i6 without using a recording layer. The operating temperature of the present invention when forming the woven layer 14 and the gold bond layer 16 is large in the pit ~% ° C, and the pH is between ph 4 and 9. - The palladium plating layer 14 described above is formed by an electrochemical reaction. The palladium plating layer may be a pure palladium plating layer or a palladium phosphorus alloy plating layer. The packaging process of the copper wire 18 or the palladium copper wire of the present invention can be further divided into the following three types according to the manner in which the key layer 14 is formed: Refer to Fig. 2, which is a flow chart of the steps of the first method. First, as described in step S1, a pad 12 is provided. Subsequently, as described in step S2, a displacement reaction is first performed on the surface of the pad 12 to form a replacement palladium plating layer 141. Further, as described in step S3, a reduction type ore layer 142 on the replacement type #bar plating layer 141 is formed by thickening by a reduction reaction. Then, as described in step S4, a gold plating layer 16 covering the reduced palladium plating layer 14 is formed by a substitution type or a reduction type or a semi-replacement semi-reduction type reaction. Finally, as described in step S5, the gold plating layer 16 on the pad 10 is wire bonded to a copper wire 18 or a copper wire to form a structure as shown in FIG. In this manner, the palladium plating layer 14 is composed of a replacement type palladium plating layer 141 and a reduced type palladium plating layer 142. Please refer to FIG. 4, which is a flow chart of the steps of the second method. First, as described in step su, a pad 12 is provided. Next, as described in step S12, the syrup is used in combination with a catalyst palladium and a chemical palladium. Therefore, the palladium plating layer 14 can be formed on the pad 12 by simultaneous replacement and reduction reactions. As described in step S13, a gold plating layer 16 is formed on the palladium plating layer 14 by a substitutional or reduced or semi-replacement semi-reduction type reaction. Finally, as described in step S14, a copper wire 18 or a palladium copper wire is wire bonded to the gold plating layer 16 of the pad 12 to form a 201233279 structure as shown in the first drawing. Please refer to Figure 5, which is a flow diagram of the third method. First, as described in step S21, a pad 12 is provided. Subsequently, as described in step S22, a displacement reaction is first performed on the surface of the pad 12 to form a replacement palladium plating layer 141. Further, as described in the step, a gold-forged layer 16 overlying the displacement-type palladium plating layer 141 is formed by a displacement or reduction or semi-replacement semi-reduction reaction. Finally, as described in step S24, a copper wire π or a copper wire is bonded to the gold plating layer 16 of the solder bump 1 to form a structure as shown in Fig. 6. The present invention provides a new surface treatment for copper wire or copper wire packaging process products by enhancing the compactness of the palladium plating layer instead of the presence of the nickel layer to avoid various problems in the presence of nickel. Furthermore, the preferred embodiment of the technique of the present invention is applied to a relatively low-order but line-intensive electronic product packaging process. Because the number of reflows required for lower-order electronic products is lower, so the transfer of copper atoms is less pure, and it will not be too much. Moreover, when the overall volume of the component is reduced and the line density is high, the pad volume is also reduced, and the invention does not use the nickel layer to facilitate the bonding of the copper pad to the copper wire or the wire, not only Affecting reliability and reducing costs. Only the above mentioned 'only Lin (four) read the best _ has, and _ mosquitoes invented the invention. Therefore, any change or modification of the characteristics and spirit of Fan Chi, which is based on the date of this issue, should be included in the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first circular system is a schematic view of a package structure of a copper wire or a palladium copper wire of the present invention. Figure 2 is a flow chart of the production steps of the copper wire of this (4) or the __ weaving process (4). The third circle is a schematic diagram of the copper wire copper_package structure obtained by the steps of FIG. 201233279 FIG. 4 is a second process step of the copper wire copper clad process of the present invention. FIG. 5 is a third process flow chart of the copper wire or palladium copper wire package process of the present invention. The figure is a schematic diagram of the package structure of the copper wire or the palladium copper wire obtained by the step of FIG. [Main component symbol description] 10 Package structure 12 Solder pad 14 Palladium plating 141 Displacement palladium plating 142 Reduced palladium plating 16 Gold plating 18 Steel wire

Claims (1)

201233279 七、申請專利範圍： 1. 一種銅線或鈀銅線的封裝結構，其包含有： 一焊墊； 一鈀鍍層，其係位於該焊墊上； 一金鍍層，其係位於該鈀鍍層上；以及 -銅線或鈀銅線，其係打線接合於該金鍍層上。 2. 如申請專利範圍第丨項所述之封裝結構，其中該焊塾之材質為銅，馳 鑛層之材質為純把或者是纪碟合金。 3. 如申4專地圍第1顿述之封裝結構，其巾她麟包含有—置換型 纪鑛層與一還原型把鑛層。 4. 如申請專利範圍第i項所述之封裝結構，其中該姆層之厚度為_〜 0.2微米’該金鍍層之厚度為〇 〇3〜〇 2微米。 5. —種銅線或鈀銅線的封裝製程方法，其包含有下列步驟： 提供一焊墊； 於該焊塾上形成一把鑛層； 於该把鑛層上形成一金鑛層；以及 於該金鍍層上打線接合一銅線或鈀銅線。 6.如申請專利範M 5項所述之方法，其中於該焊墊上形成該靖層的步 驟更包含有： 利用置換反應於該焊墊上先形成一置換型飽鍵層；以及 利用還原反應於該置換型鈀鍍層上形成一還原型鈀錢層。 7·如申請專利第5項所述之方法’其中該焊墊之㈣為鋼，該靖層 201233279 之材質為純鈀或者是鈀磷合金。 如申凊專利範圍第5項所述之方法其帽成該麵鑛層與該金鐘層之操 作溫度為25eC〜95°C，酸鹼值為沖4〜9。 如申凊專利範圍第5項所述之方法，其中該鈀鍍層之厚度為〇〇3〜〇.2 微米，該金鍍層之厚度為〇.〇3〜0.2微米。 〇’如申請專利範圍第5項所述之方法，其中於該焊墊上形成該鈀鍍層的步 驟是使用一兼具觸媒鈀與化學鈀效用之藥水來同時進行置換與還原反應 所形成。 U·如申請專鄕圍第5項騎之方法，其巾該金鍍層是_置換型、還原 型或者半置換半還原型反應所形成。 12,如申請專利範圍第5項所述之方法，其中於該焊墊上形成該顿層的步 驟是使用置換反應所形成。201233279 VII. Patent application scope: 1. A copper wire or palladium copper wire package structure, comprising: a solder pad; a palladium plating layer on the solder pad; a gold plating layer on the palladium plating layer And a copper wire or a palladium copper wire bonded to the gold plating. 2. The package structure as claimed in claim 2, wherein the material of the soldering iron is copper, and the material of the ore layer is pure or a disc alloy. 3. For example, Shen 4 specializes in the encapsulation structure of the first dynasty, and her lining contains a replacement type mineral layer and a reduced type mineral layer. 4. The package structure of claim i, wherein the thickness of the layer is _~0.2 microns. The thickness of the gold layer is 〇3~〇 2 microns. 5. A method of encapsulating a copper wire or a palladium copper wire, comprising the steps of: providing a pad; forming a layer of a deposit on the pad; forming a gold layer on the layer; A copper wire or a palladium copper wire is wire bonded to the gold plating. 6. The method of claim 5, wherein the step of forming the layer on the pad further comprises: forming a replacement type saturated bond layer on the pad by using a displacement reaction; and utilizing a reduction reaction A reduced palladium layer is formed on the displacement type palladium plating layer. 7. The method of claim 5, wherein the (4) of the bonding pad is steel, and the material of the layer 201233279 is pure palladium or a palladium phosphorus alloy. The method according to claim 5, wherein the operation temperature of the face layer and the lapis lamina is 25 eC to 95 ° C, and the acid-base value is rush 4 to 9. The method of claim 5, wherein the palladium plating layer has a thickness of 〇〇3 to 〇.2 μm, and the gold plating layer has a thickness of 〇.〇3 to 0.2 μm. The method of claim 5, wherein the step of forming the palladium plating layer on the bonding pad is performed by simultaneously performing a substitution and reduction reaction using a syrup having a catalytic palladium and a chemical palladium effect. U. If you apply for the 5th riding method, the gold plating is formed by a displacement, reduction or semi-replacement semi-reduction reaction. 12. The method of claim 5, wherein the step of forming the layer on the pad is formed using a displacement reaction.
TW100102660A 2011-01-25 2011-01-25 Copper or palladium-copper wire package process and structure thereof TW201233279A (en)

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TW100102660A TW201233279A (en) 2011-01-25 2011-01-25 Copper or palladium-copper wire package process and structure thereof
CN2011101925171A CN102605359A (en) 2011-01-25 2011-06-28 Chemical palladium-gold plated film structure and manufacturing method thereof, copper wire or palladium-gold plated film packaging structure jointed by palladium-copper wire and packaging process thereof
JP2011229483A JP2012153974A (en) 2011-01-25 2011-10-19 Chemical palladium/gold plating film structure, method for production thereof, palladium/gold plating film package structure bonded with copper wire or palladium/copper wire, and packaging process thereof
US13/326,370 US20120186852A1 (en) 2011-01-25 2011-12-15 Structure of electrolessly palladium and gold plated films and process for making the same, assembled structure of palladium and gold plated films bonded with copper or copper-palladium wire and assembling process therefore
KR1020120005470A KR20120086253A (en) 2011-01-25 2012-01-18 Structure of electrolessly palladium and gold plated films and Process for making the same, Assembled structure of palladium and gold plated films bonded with copper or copper-palladium wire and Assembling process therefor

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JP5297083B2 (en) * 2007-07-17 2013-09-25 新光電気工業株式会社 Solder bump formation method

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