501253 A7501253 A7
發明領域： 本發明係有關於第㈣搬號專射請案之積體電路 封裝用基減構及其製造方法之追加…係有關於—種積體 電路封裝肖基板其製造綠，翻是有關—種細背膠銅箱 於製作起薄之基板，並可簡化製程複雜度，省略塞孔步驟之 基板製造方法。 " 發明背景： 第891246〇i號專利申請案係有關於一種積體電路封裝用 基板結構及其製it方法，對職基板之散紐及電性品質均 月b大幅提昇，不須作習知塞孔步驟，消弭習知超薄板製程上 之困擾以及塞孔可靠朗題，尤其是顧改善習知製造超薄 板之缺失。 圖一 A〜C所示係習知技術之積體電路封裝用基板之製 程步驟包括： (a)提供一絕緣基板1〇，並以鑽孔或雷射方式在該基板1〇 表面形成複數個導通孔15，接著對上述導通孔15進行 鑛導通孔及上下側表面電鍍上一層面銅2〇，25。 ⑻對上、下側表面之面銅2〇，2S進行電路兹刻以形成上、 下電路層20a，25a，其中上、下電路層2〇a，25a之間 係藉由上述導通孔15做為導通之橋樑，並以絕緣樹脂 3〇 (或導電膠）30對上述導通孔15進行塞孔，以形成 導通孔結構15a。 (Ο隶後再將綠漆35覆蓋於基板1〇之上、下電路層2〇a， (請先閱讀背面之注意事項再填寫本頁)Field of the Invention: The present invention relates to the structure reduction of integrated circuit packaging and the manufacturing method of the No. 2 special shooting application. It is related to a kind of integrated circuit packaging Xiao substrate, its manufacturing is green, it is related — A thin-adhesive copper box is used to make a thin substrate, which can simplify the complexity of the process and omit the step of plugging the substrate. " Background of the Invention: Patent application No. 891246〇i relates to a substrate structure for integrated circuit packaging and a method for manufacturing the same, which significantly improves the quality of the substrate and the electrical quality of the substrate, without the need for practice. Knowing the plugging step eliminates the problems of the conventional ultra-thin plate manufacturing process and the reliable problem of plugging holes, especially the lack of improving the conventional manufacturing of ultra-thin plates. The process steps of a conventional integrated circuit packaging substrate shown in FIGS. A to C include: (a) An insulating substrate 10 is provided, and a plurality of surfaces are formed on the surface of the substrate 10 by drilling or lasering. The vias 15 are followed by ore vias and electroplating a layer of copper 20, 25 on the upper and lower surfaces of the vias 15.电路 Carry out circuit engraving on the upper and lower surface copper 20, 2S to form upper and lower circuit layers 20a, 25a, wherein the upper and lower circuit layers 20a, 25a are made through the above-mentioned vias 15 Is a conductive bridge, and the above-mentioned via 15 is plugged with an insulating resin 30 (or conductive adhesive) 30 to form a via structure 15a. (After that, cover the green paint 35 on the substrate 10 and the lower circuit layer 20a. (Please read the precautions on the back before filling this page)
經濟部智慧財產局員工消費合作社印製 2 501253 A7 五、發明說明（> ) 心表面，並裸露部份如作騎線塾及 墊區域（圖中未標示）。 注 以上所述係為習知技術之積體電路封裝縣板之製程， 然母案（專利申請案號·246〇2)利用互相產合之一核心絕 緣層與-銅材’-銅絲材侧絲植個導體柱後盘 -核__互_合’再於雜錢緣層翻絲材之 側表面形成上、下電路層，並以複數個導體柱導通該上、下 電路層，參照圖二A至二D，其步驟如下： (a)提供-銅箱基材200 ’定義出複數個導體柱21〇，接著 將一核心絕緣層220與該銅箔基材2〇〇作壓合，壓合 後導體柱210 —端埋在該核心絕緣層22〇内； ⑻以雷射開啟各該_柱21〇上方之核心絕緣層22〇，形 成複數個盲孔230 ; (Ο以電鍍銅方式鑛滿各該盲孔，形成—實心盲孔結構 230a，並於核心絕緣層22〇之外側表面鍍上一層面銅 240 ； (d)蝕刻定義出上、下電路層24〇a、2〇〇a，最後在該上、 下電路層240a、200a分別覆蓋上一層電路保護層25〇， 作為線路保護層，並露出欲作為打線墊及錫球墊區 域所述打線塾及錫球塾之區域係可部份或全部置於 該導體柱210上方，並在打線墊及錫球墊區鍍上一鎳/ 金（Ni/Au)層（圖中未示）。另外，亦可於二電路層 24〇a，200a分別覆上一層電路保護層250之後，露出欲 作為與晶片錫接之銲墊及錫球墊之區域（圖中未示）， 巧張尺錢时_家標^(S)A4規格⑵〇: 297公釐） 丄厶 A7 發明說明（）） 使該基板可供覆晶封H切裝晶片。 ’特提出"~彻詩銅箱壓 ί:Γ=術’在背膠鋼箱及-銅纖間完成電路層 ==膠嶋包含—絕緣層及-銅_成， -銅’且絲作更超薄技板，且同樣地，利用 均能大^料體枉’對封裝基板之散熱性及電性品質 發明之簡要說明： 止本發明之主要目的在於提供一種積體電路封裝用基板製 ^方^之追加—’ 背膠_及-銅絲材中完成電路 層之V通’可大幅簡化製程步驟，且能製作更超薄之半導體 封裝基板，使產品達到更高可靠度。 為了達到上述目的；本發明係提供一種積體電路封裝用 基板製造方法之追加―，其步驟包括： U)提供-銅材，於該編紐之上表面並定義出複數 個導體柱； (b) 提供—轉輔，該獅鋪具有職層面與銅猪層 面，將該絕緣層面與該銅箔基材之上表面作壓合，使各 該導體柱一端埋在該絕緣層内； (c) 移除各該導體柱上方背膠銅箔之部分銅箔層，使其形成 複數個與該導體柱相通之盲孔結構（blindv-ia); (d) 以電鍍銅方式鍍滿各該盲孔； (e) 圖案化該銅箔層及銅箔基材之下表面，以定義出上、下 (請先閱讀背面之注意事項再填寫本頁)Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 501253 A7 V. Description of the invention (>) The surface of the heart, and the exposed parts such as the riding cymbals and pad areas (not shown in the figure). Note that the above is the manufacturing process of integrated circuit packaging county boards of conventional technology. However, the parent case (patent application number: 2460) uses a core insulation layer and -copper'-copper wire that are mutually produced. Side wires are planted with a conductor post back core-core__mutual_combined, and then the upper and lower circuit layers are formed on the side surface of the miscellaneous edge layer turning wire material, and the upper and lower circuit layers are conducted by a plurality of conductor posts. 2A to 2D, the steps are as follows: (a) Provide-a copper box substrate 200 'defines a plurality of conductor pillars 21, and then a core insulation layer 220 and the copper foil substrate 200 are laminated together. The end of the conductor post 210 after compression is buried in the core insulation layer 22; ⑻Open the core insulation layer 22 above each of the pillars 20 with a laser to form a plurality of blind holes 230; (0 with electroplated copper The method is to fill each of the blind holes to form a solid blind hole structure 230a, and plate a layer of copper 240 on the outer surface of the core insulation layer 22o; (d) Etching defines the upper and lower circuit layers 24a, 2o. 〇a, and finally cover the upper and lower circuit layers 240a, 200a with a circuit protection layer 25, respectively, as a circuit protection layer, and expose the desired The areas of the bonding pads and solder ball pads for the bonding pads and solder ball pad areas can be partially or completely placed above the conductor post 210, and a nickel / gold (Ni / Au) layer (not shown). In addition, after the two circuit layers 24a and 200a are respectively covered with a circuit protection layer 250, the areas to be used as solder pads and solder ball pads for soldering to the wafer are exposed ( (Not shown in the figure), Qiaoqianqianqian_Jiaobiao ^ (S) A4 specification (⑵: 297 mm) 丄 厶 A7 Description of the invention ()) Make the substrate available for flip chip sealing and cutting wafers. 'Specially proposed " ~ Cross Poetry Copper Box Pressing: Γ = 术' Complete the circuit layer between the backed steel box and -copper fiber == rubber contains -insulation layer and -copper_ 成, -copper ' A more ultra-thin technology board, and similarly, the heat dissipation and electrical quality of the package substrate can be greatly improved by using the material body. The main purpose of the present invention is to provide a substrate for integrated circuit packaging. ^ Fang ^ 's addition—'backing adhesive_ and-V-pass to complete the circuit layer in copper wire' can greatly simplify the process steps, and can produce ultra-thin semiconductor packaging substrates, making the product achieve higher reliability. In order to achieve the above object, the present invention provides an addition to a method for manufacturing a substrate for integrated circuit packaging, the steps of which include: U) providing-a copper material, and defining a plurality of conductor posts on the upper surface of the button; (b ) Provide-transfer assistance, the lion shop has a job level and a copper pig level, and the insulation layer is pressed against the upper surface of the copper foil substrate so that one end of each of the conductor posts is buried in the insulation layer; (c) Remove a portion of the copper foil layer of the adhesive-backed copper foil above each of the conductor posts to form a plurality of blind hole structures (blindv-ia) communicating with the conductor posts; (d) plating each of the blind holes by electroplating copper ; (E) pattern the copper foil layer and the lower surface of the copper foil substrate to define the top and bottom (please read the precautions on the back before filling this page)
H 1 n n n n n 一一^i I I I I n 1· I I 經濟部智慧財產局員工消費合作社印製 501253H 1 n n n n n one by one ^ i I I I I n 1 · I I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 501253
五、發明說明（ 電路層； (f)在该上、下電路層分別覆蓋上一層電路保護層，移除部 分電路保護層以作為打線墊及錫球塾之區域，並於該區 域鍍上一鎳/金（Ni/Au)層。 較隹者’可只對各該盲孔以電鍍銅方式鍍上一層面銅。 較佳者，以電鍍銅方式鑛上一層面銅於各該盲孔之後， 可在所述絕緣層欲作為晶片置放區下方之複數個盲孔，形成 上複數個銲錫凸塊（Bump)。 為了使貴審查委員對本發明之目的、特徵及功效，有 更進一步的瞭解與認同，茲配合圖式詳加說明如后： 圖式之簡單說明： 圖一 A〜一 c係習知積體電路封裝用基板之製程示意 圖 圖二A, 圖 D係母案積體電路封裝用基板之製程示意 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 圖三A〜三F係本發明第一實施例積體電路封裝用基板 製程不意圖。 圖四A〜四F係本發明第二實施例積體電路封裝用基板 製程示意圖。 圖五A〜五F係本發明第三實施例積體電路封裝用基板 製程示意圖。 „ ^紙張尺度綱t關家辟（CNS)A4娜（21〇 x^97^i7 -I n I ! I I n — — — — — — n I · - (請先閱讀背面之注意事項再填寫本頁) 501253 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（f) 圖式中之圖號說明· 10-基板 15-導通孔 15a-導通孔結構 230, 330, 430, 530-盲孔 230a, 330a，430a，530a-盲孔結構 20, 25, 240, 440, 540-面銅 30-絕緣樹脂 35-綠漆< 20a, 240a，3202a，4202a，5202a-上電路層 25a，200a, 300a，400a，500a-下電路層 200, 300, 400, 500-銅箔基材 210, 310, 410, 510-導體柱 220-核心絕緣層 250,350,450,550-保護層 320, 420, 520-背膠銅箔 360, 460, 560-打線墊 370, 470, 570-錫球墊 580-銲錫凸塊 3201,4201,5201-絕緣層 3202, 4202, 5202_ 銅猪層 詳細說明： 本發明積體電路封裝用基板結構及其製造方法之追加一 〈請先閱讀背面之注意事項再填寫本頁) ·# 訂---------線 Φ! 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 五、發明說明（t ) 二口、個實施例來闡述，請參閱下述說明。 弟一實施例V. Description of the invention (Circuit layer; (f) Cover the upper and lower circuit layers with a circuit protection layer, remove part of the circuit protection layer to serve as the area for wire bonding pads and solder bumps, and plate one on the area. Nickel / gold (Ni / Au) layer. The competitor can only plate one layer of copper by electroplating copper for each of the blind holes. Preferably, a layer of copper is mined by electroplating copper after each of the blind holes. To form a plurality of solder bumps on the insulating layer to be used as a plurality of blind holes below the chip placement area. In order to make your reviewer have a better understanding of the purpose, features and effects of the present invention I agree with the drawings in detail as follows: Brief description of the drawings: Figures 1 ~ 1c are schematic diagrams of the conventional integrated circuit packaging substrate manufacturing process. Figure 2A and Figure D are mother package integrated circuit packages. The manufacturing process of the substrate is used to indicate that the printing of the printed circuit board of the Intellectual Property Bureau employee consumer cooperative of the Ministry of Economic Affairs is not intended. The manufacturing process of the integrated circuit packaging substrate of the first embodiment of the present invention is not intended. Example integrated circuit package Schematic diagram of the substrate manufacturing process. Figures 5A to 5F are schematic diagrams of the substrate manufacturing process for integrated circuit packaging according to the third embodiment of the present invention. ^ ^ Paper size outline t Guan Jia Pi (CNS) A4 Na (21〇x ^ 97 ^ i7 -I n I! II n — — — — — — n I ·-(Please read the notes on the back before filling out this page) 501253 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Description of the drawing number10- substrate 15-via 15a-via structure 230, 330, 430, 530-blind hole 230a, 330a, 430a, 530a-blind hole structure 20, 25, 240, 440, 540-surface Copper 30-Insulating resin 35-Green paint < 20a, 240a, 3202a, 4202a, 5202a- Upper circuit layer 25a, 200a, 300a, 400a, 500a- Lower circuit layer 200, 300, 400, 500- Copper foil substrate 210 , 310, 410, 510-conductor pillar 220-core insulation layer 250, 350, 450, 550-protective layer 320, 420, 520-adhesive copper foil 360, 460, 560-wire pad 370, 470, 570- solder ball pad 580- solder bump 3201,4201,5201-Insulating layer 3202, 4202, 5202_ Copper pig layer Detailed description: The substrate structure for integrated circuit packaging and its manufacturing method of the present invention are added. Note on the back, please fill in this page again) · # Order --------- Line Φ! This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) A7 B7 V. Description of the invention ( t) Two mouths, examples to explain, please refer to the following description. Brother one example
明參閱圖：A 嫠一 二所示，本發明積體電路封裝用基板 第實，例之製程步驟包括： j泊基材300，以兹刻等方式定義出複數個導體 J ’接著以微蝕刻方式（Microetching)粗化導體柱310 表面以增強其接著性（圖中未示）； (b) 提供1膠銅㈣〇,該背膠鋪320係包含絕緣層通 與銅^層3202，將該絕緣層3201與該鋪基材3〇〇之上表 面作壓。’使各该導體牲細一端埋在絕緣層幻⑺内。其 中所1¾緣層32G1之材質係可為-具玻璃纖維之預浸材 (Prepreg)、j裒氧樹脂（印〇χγ_)或較厚之絕緣樹脂； (c) 以雷射開啟各該導體柱31〇上方之背膠銅箔32〇，形成 複數個盲孔330，並清除導體柱310面上之殘餘絕緣物質； (d) 以電鍍銅方式鍍滿各該盲孔33〇，形成一實心盲孔結構 330a ； (e) 蝕刻定義出上、下電路層3202a、300a ; (0最後，在該上、下電路層3202a、300a分別覆蓋上一層 電路保護層350，該保護層350可為防銲漆或絕緣樹脂，作 為線路保護層，並露出欲作為晶片封裝打線之打線墊360及 與電路板電性連接之錫球墊區域370，並在打線墊及錫球墊 區鍍上一鎳/金（Ni/Au)層。 、 另外，本實施例亦可在兩面電路層3202a、300a分別覆 蓋上一層電路保護層350之後，露出欲作為與晶片銲錫接之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) ,#·---訂.·丨------丨線» 經濟部智慧財產局員工消費合作社印製 期253 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（， 鲜墊（圖中4示)及锡球塾之區域37〇 層，使本實施_可供覆晶封裝方式封裝晶片獻金(馳u) 第二實施例 請參閱圖四A〜四F戶斤+，士 α 所不，本發明積體電路封裝用美柘 第二實_之製程步驟包括： —裒用基板 5提供-銅絲材400 ’以蚀刻等方式定義岀_轉體 柱410，亚以微侧方式粗化導體柱彻表面，以增強 著性（圖中未示）； 〃 ⑻提供一背翻箔42〇,該背膠_微係包含絕緣層傷 與銅箱層砸’將該絕緣層伽與該銅箱基材之上表 面作壓合’使各該導體㈣0 一魏在該絕緣層鑛内。 其中所述絕緣層4201之材質係可為一具玻璃纖維之預浸材 (ΡΓ，δ)、環氧樹脂（卿-)或較厚之絕緣樹脂； (〇以雷射開啟各該導·410上方之背軸_ 42〇，形成 複數個盲孔430 ’並清除導體柱41〇上面之殘餘絕緣物質； ⑷以電鍍銅方式對所盲孔43〇鑛上一層面銅44〇，形成一 盲孔結構430a; (e)兹刻定義出上、下電路層42〇2a、4〇〇a ; ⑴在該上、下電路層42G2a、4(X)a分職蓋上-層電路保 護層450，該保護層450可為防銲漆或絕緣樹脂，並露出欲 作為晶片封裝打線之打線墊46〇及與電路板電性連接之錫球 墊區域470，並在打線墊及錫球墊區鍍上一鎳/金（Ni/Au)層 (圖中未示）。 當然，如同第一實施例，本實施例亦可在兩面電路層 一 —_ 8 ^&尺度適用中國國家標準（CNS)A4 (請先閱讀背面之注意事項再填寫本頁) pRefer to the drawings: A and FIG. 12 show the first embodiment of the integrated circuit packaging substrate of the present invention. The process steps of the example include: a substrate 300, a plurality of conductors are defined in a manner such as engraving, and then micro-etching is performed. (Microetching) roughen the surface of the conductive post 310 to enhance its adhesion (not shown in the figure); (b) provide 1 glue of copper ㈣〇, the backing shop 320 includes an insulating layer and a copper layer 3202, and The insulating layer 3201 is pressed against the upper surface of the substrate 300. 'Each one end of each of the conductors is buried in an insulating layer. The material of the 1¾ edge layer 32G1 can be-prepreg with glass fiber (Prepreg), j 裒 oxy resin (printed 〇χγ_) or a thicker insulating resin; (c) each of the conductor posts is opened by a laser. The adhesive-backed copper foil 32 above 31 ° forms a plurality of blind holes 330 and removes any remaining insulating material on the surface of the conductor post 310; (d) each of the blind holes 3330 is plated by electroplating copper to form a solid blind Hole structure 330a; (e) Etching defines upper and lower circuit layers 3202a, 300a; (0 Finally, the upper and lower circuit layers 3202a, 300a are respectively covered with a circuit protection layer 350, and the protection layer 350 may be solder resist Lacquer or insulating resin, as the circuit protection layer, and exposes the wire pad 360 which is to be used for chip package wiring and the solder ball pad area 370 which is electrically connected to the circuit board, and is plated with nickel / gold on the wire pad and the solder ball pad area. (Ni / Au) layer. In addition, in this embodiment, after the two-sided circuit layers 3202a and 300a are covered with a circuit protection layer 350, respectively, the paper size to be used as the solder connection to the chip is exposed to the Chinese National Standard (CNS). A4 size (210 X 297 mm) (Please read the note on the back first (Please fill in this page if you want to pay attention), # · --- Order. · 丨 ------ 丨 line »Printing period of employee consumer cooperative of Intellectual Property Bureau of Ministry of Economic Affairs 253 3. Description of the invention (, fresh pad (shown in Figure 4) and the area of the solder ball 370 layers, so that this implementation _ can be used for chip-on-chip packaging package chip donation (Chi u) For a second embodiment, please refer to Figure 4A ~ Four F households +, not what α, the process steps of the second embodiment of the integrated circuit packaging for integrated circuits of the present invention include:-using substrate 5 to provide-copper wire 400 'defined by etching and other methods Body pillar 410, the surface of the conductor pillar is roughened in a micro-side way to enhance the workability (not shown in the figure); 〃 ⑻ provides a back flip foil 42. This adhesive_micro system contains insulation layer damage and copper box The layer 'presses the insulating layer and the upper surface of the copper box substrate' so that each of the conductors is in the insulating layer. The material of the insulating layer 4201 may be a glass fiber. Prepreg (PΓ, δ), epoxy resin (Qing-) or thicker insulating resin; (〇 open the back shaft above each guide 410 with a laser _ 42 , Forming a plurality of blind holes 430 ′ and removing the remaining insulating material on the conductor post 41〇; ⑷ copper plating on the upper layer of the blind hole 4330 by electroplating copper to form a blind hole structure 430a; (e) The upper and lower circuit layers 4202a, 400a are defined; ⑴ The upper and lower circuit layers 42G2a, 4 (X) a are separately covered with a layer-layer circuit protection layer 450, and the protection layer 450 may be an anti- Solder lacquer or insulating resin, and expose the wire bonding pad 46 which is to be used for chip package wiring and the solder ball pad area 470 electrically connected to the circuit board, and plate a nickel / gold (Ni / Au) layer (not shown). Of course, as in the first embodiment, this embodiment can also be used on both sides of the circuit layer. One —_ 8 ^ & scale applies Chinese National Standard (CNS) A4 (please read the precautions on the back before filling this page) p
五、發明說明（？） 4202a、400a分別覆蓋上一層電路保護層45〇之後，露出欲 作為與晶片銲錫揍之銲墊（圖中未示）及锡球塾之區域，亦 鍛上鎳/金（Ni/Au)層（圖中未示），使本實施例亦可供 覆晶封裝方式封裝晶片。 與第-實施例不同的是，本實施例並未將盲孔43〇鍍滿 銅，而只有鍍上一層薄面鋼440，再以電路保護層45〇之防 鲜材填滿。 ， 第三實施例 請參閱圖五A〜五F所示，本發明積體電路封裝用基板 第三實施例之製程步驟包括： ⑷提供-銅ϋ基材500，以侧等方式定義出複數個導體 柱510，並以微钮刻方式粗化導體柱51〇表面，以增強 其接著性（圖中未示）； (b )提供一背膠銅箔520，該背膠銅箔520係包含絕緣層5201 與銅治層5202，將該絕緣層5201與該銅f|基材5〇〇之 上表面作壓合，使各該導體柱一端埋在該絕緣層 5201 内； (c)以雷射開啟各該導體柱510上方之背膠銅箔52〇1，形 成複數個盲孔530，並清除導體柱51〇面上之殘餘絕緣 物質； ⑷以電鍍銅方式對所述盲孔530鍍上一層面銅54〇，形成 盲孔結構530a ; - (e)餘刻定義出上、下電路層5202a、500a ; ⑴在該上、下電路層分別覆蓋上一層電路保護層55〇 (可 (請先閱讀背面之注意事項再填寫本頁) -I a— n H Μϋ n n I n n ϋ 1 n mmmBm mw— i 經濟部智慧財產局員工消費合作社印製 9 501253 經濟部智慧財產局員工消費合作社印製 A7 五、發明說明（，） 為防銲漆或絕緣樹脂），作為線路保護層，並露出欲作 為晶片封裝打線之複數個打線墊56〇及電路板電性連 接之錫球墊區域570，並在錫球墊區域57〇鍍上一鎳/ 金（Ni/Au)層； (g)在所述上電路層5202a欲作為晶片置放區之複數個銲墊 56〇’覆蓋上-薄導電層（圖中未示），再接著开)成複 數個銲錫凸塊580 (SolderBump)。 本實施例於上述兩實施例不同的是，在晶片置放區下方 之複數個盲孔530a ,形成複數個銲錫凸塊58〇 (Bump)，可 直接作為晶片之接腳，此外，本實施例步驟(d)亦可如同第一 實施例，係以電鍍銅方式鍍滿各該盲孔。 以上所述係為本發明各較佳實施例積體電路封裝用基板 製程步驟之追加一之詳細說明，本發明與母案最大的不同處 係在於使用背膠銅箱製作封裝用基板，尤其是製作超薄板 (0.1mm〜0.4mm)時，以蝕刻及電鍍等方式，在背膠銅箔 及一實心銅箔中完成電路層之導通，因其背膠銅箔係包含一 絕緣層及一銅箔層之組成，不但可簡化製程，且能製作更超 薄之基板，且同樣地，利用一銅箔基板形成之導體柱，對封 裝基板之散熱性及電性品質均能大幅提昇。 因此，本追加案可有效改善習知製造超薄板之缺失，且 本發明之製程容易、成本亦非常低廉，量產性高，充分顯示 出本發明之目的及功效上均深富實施之進步性，極具產業之 利用價值，且為目前市面上所未見之新發明，實施之具體性 本發明誠已符合專利法中所規定之發明專利要件，爰依法提 n 8— Is n n n n n ϋ mm— · n a— n 1 n n n^δ,，« n la ϋ n n n n 8 # (請先閱讀背面之注意事項再填寫本頁) 501253 A7V. Description of the invention (?) After 4202a and 400a are covered with a layer of circuit protection layer 45 respectively, the areas to be used as solder pads (not shown in the figure) and solder balls on the wafer are exposed, and nickel / gold is also forged. (Ni / Au) layer (not shown), so that this embodiment can also be used for chip-on-chip packaging. Different from the first embodiment, this embodiment does not plate the blind hole 43o with copper, but only coats a thin surface steel 440, and then fills it with a fresh-proof material of the circuit protection layer 45o. For the third embodiment, please refer to FIGS. 5A to 5F. The process steps of the third embodiment of the integrated circuit packaging substrate of the present invention include the following steps: ⑷Provide-copperϋsubstrate 500, and define a plurality of sides in a manner such as: Conductor post 510, and roughen the surface of conductor post 51 in a micro-button manner to enhance its adhesion (not shown in the figure); (b) Provide a self-adhesive copper foil 520, which includes insulation Layer 5201 and copper layer 5202, the insulating layer 5201 and the upper surface of the copper f | substrate 5000 are pressed together, so that one end of each of the conductor posts is buried in the insulating layer 5201; (c) a laser Open the adhesive-backed copper foil 5201 above each of the conductor posts 510 to form a plurality of blind holes 530, and remove the remaining insulating material on the surface of the conductor posts 51. 镀 Plating the blind holes 530 by electroplating copper Layer copper 54 °, forming a blind hole structure 530a;-(e) Define the upper and lower circuit layers 5202a, 500a at a time; 覆盖 Cover the upper and lower circuit layers with a circuit protection layer 55o (may (please first Read the notes on the back and fill in this page) -I a— n H Μϋ nn I nn ϋ 1 n mmmBm mw— i Intellectual Property of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative 9 501253 Printed by the Consumer ’s Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 Printed by the Consumer ’s Cooperative of the Ministry of Economic Affairs (5) Invention description (,) is solder resist or insulating resin) as a protective layer of the circuit, and exposed a number of wafer packaging lines The wire pads 56 and the solder ball pad area 570 electrically connected to the circuit board are plated with a nickel / gold (Ni / Au) layer on the solder ball pad area 57. (g) The upper circuit layer 5202a is intended to be used as A plurality of solder pads 560 ′ in the chip placement area are covered with a thin conductive layer (not shown), and then opened) into solder bumps 580 (SolderBump). This embodiment is different from the above two embodiments in that the plurality of blind holes 530a below the wafer placement area form a plurality of solder bumps 58 (Bump), which can be directly used as pins of the wafer. In addition, this embodiment Step (d) is also the same as in the first embodiment, in which each of the blind holes is plated with copper plating. The above is a detailed description of an additional one of the manufacturing process steps of integrated circuit packaging substrates of various preferred embodiments of the present invention. The biggest difference between the present invention and the mother case is the use of adhesive-backed copper boxes to make packaging substrates, especially When making ultra-thin plates (0.1mm ~ 0.4mm), the conduction of the circuit layer is completed in the adhesive-backed copper foil and a solid copper foil by means of etching and electroplating, because the adhesive-backed copper foil includes an insulating layer and a The composition of the copper foil layer not only simplifies the manufacturing process, but also enables the production of ultra-thin substrates. Similarly, the conductive pillars formed by a copper foil substrate can greatly improve the heat dissipation and electrical quality of the package substrate. Therefore, this addendum can effectively improve the lack of conventional manufacturing of ultra-thin plates, and the process of the present invention is easy, the cost is very low, and the mass productivity is high, which fully shows that the object and effect of the present invention are deeply implemented. Nature, has great industrial use value, and is a new invention not seen on the market today. The specificity of the implementation of this invention has already met the requirements of the invention patent stipulated in the Patent Law. According to the law, n 8— Is nnnnn ϋ mm — · Na— n 1 nnn ^ δ ,, «n la ϋ nnnn 8 # (Please read the notes on the back before filling this page) 501253 A7
發明說明（\。） 出申請，謹請貴審查委員惠予審視，並賜准專利為禱。 當然’以上所述僅為本發明顧·職用基板製程之 追加-之較錄_，並義穩制树仅實施範圍 如導體柱之之高絲f孔之深料，並料綱書或 揭露者練’任織龍微藝者在骑穌购 做之修改，均·於本剌之範圍，目此本翻 當以下列所述之冑料職®做為依據。 ’'&圍 (請先閱讀背面之注意事項再填寫本頁}Description of the Invention (\.) Please submit your application for your review and grant the patent as a prayer. Of course, the above is only an addition to the manufacturing process of the substrate for professional use in the present invention, and it is a comparison. It also only implements deep materials such as high-wire f-holes in the conductor column, and the material outline or disclosure. The modifications made by Ren Zhilong's micro-artist during the ride are all within the scope of this book. For the purpose of this book, we will use the following materials as the basis for the book. ’'&Amp; Wai (Please read the notes on the back before filling out this page}
經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
IX 1X 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）IX 1X This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)