201233052 1 w/D\)irj\ 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種軌對執放大器。 【先前技術】 請同時參照第1A圖及第1B圖，第1A圖繪示傳統執 對執放大器之電路圖，第1B圖繪示傳統執對軌放大器之 操作電壓區間之示意圖。於第1A圖之執對執放大器10 中，NMOS電晶體N1及N2組成NMOS輸入對，PMOS 電晶體P1及P2組成PMOS輸入對，NMOS輸入對及PMOS 輸入對分別耦接至電流源12及14。 當輸入電壓Vi低於NMOS電晶體N1及N2的臨界電 壓時，NMOS電晶體N1及N2為截止，電流源12的電流 不會流入輸出級電路16 ;同時段，PMOS電晶體P1及P2 為導通，電流源14的電流流入輸出級電路16以供進行操 作。此外，當輸入電壓Vi高於PMOS電晶體P1及P2的 臨界電壓時，PMOS電晶體P1及P2為截止，電流源14 的電流不會流入輸出級電路16 ;同時段，NMOS電晶體 N1及N2為導通，電流源12的電流流入輸出級電路16以 供進行操作。觀察第1B圖可得知，執對執放大器10在部 分的輸入電壓區間時，NMOS輸入對及PMOS輸入對同時 導通，相較於單一輸入對放大器而言，雖具有全區間輸入 電壓可操作的優點，但會導致不必要的功率消耗。 【發明内容】 201233052201233052 1 w/D\)irj\ VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a rail-to-arm amplifier. [Prior Art] Please refer to FIG. 1A and FIG. 1B at the same time. FIG. 1A is a circuit diagram of a conventional licensed amplifier, and FIG. 1B is a schematic diagram showing an operating voltage range of a conventional rail-on-amplifier. In the implementation of the amplifier 10 in Figure 1A, the NMOS transistors N1 and N2 form an NMOS input pair, the PMOS transistors P1 and P2 form a PMOS input pair, and the NMOS input pair and the PMOS input pair are coupled to the current sources 12 and 14, respectively. . When the input voltage Vi is lower than the threshold voltages of the NMOS transistors N1 and N2, the NMOS transistors N1 and N2 are turned off, the current of the current source 12 does not flow into the output stage circuit 16; at the same time, the PMOS transistors P1 and P2 are turned on. The current from current source 14 flows into output stage circuit 16 for operation. In addition, when the input voltage Vi is higher than the threshold voltages of the PMOS transistors P1 and P2, the PMOS transistors P1 and P2 are turned off, and the current of the current source 14 does not flow into the output stage circuit 16; at the same time, the NMOS transistors N1 and N2 To turn on, current from current source 12 flows into output stage circuit 16 for operation. Observing Figure 1B, it can be seen that when the input amplifier voltage section 10 is in the partial input voltage range, the NMOS input pair and the PMOS input pair are simultaneously turned on, compared with the single input pair amplifier, although the full range input voltage is operable. Advantages, but can result in unnecessary power consumption. [Abstract content] 201233052
TW7501PA 電路二露:單有關Γ種放大器，在操作時利用電流轉換 時兼具全區間：:==器相同的電流消耗，故可同 根據本揭露之第β ”及低功率消耗的優點。 出級電路、一電3一方面’提出一種放大器，包括一輸 對以及-電流以路：輸入對 壓及-地電壓輸出級電路電性連接至-供應電 輸入對耦接至節點有：即:點以提供-電流。_S 輸入對搞接至供應電壓並受控於—輸人電壓。NMOS 麵接至節點及Nlvios/t控於輸人電麗。電流轉換電路 定值時，PM0S輪入對^對°其中’當輸入電壓小於一特 路截止，使得電流㈣A/ ’NM()S輸人對及電流轉換電 壓大於等於特I;;由郎點流入 及電流轉換電路入對截止，咖S輸入對 流入mios輸入對。吏仔電^經由節點及電流轉換電路 根據本揭露之笛一 出級電路、-電流源== 一種放大器’包括-輸 對以及-電流榦^ NM0S輸入對、- PMOS輸入 壓及-地電壓1、^°輸出級電路電性連接至一供應電 輸入對減心提供1流。轉 PMOS I-a 仏應電壓，並受控於一輸入電壓。 電路耦：至1地電壓並受控於輸入電壓。電流轉換 = =:PM〇S輸入對。其中，當輸入電壓大於 換電路截止’使得〇電= 入對導通，請⑽輸入對及電流轉 入電壓小於等於特定^由節點流入NM〇S輸入對，當輸 值日守，NM〇S輸入對截止，PMOS輸 201233052TW7501PA circuit two dew: single amplifier related to the use of current conversion in the operation of the full range: : = = the same current consumption of the device, so the same according to the disclosure of the β ” and low power consumption advantages. The stage circuit, an electric circuit 3, on the one hand, proposes an amplifier comprising an input pair and a current path: the input counter voltage and the ground voltage output stage circuit are electrically connected to the - supply electric input pair coupled to the node: ie: Point to provide - current. _S input pair is connected to the supply voltage and controlled by - input voltage. NMOS surface is connected to the node and Nlvios / t control is input to the battery. When the current conversion circuit is set, the PM0S wheeled pair ^对° where 'when the input voltage is less than a special way to cut off, so that the current (four) A / 'NM () S input pair and the current conversion voltage is greater than or equal to special I;; from the lang point inflow and current conversion circuit into the cut-off, coffee S input Input to the mios input pair. 吏仔电^ via node and current conversion circuit according to the present disclosure of the flute-level circuit, - current source == an amplifier 'including-transmission pair and - current dry ^ NM0S input pair, - PMOS input Voltage and ground voltage 1, ^ ° output The circuit is electrically connected to a supply electrical input to provide a current to the centering. The PMOS Ia is responsive to a voltage and is controlled by an input voltage. Circuit coupling: to a ground voltage and controlled by the input voltage. Current conversion ==: PM〇S input pair. Among them, when the input voltage is greater than the cut-off of the circuit, so that the input voltage is turned on, please (10) input pair and the current transfer voltage is less than or equal to the specific ^ from the node into the NM〇S input pair, when the value is converted Shou, NM〇S input pair cutoff, PMOS input 201233052
1 W/5U1^A ==:::通’使得電流經由節點及電流轉換 為了對本揭露之上述及其他方 特舉一實施例，並配合所_式，作詳細朗^:，下文 【實施方式】 本揭露所提出之放大器，在操作 將電流源在PMQS輸人對與Ν_輸二轉換電路 換，以達成與單一輸人對放μ ’間進打轉 拉i曰相同的電流消耗，故可同 寺兼具全區間輸人電壓可操作及低功率消耗的優點。 請參照第2A圖與第2B圖，第2A圖繪示依照一實施 =之放大器之電路圖’帛2B圖繪示依照—實施例之放大 裔^呆作電壓區間之示意圖。於第2A圖中，放大器1〇〇 實貝上為執對執放大器，其包括一輸出級電路丨1〇、一 電流源120、一 PM0S輸入對13〇、一 NM〇s輸入對14〇 以及一電流轉換電路150。輸出級電路110電性連接至一 供應電壓（supply voltage)VSS及一地電壓gnD。電流源 120具有一節點01以提供一電流。PMOS輸入對130實質 上由PM0S電晶體P01及P02所組成，其耦接至節點Ο卜 並透過輸出級電路U〇電性連接至地電壓GND。PMOS輸 入對130受控於一輸入電壓％。 NM0S輸入對140實質上由NMOS電晶體N01及N02 戶斤組成’其其透過輸出級電路110電性連接至供應電壓 VSS並受控於輸入電壓Vi。電流轉換電路150耦接至節點 〇1及NMOS輸入對14〇。電流轉換電路150包括一第一 201233052 i w/^ui^a NMOS電晶體N1、一第二NMOS電晶體N2以及一第一 PM0S電晶體P卜第一 NM0S電晶體N1之第一端耦接至 NMOS輸入對140，第一 NMOS電晶體N1之第二端耦接 至地電壓GND。 第二NMOS電晶體N2之第一端耦接至第一 NMOS 電晶體N1之控制端，第二NMOS電晶體N2之第二端耦 接至地電壓GND，第二NMOS電晶體N2之控制端耦接至 第一 NMOS電晶體N1之控制端。第一 PM0S電晶體P1 之第一端耦接至節點01，第一 PM0S電晶體P1之第二端 耦接至第二NMOS電晶體N2之第一端，第一 PM0S電晶 體P1之控制端接收一控制電壓VI，控制電壓VI相關於 輸入電壓Vi及第一 PM0S電晶體P1之臨界電壓。 當輸入電壓Vi小於一特定值SV時，PM0S電晶體 P01及P02導通，亦即PM0S輸入對130導通；同時，NMOS 輸入對140及電流轉換電路150截止，使得電流源120提 供之電流經由節點01流入導通之PM0S輸入對130，再 送至輸出級電路110以供進行操作。其中，特定值SV約 為控制電壓VI與第一 PM0S電晶體P1之臨界電壓的和扣 掉輸入電壓Vi與節點01之電壓差。 當輸入電壓Vi上升時，節點01的電壓也會上升。當 輸入電壓Vi大於等於特定值SV時，NMOS電晶體N01 及N02導通，亦即NMOS輸入對140導通；同時，PM0S 輸入對130截止。此時，電流轉換電路150導通，第一 PM0S 電晶體P1導通，藉由第一 NMOS電晶體N1與第二NMOS 電晶體N 2所組成的電流鏡*將電流源12 0的電流經由印 201233052 i w/^υΐΡΑ 點01及電流轉換電路150流入NMOS輸入對140，再送 至輸出級電路110以供進行操作。 如此一來，即可讓NMOS輸入對140可以操作在 PM0S輸入對130無法導通的輸入電壓區間，達到全區間 輸入電壓可操作的優點，且更進一步地可利用控制電壓 VI以決定NMOS輸入對140導通的輸入電壓區間。此 外，觀察第2B圖可以得知，無論對應於任何輸入電壓， 只有PMOS輸入對130與NMOS輸入對140其中之一輸 入對會導通，故可達到節省電流的目的，且因為移除NMOS 輸入對140對應的尾端電流源，所以操作電流與單一輸入 對放大器相同。 請參照第3A圖與第3B圖，第3A圖繪示依照另一實 施例之放大器之電路圖，第3B圖繪示依照另一實施例之 放大器之操作電壓區間之示意圖。於第3A圖中，放大器 200實質上為一軌對執放大器，其包括一輸出級電路210、 一電流源220、一 NMOS輸入對230、一 PMOS輸入對240 以及一電流轉換電路250。輸出級電路210電性連接至供 應電壓VSS及地電壓GND。電流源220具有一節點02 以提供一電流。NMOS輸入對230實質上由NMOS電晶體 N01及N02所組成，其耦接至節點02，並透過輸出級電 路210電性連接至供應電壓VSS。NMOS輸入對230受控 於一輸入電壓Vi。 PMOS輸入對240實質上由PMOS電晶體P01及P02 所組成，其透過輸出級電路210電性連接至地電壓G.NS 並受控於輸入電壓Vi。電流轉換電路250耦接至節點02 2012330521 W/5U1^A ==:::pass: The current is converted via the node and the current in order to exemplify the above and other embodiments of the present disclosure, and in conjunction with the formula, the details are as follows: The amplifier proposed in the disclosure has the same current consumption in the operation of the PMQS input pair and the Ν_transmission two conversion circuit in order to achieve the same current consumption as the single input pair. Tongsi has the advantages of full range input voltage operation and low power consumption. Please refer to FIG. 2A and FIG. 2B. FIG. 2A is a schematic diagram showing the circuit diagram of the amplifier according to an embodiment. FIG. In Figure 2A, the amplifier 1 is a pair of amplifiers, which includes an output stage circuit 丨1〇, a current source 120, a PMOS input pair 13〇, an NM〇s input pair 14〇, and A current conversion circuit 150. The output stage circuit 110 is electrically connected to a supply voltage VSS and a ground voltage gnD. Current source 120 has a node 01 to provide a current. The PMOS input pair 130 is substantially composed of PM0S transistors P01 and P02, which are coupled to the node and electrically connected to the ground voltage GND through the output stage circuit U. The PMOS input pair 130 is controlled by an input voltage %. The NM0S input pair 140 is substantially composed of NMOS transistors N01 and N02, which are electrically connected to the supply voltage VSS through the output stage circuit 110 and are controlled by the input voltage Vi. The current conversion circuit 150 is coupled to the node 〇1 and the NMOS input pair 14A. The current conversion circuit 150 includes a first 201233052 iw/^ui^a NMOS transistor N1, a second NMOS transistor N2, and a first PMOS transistor P. The first end of the first NMOS transistor N1 is coupled to the NMOS. Input pair 140, the second end of the first NMOS transistor N1 is coupled to the ground voltage GND. The first end of the second NMOS transistor N2 is coupled to the control terminal of the first NMOS transistor N1, the second terminal of the second NMOS transistor N2 is coupled to the ground voltage GND, and the control terminal of the second NMOS transistor N2 is coupled. Connected to the control terminal of the first NMOS transistor N1. The first end of the first PMOS transistor P1 is coupled to the node 01, and the second end of the first PMOS transistor P1 is coupled to the first end of the second NMOS transistor N2, and the control terminal of the first PMOS transistor P1 receives A control voltage VI, the control voltage VI is related to the input voltage Vi and the threshold voltage of the first PMOS transistor P1. When the input voltage Vi is less than a specific value SV, the PMOS transistors P01 and P02 are turned on, that is, the PMOS input pair 130 is turned on; meanwhile, the NMOS input pair 140 and the current conversion circuit 150 are turned off, so that the current supplied by the current source 120 passes through the node 01. The PMOS input pair 130, which is turned on, is sent to the output stage circuit 110 for operation. The specific value SV is about the sum of the control voltage VI and the threshold voltage of the first PM0 transistor P1, and the voltage difference between the input voltage Vi and the node 01 is deducted. When the input voltage Vi rises, the voltage at node 01 also rises. When the input voltage Vi is greater than or equal to the specific value SV, the NMOS transistors N01 and N02 are turned on, that is, the NMOS input pair 140 is turned on; meanwhile, the PMOS input pair 130 is turned off. At this time, the current conversion circuit 150 is turned on, the first PMOS transistor P1 is turned on, and the current of the current source 12 0 is passed through the 201233052 iw by the current mirror* composed of the first NMOS transistor N1 and the second NMOS transistor N 2 . /^υΐΡΑ Point 01 and current conversion circuit 150 flows into NMOS input pair 140 and is sent to output stage circuit 110 for operation. In this way, the NMOS input pair 140 can be operated in the input voltage range in which the PM0S input pair 130 cannot be turned on, and the full range input voltage can be operated, and the control voltage VI can be further utilized to determine the NMOS input pair 140. The input voltage range that is turned on. In addition, it can be seen from FIG. 2B that, regardless of any input voltage, only one of the PMOS input pair 130 and the NMOS input pair 140 is turned on, so that current saving can be achieved, and because the NMOS input pair is removed. 140 corresponds to the tail current source, so the operating current is the same as the single input pair amplifier. Referring to FIGS. 3A and 3B, FIG. 3A is a circuit diagram of an amplifier according to another embodiment, and FIG. 3B is a schematic diagram showing an operating voltage interval of an amplifier according to another embodiment. In FIG. 3A, amplifier 200 is essentially a rail-to-rail amplifier comprising an output stage circuit 210, a current source 220, an NMOS input pair 230, a PMOS input pair 240, and a current conversion circuit 250. The output stage circuit 210 is electrically connected to the supply voltage VSS and the ground voltage GND. Current source 220 has a node 02 to provide a current. The NMOS input pair 230 is substantially composed of NMOS transistors N01 and N02, which are coupled to the node 02 and electrically connected to the supply voltage VSS through the output stage circuit 210. The NMOS input pair 230 is controlled by an input voltage Vi. The PMOS input pair 240 is substantially composed of PMOS transistors P01 and P02, which are electrically coupled to the ground voltage G.NS through the output stage circuit 210 and are controlled by the input voltage Vi. The current conversion circuit 250 is coupled to the node 02 201233052
IW75U1FA 及PMOS輸入對240。電流轉換電路250包括一第一 PMOS 電晶體P1、一第二PM0S電晶體P2以及一第一 NM0S電 晶體N1。第一 PMOS電晶體P1之第一端耦接至PMOS輸 入對240，第一 PMOS電晶體P1之第二端耦接至供應電 壓 VSS。 第二PMOS電晶體P2之第一端耦接至第一 PMOS電 晶體P1之控制端，第二PMOS電晶體P2之第二端耦接至 供應電壓VSS，第二PMOS電晶體P2之控制端耦接至第 一 PMOS電晶體P1之控制端。第一 NM0S電晶體N1之 第一端耦接至節點02，第一 NM0S電晶體N1之第二端 耦接至第二PMOS電晶體P2之第一端，第一 NM0S電晶 體N1之控制端接收一控制電壓V2，控制電壓V2相關於 輸入電壓Vi及第一 NM0S電晶體N1之臨界電壓。 當輸入電壓Vi大於一特定值SV時，NM0S電晶體 N01及N02導通，亦即NM0S輸入對230導通；同時， PMOS輸入對240及電流轉換電路250截止，使得電流源 220提供之電流經由節點02流入導通之NM0S輸入對 230，再送至輸出級電路210以供進行操作。其中，特定 值S V約為控制電壓V2與第一 NM0S電晶體N1之臨界 電壓的差加上輸入電壓Vi與節點02之電壓差。IW75U1FA and PMOS input pair 240. The current conversion circuit 250 includes a first PMOS transistor P1, a second PMOS transistor P2, and a first NMOS transistor N1. The first end of the first PMOS transistor P1 is coupled to the PMOS input pair 240, and the second end of the first PMOS transistor P1 is coupled to the supply voltage VSS. The first end of the second PMOS transistor P2 is coupled to the control terminal of the first PMOS transistor P1, the second end of the second PMOS transistor P2 is coupled to the supply voltage VSS, and the control terminal of the second PMOS transistor P2 is coupled. Connected to the control terminal of the first PMOS transistor P1. The first end of the first NMOS transistor N1 is coupled to the node 02, and the second end of the first NMOS transistor N1 is coupled to the first end of the second PMOS transistor P2, and the control terminal of the first NMOS transistor N1 receives A control voltage V2, the control voltage V2 is related to the input voltage Vi and the threshold voltage of the first NMOS transistor N1. When the input voltage Vi is greater than a specific value SV, the NM0S transistors N01 and N02 are turned on, that is, the NM0S input pair 230 is turned on; meanwhile, the PMOS input pair 240 and the current conversion circuit 250 are turned off, so that the current supplied by the current source 220 passes through the node 02. The incoming NM0S input pair 230 is sent to the output stage circuit 210 for operation. The specific value S V is approximately the difference between the control voltage V2 and the threshold voltage of the first NMOS transistor N1 plus the voltage difference between the input voltage Vi and the node 02.
當輸入電壓Vi下降時，節點02的電壓也會下降。當 輸入電壓Vi小於等於特定值SV時，PMOS電晶體P01及 P02導通，亦即PMOS輸入對240導通；同時，NM0S輸 入對230截止。此時，電流轉換電路250導通，第一 NM0S 電晶體N1導通，藉由第一 PMOS電晶體P1與第二PMOS 201233052 l w /^υιι^Α 電晶體P2所組成的電流鏡，將電流源220的電流經由節 點02及電流轉換電路250流入PMOS輸入對240，再送 至輸出級電路210以供進行操作。 如此一來，即可讓PMOS輸入對240可以操作在 NMOS輸入對230無法導通的輸入電壓區間，達到全區間 輸入電壓可操作的優點，且更進一步地可利用控制電壓 V2以決定PMOS輸入對240導通的輸入電壓區間。此外， 觀察第3B圖可以得知，無論對應於任何輸入電壓，只有 NMOS輸入對230與PMOS輸入對240其中之一輸入對會 導通，故可達到節省電流的目的，且因為移除PMOS輸入 對240對應的尾端電流源，所以操作電流與單一輸入對放 大器相同。 本揭露上述實施例所揭露之放大器，利用電流轉換電 路取代傳統的尾端電流源，故可在操作時將電流源在 PMOS輸入對與NMOS輸入對之間進行轉換，以達成與單 一輸入對放大器相同的電流消耗，故可同時兼具全區間輸 入電壓可操作及低功率消耗的優點。 綜上所述，雖然本發明已以多個實施例揭露如上，然 其並非用以限定本發明。本發明所屬技術領域中具有通常 知識者，在不脫離本發明之精神和範圍内，當可作各種之 更動與潤飾。因此，本發明之保護範圍當視後附之申請專 利範圍所界定者為準。 201233052 i w/^υι^Α 【圖式簡單說明】 第1A圖繪示傳統執對軌放大器之電路圖。 第1B圖繪示傳統軌對軌放大器之操作電壓區間之示 意圖。 第2A圖繪示依照一實施例之放大器之電路圖。 第2B圖繪示依照一實施例之放大器之操作電壓區間 之示意圖。 第3A圖繪示依照另一實施例之放大器之電路圖。 第3B圖繪示依照另一實施例之放大器之操作電壓區 間之示意圖。 【主要元件符號說明】 10 :執對軌放大器 12、14、120、220 :電流源 16、110、210 :輸出級電路 100、200 :放大器 130、240 : PMOS 輸入對 140、230 : NMOS 輸入對 150、250 :電流轉換電路When the input voltage Vi drops, the voltage at node 02 also drops. When the input voltage Vi is less than or equal to the specific value SV, the PMOS transistors P01 and P02 are turned on, that is, the PMOS input pair 240 is turned on; meanwhile, the NM0S input pair 230 is turned off. At this time, the current conversion circuit 250 is turned on, and the first NMOS transistor N1 is turned on, and the current source 220 is formed by the current mirror composed of the first PMOS transistor P1 and the second PMOS 201233052 lw /^υιι^ transistor P2. Current flows into node PMOS input pair 240 via node 02 and current conversion circuit 250 and is sent to output stage circuit 210 for operation. In this way, the PMOS input pair 240 can be operated in an input voltage range in which the NMOS input pair 230 cannot be turned on, and the full range input voltage can be operated, and the control voltage V2 can be further utilized to determine the PMOS input pair 240. The input voltage range that is turned on. In addition, it can be seen from FIG. 3B that only one of the NMOS input pair 230 and the PMOS input pair 240 will be turned on regardless of any input voltage, so that current saving can be achieved, and the PMOS input pair is removed. 240 corresponds to the tail current source, so the operating current is the same as the single input pair amplifier. The amplifier disclosed in the above embodiment uses a current conversion circuit to replace the conventional tail current source, so that the current source can be converted between the PMOS input pair and the NMOS input pair during operation to achieve a single input to the amplifier. The same current consumption, so it can simultaneously have the advantages of full range input voltage operation and low power consumption. In the above, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 201233052 i w/^υι^Α [Simple description of the diagram] Figure 1A shows the circuit diagram of a conventional rail-to-rail amplifier. Fig. 1B is a diagram showing the operation voltage interval of a conventional rail-to-rail amplifier. 2A is a circuit diagram of an amplifier in accordance with an embodiment. 2B is a schematic diagram showing an operating voltage interval of an amplifier in accordance with an embodiment. FIG. 3A is a circuit diagram of an amplifier in accordance with another embodiment. Figure 3B is a schematic diagram showing the operating voltage range of an amplifier in accordance with another embodiment. [Main component symbol description] 10: Rail amplifier 12, 14, 120, 220: Current source 16, 110, 210: Output stage circuit 100, 200: Amplifier 130, 240: PMOS input pair 140, 230: NMOS input pair 150, 250: current conversion circuit