200916796 九、發明說明： 【發明所屬之技術領域】 明係關於一偵測電路，特別是指接地電位交越偵 測（或稱交越接地電位偵測），該電路僅包括四 $四個電晶體僅具有二個電流源，因此本發明所設計之 電路可大大減少電源之消耗。 【先前技術】 請^第-圖，其係傳統靠—單電源3以及13個電晶 體執仃接地電位交越（gIOUnd VQltage⑽如⑻之伯測電 路’該13個電晶體構成5個電流源，在第一圖中，編號^ 係-輸入端，編號2係-輸出端；編號14係__ 差動放大電路，其係由p型電晶體7、1()、u以及η型電 晶體8、9所組成#; ρ型電晶體1Μ目當於—第一電位位 移器’視同-第-祕追隨器，以及ρ型電晶體17相當於 第二電位位移器，視同一第二源極追隨器。 該電路之作動原理說明如下：藉由—電源電位3啟動 η型電晶體6，因此Α點電壓被往下拉，進而維雜定，又 P型電晶體15、7、16、5、12之閘極電位都被固定於A 點電位’故電晶體15 ' 7 ' 16、5 ' 12提供了 5個怪定電流 源，B點之電壓因此維持穩定。 P型電晶體17係-個源極追隨器，其具有一個問極接 地，其作動如同一位移電壓器用以提供一拉升殘餘電壓 (residual voltage)之功能，其可將£點之殘餘電壓拉升 以提供CMOS type差動放大電路14第一輸入端之輸入電 壓；P型電晶體18亦係一個源極追隨器，且其作動如同一 200916796 電壓位移器，開極接受一輸入端1饋入待偵測之輸入訊 號’ p型電晶體18與P梨電晶體π具有相同之特性。 因N型電晶體8、9構成一電流鏡，所以n(Iref)通過 P型電晶體10時，將與電流12(1。)通過p型電晶體η時 相同。 請同時參照第二A圖以及第二B圖’待偵測之輸入訊 號L1比接地電位高時，為輸入端1所接收，CMOS type差 動放大電路14之第二輸入端F電位藉由拉升位移電位Μ 被拉升至一電位L2，同樣地，CMOS type差動放大電路 之第一輸入端E接地電位藉由拉升位移電位17被拉升至一 電位L3，當電位L2高於電位L3時，PM0S電晶體Η二端 之電位差因此減低，因此’藉由η型電晶體13放大輸出端 2之電壓後，將減少c點之電壓。 當待偵測之輸入訊號L1低於接地電位時為輸入端1 所接收，如上述，CMOS type差動放大電路14之第二輸入 F電位與第·—輸入端E電位被分別拉升至一電位L2與 L3。然而’電位L2係低於電位L3 ’ PM0S電晶體1〇二端 之電位差因此增加，因而使得D點電壓減少，因此，在c 點之PM0S電晶體11二端電位差值係高的，Δν2的電位變 化低時，將使AVI升高’結果是輸出端2電位低，其情形 如第二Β圖所示。 當輸入訊號L相當於接地電位時，CM0S之第二輸入端 E之電位以及第一輸入端F之電位係相等的，因此輸出端2 之電位係未定的；輸出端2之電位將依據其前後狀態作相 對應之改變’例如：如輸入訊號L從低於接地電位升高至 200916796 高於接地電位，輸出端2之電位將由一低狀態改變為一高 狀態’或是如輸入訊號L從高於接地電位降低至低於接地 電位’輸出端2之電位將由一高狀態改變為一低狀態，因 此當輸入訊號通過接地時，該電路可提供一偵測接地電位 交越之功能。 【發明内容】 本發明係揭露一偵測電路，偵測一輸入訊號交越接地 電位或VCC電源電位’當電路使用偵測交越接地電位時， 該電路包括二個PM0S電晶體，該二pM0S電晶體分別連接 於二個NM0S電晶體，該二pm〇s電晶體接具有一源極，且 該二源極連接於一電源電位’第二PM〇s電晶體之閘極與汲 極係相連接的，第一 NM0S電晶體具有一如同輸入端之源極 以及一如同輸出端之汲極，該源極收回一輸入訊號，而第 一 NM0S電晶體具有一源極接地；該二電晶體之閘極 係相連接的，且亦連接於一偏電壓；若輸入端設置於第一 PM0S電晶體之源極，且該第一 NM〇s電晶體之源極係接地 的，该電路亦能夠用來偵測電源電位交越。 關於本發明所述之偵測電路，可以藉由以下發明詳述 及所附圖式，得到進一步的瞭解。 【實施方式】 如習知技術所述，不論交越接地電位或交越Vcc之偵 測電路皆包含13個電晶體以及5個電流源，因此，傳統之 偵測電路係相當複雜且高電流消耗的，對於電池供給電力 200916796 之設備是不利的。 針對電池供給電力之設備，本發明設計出一電路，僅 包含四個電晶體以及二個電流源，可節省電源消耗，如第 二a圖所不，其係本發明第一實施例交越接地電位之偵測 電路，係由二個PM0S電晶體Pi，P2以及二個_s電晶體 Nl，N2.所構成之偵測電路。 在該電路中，該PM0S電晶體Pi，P2之源極係共同連 接於一電源Vcc，該二閘極係相連接的，且該二汲極係各 別與NM0S電晶體N1與NM0S電晶體N2之汲極相連接，另 外’PM0S電晶體P2之閘極更與其本身之汲極相連接，顺〇s 電晶體Nl，N2之閘極係共同連接於一偏壓訊號bias，nm〇s 電晶體N2之源極係接地的，但刚〇s電晶體N1之源極係與 一輸入訊號IN相連接，NM0S電晶體N1之汲極作為一輸出 端 OUT。 該交越接地電位偵測電路之運作說明如下：請同時參 照第二b圖以及第二c圖，當一輸入訊號νίΝ之電位高於接 地電位或輸入端浮置，當高於NM0S電晶體N2啟始電位VtN2 的電位Vms施加於NM0S電晶體Nl、N2之閘極，即刚〇s電 晶體N2係呈啟動狀態’且進入三態’但刚|〇s電晶體Ni 係呈關閉狀態’因為VBIAS-VtNl - VlN〈 0，因此產生丨2而 Ιι= 0 ’沒有電流通過PM0S電晶體P1，因而將輸出端out 的電位拉升至VCC。 當輸入訊號VlN的電位減少至接近接地電位（〉〇 + )時， VBIAS-VtNl - VlN的總合會稍大於〇,且電流1,開始流動i e Ιι笑0 ’但仍然小於12，在這個狀況下，Vd2 < vcc _ 1+ 200916796 abs(Vtp2)，在 abs(Vtp2)，Vs〇 的 Vs〇+abs(Vtp2)分別係一 啟始電壓的絕對值以及一 PM〇s電晶體p2源極至閘極的電 壓’ PM0S電晶體pi，P2將進入一飽和狀態，因此輸出端 out的電壓yQUT仍然拉升至接近vcc。 當輸入訊號VIN的電位等於接地電位時，該電路變成一 電流鏡’因此ΐ2= ’輸出端OUT的電壓Vot在VCC以及 GND之中。當輸入訊號Vin的電位低於接地電位時，[> I2 ’且V⑽與Vbus將使NM0S電晶體N1進入一飽和狀態，輸 出端out的電壓ν〇υτ仍然維持在低狀態。因此，輸出端ουτ 的電壓Vout將由高轉為低，或是由低轉為高，輸入訊號-交越接地電位時將能夠被偵測到。 上述之實施例係建立於NM0S電晶體N1，N2的大小相 等’若NM0S電晶體N1的大小比例與NM〇s電晶體N2不同， 則可調高交越電位或調低交越電位，不限於接地電位之交 越Y貞測。 上述電路係也可以如下變化以偵測一交越VCC電位之 輸入訊號IN如第四a圖所示，電晶體的數量，形式以及連 接方式與第三a圖相似，不同之處在於輸入端in的位置， 請參照第四圖，其係本發明之第二最佳實施例，輸入端IN 係設置於PM0S電晶體P1之源極，跨VCc偵測電路之輸入 訊號IN之說明將於以下詳細敘述。 請參照第四圖，當輸入訊號IN之電壓係接地的或低於 接地電位，高於NM0S電晶體N2電壓ytN2之電壓VBiAS將應用 於NM0S電晶體N2，N1之閘極，因為vBus-VtN2 > 0，因此 NM0S電晶體N2係呈開啟狀態，且使其進入三態，此時電 200916796 壓 Vd2 < VCC - VsGP2+ abs(VtP2)，一恆定電流 12流通過 NMOS 電晶體N2至接地，沒有電流流通過PMOS電晶體PI (l1 = 0)，輸出電壓OUT係維持低狀態。 當輸入訊號IN之電位由接地電位拉升時（仍然低於 VCC) ’電流開始流動，且流通過NM0S電晶體N1至接地， Vbus電壓以及電流i^NMOS電晶體N1進入三態，此時ΐκ< Ιζ ’因此輸出端OUT之電壓係維持低狀態。當輸入訊號in 之電位等於VCC時，該電路變為一電流鏡’該電流鏡具有 一鏡像電流Ιι ’通過PM0S電晶體P1之鏡像電流I!係與通 過PM0S電晶體P2之參考電流I2相等的，輸出端〇υτ之電 位被拉升至VCC，因此跨VCC電位之輸入訊號in將被偵測 到，請參照第四b圖以及第四c圖，該輸入訊號改變且該 輸出訊號改變。 本發明之優點如下： 1·因為本發明之電路僅由四個電晶體所構成，因此相對於 習知技術，本發明可大大減少電流消耗。 2.只需，變電晶體之通道寬度長度比(w/l)ni/(w/l>2，即 可調高或調低交越電位之偵測點。 本發明雖以触實例_如上’然其並_以限定本 發明之精神與㈣實止於上述實施_。是以，在不 ，離本發明之精神絲_所作之修改，均應包括在下述 申請專利範圍内。 200916796 【圖式簡單說明】 第一圖，傳統接地電位交越之偵測電路； 第二a圖以及第二b圖，依據第一圖電路之輸入以及輸出 之電位改變； 第三a圖，依據本發明第一實施例交越接地電位之偵測電 路； 第三b圖以及第三c圖，依據第三a圖電路之輸入以及輸 出之電位改變； 第四a圖，依據本發明第二實施例偵測交越Vcc電位之偵 測電路； 第四b圖以及第四c圖，依據第四a圖電路之輸入以及 輸出之電位改變。 【主要元件符號說明】 11 200916796 1、 IN輸入端 2、 OUT輸出端 F第一輸入端 E第二輸入端 3電源電位 6、8、9、13 N型電晶體 5、7、10、11、12、15、16、17、18 P 型電晶體 A、B、C、D、D2 電壓點 14差動放大電路 I〇、Iref、II、h 電流 L > LI ' L2、L3、L4 訊號200916796 IX. Description of the invention: [Technical field of the invention] The system relates to a detection circuit, in particular to ground potential crossover detection (or crossover ground potential detection), the circuit only includes four or four electric The crystal has only two current sources, so the circuit designed by the present invention can greatly reduce the power consumption. [Prior Art] Please ^-picture, which is traditionally based on - single power supply 3 and 13 transistors to perform ground potential crossover (gIOUnd VQltage (10) such as (8) of the beta circuit's 13 transistors constitute 5 current sources, In the first figure, the number is - the input, the number is 2 - the output; the number is 14 - _ differential amplifier circuit, which is composed of p-type transistors 7, 1 (), u and n-type transistor 8 9 constituents #; ρ-type transistor 1 当 当 — — 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一 第一The operation principle of the circuit is as follows: the n-type transistor 6 is activated by the power supply potential 3, so that the voltage of the defect is pulled down, and then the P-type transistor 15, 7, 16, 5, The gate potential of 12 is fixed at the potential of point A. Therefore, the transistor 15 ' 7 ' 16, 5 ' 12 provides five strange current sources, and the voltage at point B remains stable. P-type transistor 17 series - a source follower having a gate ground, the act of which acts as a displacement voltage regulator to provide a pull-up residual voltage (residual volt The function of age), which pulls up the residual voltage of the point to provide the input voltage of the first input of the CMOS type differential amplifier circuit 14; the P-type transistor 18 is also a source follower, and the actuation is the same 200916796 Voltage Displacer, open-circuit accepts an input 1 to feed the input signal to be detected' p-type transistor 18 has the same characteristics as P-Pear transistor π. Since N-type transistors 8, 9 form a current mirror, Therefore, when n(Iref) passes through the P-type transistor 10, it will be the same as when the current 12 (1.) passes through the p-type transistor η. Please refer to the second A picture and the second B picture as the input signal L1 to be detected. When the ground potential is higher than the ground potential, the second input terminal F of the CMOS type differential amplifier circuit 14 is pulled up to a potential L2 by the pull-up displacement potential ,, and similarly, the CMOS type differential amplification is performed. The grounding potential of the first input terminal E of the circuit is pulled up to a potential L3 by the pull-up displacement potential 17, and when the potential L2 is higher than the potential L3, the potential difference between the two ends of the PM0S transistor is thus reduced, so 'by type η After the transistor 13 amplifies the voltage at the output terminal 2, it will reduce the voltage at point c. When the detected input signal L1 is lower than the ground potential, it is received by the input terminal 1. As described above, the second input F potential of the CMOS type differential amplifier circuit 14 and the potential of the first input terminal E are respectively pulled up to a potential L2. And L3. However, the potential difference of the potential L2 is lower than the potential L3', and the potential difference between the two ends of the PM0S transistor is increased, thereby reducing the voltage at the point D. Therefore, the difference in the potential of the two ends of the PM0S transistor 11 at the point c is high, When the potential change of Δν2 is low, AVI will be raised. The result is that the potential of the output terminal 2 is low, as shown in the second figure. When the input signal L is equivalent to the ground potential, the potential of the second input terminal E of the CM0S and the potential of the first input terminal F are equal, so the potential of the output terminal 2 is undetermined; the potential of the output terminal 2 will be based on the front and rear The status changes accordingly. For example, if the input signal L rises from below the ground potential to 200916796, the potential of the output terminal 2 will change from a low state to a high state, or if the input signal L is high. When the ground potential is lower than the ground potential, the potential of the output terminal 2 will change from a high state to a low state, so that when the input signal passes through the ground, the circuit can provide a function of detecting the ground potential crossover. SUMMARY OF THE INVENTION The present invention discloses a detection circuit for detecting an input signal crossover ground potential or a VCC power supply potential. When the circuit uses the detection crossover ground potential, the circuit includes two PMOS transistors, and the two pM0S The transistors are respectively connected to two NM0S transistors, the two pm〇s transistors are connected to have a source, and the two sources are connected to a power supply potential 'the gate of the second PM〇s transistor and the drain phase Connected, the first NMOS transistor has a source like the input terminal and a drain like the output terminal, the source retracts an input signal, and the first NMOS transistor has a source ground; the second transistor The gate is connected to the bias voltage and is also connected to a bias voltage; if the input terminal is disposed at the source of the first PMOS transistor and the source of the first NM 〇s transistor is grounded, the circuit can also be used To detect the power supply potential crossover. The detection circuit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings. [Embodiment] As described in the prior art, the detection circuit of the crossover ground potential or the crossover Vcc includes 13 transistors and 5 current sources, so the conventional detection circuit is quite complicated and high current consumption. The device for battery power 200916796 is disadvantageous. For the device for supplying power to the battery, the present invention designs a circuit comprising only four transistors and two current sources, which can save power consumption, as shown in the second figure, which is the grounding of the first embodiment of the present invention. The potential detecting circuit is a detecting circuit composed of two PM0S transistors Pi, P2 and two _s transistors N1, N2. In the circuit, the source of the PM0S transistors Pi, P2 are commonly connected to a power source Vcc, the two gates are connected, and the two gates are respectively associated with the NM0S transistor N1 and the NM0S transistor N2. The drain is connected to the pole, and the gate of the 'PM0S transistor P2 is connected to its own drain. The gates of the transistors N1 and N2 are connected to a bias signal bias, nm〇s transistor. The source of N2 is grounded, but the source of the transistor N1 is connected to an input signal IN, and the drain of the NM0S transistor N1 is used as an output terminal OUT. The operation of the crossover ground potential detecting circuit is as follows: Please refer to the second b diagram and the second c diagram simultaneously, when the potential of an input signal νίΝ is higher than the ground potential or the input terminal is floating, when it is higher than the NM0S transistor N2 The potential Vms of the starting potential VtN2 is applied to the gates of the NM0S transistors N1, N2, that is, the Ns transistor N2 is in the startup state 'and enters the tri-state' but the 〇s transistor Ni is in the off state' because VBIAS-VtNl - VlN< 0, thus generating 丨2 and Ιι= 0 'no current flows through the PMOS transistor P1, thus pulling the potential of the output out to VCC. When the potential of the input signal VlN decreases to near the ground potential (>〇+), the sum of VBIAS-VtNl - VlN is slightly larger than 〇, and the current 1 starts to flow ie Ιι笑0' but still less than 12, in this case Next, Vd2 < vcc _ 1+ 200916796 abs(Vtp2), in abs(Vtp2), Vs〇+abs(Vtp2) of Vs〇 are the absolute values of a starting voltage and a PM〇s transistor p2 source respectively The voltage to the gate 'PM0S transistor pi, P2 will enter a saturated state, so the voltage yQUT of the output terminal out is still pulled close to vcc. When the potential of the input signal VIN is equal to the ground potential, the circuit becomes a current mirror. Therefore, the voltage Vot of the output terminal OUT is at VCC and GND. When the potential of the input signal Vin is lower than the ground potential, [> I2 ' and V(10) and Vbus will bring the NM0S transistor N1 into a saturated state, and the voltage ν 〇υτ of the output terminal out remains at a low state. Therefore, the voltage Vout of the output terminal ουτ will change from high to low, or from low to high, and the input signal can be detected when it crosses the ground potential. The above embodiments are established in the NM0S transistor N1, and the size of N2 is equal. 'If the size ratio of the NM0S transistor N1 is different from that of the NM〇s transistor N2, the high crossover potential or the crossover potential can be adjusted, not limited to The crossover of the ground potential is measured by Y. The above circuit system can also be changed as follows to detect an input signal IN of the VCC potential. As shown in the fourth figure, the number, form and connection mode of the transistor are similar to those of the third a picture, except that the input terminal is in For the second preferred embodiment of the present invention, the input terminal IN is disposed at the source of the PMOS transistor P1, and the description of the input signal IN across the VCc detection circuit will be described in detail below. Narrative. Please refer to the fourth figure. When the voltage of the input signal IN is grounded or lower than the ground potential, the voltage VBiAS higher than the NM0S transistor N2 voltage ytN2 will be applied to the gate of the NM0S transistor N2, N1 because vBus-VtN2 > 0, so the NM0S transistor N2 is turned on and puts into a three-state, at this time, the voltage 200916796 voltage Vd2 < VCC - VsGP2+ abs (VtP2), a constant current 12 flows through the NMOS transistor N2 to the ground, no The current flows through the PMOS transistor PI (l1 = 0) and the output voltage OUT remains low. When the potential of the input signal IN is pulled up by the ground potential (still lower than VCC), the current begins to flow, and the current flows through the NM0S transistor N1 to the ground, and the Vbus voltage and the current i^ NMOS transistor N1 enter a three-state, at this time ΐκ< ; Ιζ 'The voltage at the output OUT therefore remains low. When the potential of the input signal in is equal to VCC, the circuit becomes a current mirror 'The current mirror has a mirror current Ιι'. The mirror current I through the PMOS transistor P1 is equal to the reference current I2 through the PMOS transistor P2. The potential of the output terminal 〇υτ is pulled up to VCC, so the input signal in across the VCC potential will be detected. Please refer to the fourth b diagram and the fourth c diagram, the input signal changes and the output signal changes. The advantages of the present invention are as follows: 1. Since the circuit of the present invention is composed of only four transistors, the present invention can greatly reduce current consumption with respect to the prior art. 2. Only, the channel width length ratio of the transistor (w/l) ni/(w/l>2, can increase or decrease the detection point of the crossover potential. The present invention uses the example _ 'It is intended to limit the spirit of the present invention and (4) to the above-mentioned implementation. Therefore, the modifications made by the spirit of the present invention should be included in the scope of the following patent application. Brief description of the formula] The first figure, the detection circuit of the traditional ground potential crossover; the second a diagram and the second b diagram, according to the input and output potential of the circuit of the first diagram change; the third a diagram, according to the invention An embodiment of the detection circuit for crossing the ground potential; the third b and the third c, according to the input and output potential of the circuit of the third a; the fourth a picture, according to the second embodiment of the present invention Crossover Vcc potential detection circuit; fourth b diagram and fourth c diagram, according to the input and output potential of the circuit of the fourth diagram a. [Main component symbol description] 11 200916796 1, IN input terminal 2, OUT output Terminal F first input E second input 3 power supply potential 6, 8, 9, 13 N-type transistor 5, 7, 10, 11, 12, 15, 16, 17, 18 P-type transistors A, B, C, D, D2 voltage point 14 differential amplifier circuit I〇, Iref, II, h current L > LI ' L2, L3, L4 signal
Vin輸入訊號 V〇ut輸出訊號 L2、L3、Μ卜 M2、VD2、VSG、VSGP2 電壓電位 PI、P2 PM0S電晶體Vin input signal V〇ut output signal L2, L3, M Bu M2, VD2, VSG, VSGP2 voltage potential PI, P2 PM0S transistor
Nl、N2 NM0S電晶體Nl, N2 NM0S transistor
Vcc電源 BIAS偏壓訊號Vcc power supply BIAS bias signal
VtN2起始電位 GND接地電位 12VtN2 start potential GND ground potential 12