1342402 九、發明說明： ' 【發明所屬之技術領域】 ‘ 本發明係關於一憤測電路，特別是指接地電位交越搞 測（或稱絲接地電位價測），該電路僅包括四個電晶體， • 且該四個電晶體僅具有二個電流源，因此本發明所設計之 , 電路可大大減少電源之消耗。 【先前技術】 請參照第一圖，其係傳統靠一單電源3以及〗3個電晶 • 體執行接地電位交越(gr〇und voltage crossing)之偵測電 路，該13個電晶體構成5個電流源，在第一圖中，編號i 係一輸入端’編號2係一輸出端；編號14係一 CM〇s_tfpe 差動放大電路，其係由p型電晶體7、1〇、u以及n型電 晶體8、9所組成的；p型電晶體18相當於—第一電位位 移器，視同一第一源極追隨器，以及p型電晶體17相當於 第二電位位移器，視同一第二源極追隨器。 έ亥電路之作動原理說明如下：藉由—電源電位3啟動 φ η型電晶體6 ’因此Α點電壓被往下拉，進而维梓陌定 P型電晶想15、7、16'5、12之閘極電位==二 點電位’故電晶體15、7、16、5、12提供了 5個怪定電流 源，B點之電壓因此維持穩定。 P型電晶體17係一個源極追隨器，其具有一個閘極接 - 地’其作動如同一位移電壓器用以提供一拉升殘餘電壓 (residual voltage)之功能，其可將E點之殘餘電壓拉升 以提供CMOS type差動放大電路14第一輸入端之輸入電 壓，P型電晶體18亦係一個源極追隨器，且其作動如同一 5 1342402 賴位移H，祕接受-輸人端丨饋人待制之輸入訊 ' 號’ ”電晶體18與P型電晶體17具有相同之特性。 因N型電晶體8、9構成-電流鏡，所以u(Iref)通過 P型電晶體1G時’將與電流12(1。)通過p型電晶體u時 相同。 。_時參照第二A圖以及第二B圖，待_之輸入訊 號L1比接地電位向時，為輸入端丨所接收，CM〇s仿卯差 動放大電路14之第二輸入端F電位藉由拉升位移電位18 φ 被拉升至一電位L2，同樣地，CMOS type差動放大電路14 之第一輸入端E接地電位藉由拉升位移電位I?被拉升至一 電位L3 ’當電位L2高於電位L3時，PM0S電晶體11二端 之電位差因此減低’因此，藉由n型電晶體13放大輸出端 2之電壓後，將減少C點之電壓。 當待偵測之輸入訊號L1低於接地電位時為輸入端1 所接收’如上述’ CMOS type差動放大電路14之第二輸入 端F電位與第一輸入端E電位被分別拉升至一電位L2與 • L3。然而’電位L2係低於電位L3，PM0S電晶體1〇二端 之電位差因此增加，因而使得D點電壓減少，因此，在c 點之PM0S電晶體11二端電位差值係高的，Δν2的電位變 化低時，將使Δνΐ升高，結果是輸出端2電位低，其情形 如第二Β圖所示。 . 當輸入訊號L相當於接地電位時，CMOS之第二輸入端 E之電位以及第一輸入端F之電位係相等的，因此輸出端2 之電位係未定的；輸出端2之電位將依據其前後狀態作相 對應之改變，例如：如輸入訊號L從低於接地電位升高至 6 高於接地電位，輸出端2之電位將由一低狀態改變為一高 狀態’或是如輸入訊號L從高於接地電位降低至低於接地 電位’輸岀端2之電位將由一高狀態改變為一低狀態，因 此當輸入訊號通過接地時’該電路可提供一偵測接地電位 交越之功能。 【發明内容】 本發明係揭露一偵測電路，偵測一輸入訊號交越接地 電位或VCC電源電位，當電路使用偵測交越接地電位時， 該電路包括二個PMOS電晶體，該二PMOS電晶體分別連接 於二個NMOS電晶體，該二PMOS電晶體接具有一源極，且 該二源極連接於一電源電位，第二PM〇s電晶體之閘極與汲 極係相連接的’第一 NM0S電晶體具有一如同輸入端之源極 以及一如同輸出端之汲極，該源極收回一輸入訊號，而第 二NM0S電晶體具有一源極接地；該二NM〇s電晶體之閘極 係相連接的’且亦連接於一偏電壓；若輸入端設置於第一 PMOS電晶體之源極，且該第一 NM〇s電晶體之源極係接地 的’該電路亦能夠用來偵測電源電位交越。 關於本發明所述之偵測電路，可以藉由以下發明詳述 及所附圖式，得到進一步的瞭解。 【實施方式】 如習知技術所述，不論交越接地電位或交越Vcc之偵 測電路皆包含13個電晶體以及5個電流源，因此，傳統之 偵測電路係相當複雜且高電流消耗的’對於電池供給電力 1342402 之設備是不利的。 針對電池供給電力之設備，本發明設計出一電路，僅 包含四個電晶體以及二個電流源，可節省電源消耗，如第 二a圖所示’其係本發明第—實施例交越接地電位之侦測 電路，係由二個PMOS f晶體P1，P2以及二個_s電晶體 Ml，N2.所構成之偵測電路。 曰 在該電路卜該PM0S電晶體P1，P2之源極係共同連 接於-電源Vex，該二閘極係、相連接的，且該二汲極係各 別與NM0S電晶體N1與NM0S電晶體N2之汲極相連接Γ另 外，PM0S電晶體P2之閑極更與其本身之錄相連接，_ 電晶體Nl，N2之閘極係共同連接於一偏壓訊號BUS，nm〇s 電晶體N2之源極係接地的，但NM〇s電晶體N1之源極係與1342402 IX. Description of the invention: ' [Technical field to which the invention pertains] ' The present invention relates to an intrusion circuit, in particular to a ground potential crossover test (or wire ground potential price measurement), the circuit includes only four electricity The crystal, • and the four transistors have only two current sources, so the circuit designed by the present invention can greatly reduce the power consumption. [Prior Art] Please refer to the first figure, which is a conventional detection circuit for ground potential crossover by a single power supply 3 and three electro-optical bodies. The 13 transistors constitute 5 In the first figure, the number i is an input terminal 'number 2 is an output terminal; the number 14 is a CM 〇 s_tfpe differential amplifier circuit, which is composed of p-type transistors 7, 1 〇, u and N-type transistors 8, 9; p-type transistor 18 is equivalent to - the first potential shifter, depending on the same first source follower, and p-type transistor 17 is equivalent to the second potential shifter, depending on the same Second source follower. The operation principle of the circuit is explained as follows: by the power supply potential 3, the φ η-type transistor 6 ' is activated, so the voltage of the Α point is pulled down, and the P 梓 梓 梓 梓 想 想 15 15 15 15 15 15 15 15 15 15 15 15 15 15 The gate potential == two-point potential', so the transistors 15, 7, 16, 5, 12 provide five strange current sources, and the voltage at point B remains stable. P-type transistor 17 is a source follower having a gate-ground' operation as the same displacement voltage device for providing a residual voltage, which can reproduce the residual voltage at point E. Pulling up to provide the input voltage of the first input end of the CMOS type differential amplifier circuit 14, the P-type transistor 18 is also a source follower, and its actuation is the same as 5 1342402 lag displacement H, the secret accepts - the input terminal The transistor 18 has the same characteristics as the P-type transistor 17. Since the N-type transistors 8, 9 constitute a current mirror, u(Iref) passes through the P-type transistor 1G. 'It will be the same as when the current 12 (1.) passes through the p-type transistor u. When referring to the second A picture and the second B picture, the input signal L1 of the _ is _ received by the input terminal The potential of the second input terminal F of the CM〇s pseudo-amplifier amplifier circuit 14 is pulled up to a potential L2 by the pull-up displacement potential 18 φ. Similarly, the first input terminal E of the CMOS type differential amplifier circuit 14 The ground potential is pulled up to a potential L3 by pulling up the displacement potential I? 'When the potential L2 is higher than the potential L3 The potential difference between the two ends of the PM0S transistor 11 is thus reduced. Therefore, after the voltage of the output terminal 2 is amplified by the n-type transistor 13, the voltage at the point C is reduced. When the input signal L1 to be detected is lower than the ground potential, The potential of the second input terminal F of the CMOS type differential amplifier circuit 14 received by the input terminal 1 and the potential of the first input terminal E are respectively pulled up to a potential L2 and • L3. However, the potential L2 is lower than the potential. L3, the potential difference between the two ends of the PM0S transistor is increased, thus reducing the voltage at point D. Therefore, when the potential difference between the two ends of the PM0S transistor 11 at point c is high, and the potential change of Δν2 is low, the Δν is increased. If the input signal L is equivalent to the ground potential, the potential of the second input terminal E of the CMOS and the potential of the first input terminal F are equal. Therefore, the potential of the output terminal 2 is undetermined; the potential of the output terminal 2 will be changed according to the front and rear states, for example, if the input signal L rises from below the ground potential to 6 above the ground potential, the output terminal 2 potential will be a low Change to a high state 'or if the input signal L decreases from above ground potential to below ground potential', the potential of the input terminal 2 will change from a high state to a low state, so when the input signal passes through the ground, the circuit The invention provides a function for detecting a ground potential crossover. SUMMARY OF THE INVENTION The present invention discloses a detecting circuit for detecting an input signal crossover ground potential or a VCC power supply potential. When the circuit uses the detection crossover ground potential, The circuit includes two PMOS transistors, the two PMOS transistors are respectively connected to two NMOS transistors, the two PMOS transistors are connected to have a source, and the two sources are connected to a power supply potential, and the second PM 〇s The first NMOS transistor connected to the gate of the transistor has a source like the input terminal and a drain like the output terminal, the source retracts an input signal, and the second NMOS transistor has a source is grounded; the gates of the two NM〇s transistors are connected to each other and are also connected to a bias voltage; if the input end is disposed at the source of the first PMOS transistor, and the first NM〇s is Source of crystal Ground 'also can be used to detect the circuit power supply potential crossover. The detection circuit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings. [Embodiment] As described in the prior art, the detection circuit of the crossover ground potential or the crossover Vcc includes 13 transistors and 5 current sources, so the conventional detection circuit is quite complicated and high current consumption. 'The equipment for the battery to supply power 1342402 is unfavorable. For the device for supplying power to the battery, the present invention designs a circuit comprising only four transistors and two current sources, which can save power consumption, as shown in FIG. 2A, which is the grounding of the first embodiment of the present invention. The potential detecting circuit is a detecting circuit composed of two PMOS f crystals P1, P2 and two _s transistors M1, N2. In the circuit, the source of the PIOS transistors P1, P2 is commonly connected to the - power source Vex, the two gates are connected, and the dipoles are respectively connected to the NM0S transistor N1 and NM0S transistors. In addition, the idle pole of the P0O transistor P2 is connected to its own video, and the gates of the transistors N1 and N2 are commonly connected to a bias signal BUS, nm〇s transistor N2. The source is grounded, but the source of the NM〇s transistor N1 is
一輸入訊號IN相連接’ NM0S電晶體N1之汲極作為一輪出 端 out 。 ‘ 月’J 該交越接地電位偵測電路之運作說明如下：請同時參 照第三b圖以及第三c圖，當一輸入訊號Vin之電位高於接 地電位或輸入端浮置’當高於NM0S電晶體N2啟始電位VtN2 的電位VBIAS施加於NM0S電晶體Nl、N2之閘極，即NM〇s電 晶體N2係呈啟動狀·％ ’且進入二態，但電晶體Ni 係呈關閉狀態’因為Vbias-Vwi - ViN〈 〇，因此產生12而 0 ’沒有電流通過PM0S電晶體P1 ’因而將輸出端〇υτ 的電位拉升至VCC。 當輸入訊號νΙΝ的電位減少至接近接地電位(>〇+)時， VBiAS-VtN丨-Vin的總合會稍大於〇’且電流^開始流動i e.， 1#0 ’但仍然小於12，在這個狀況下，vD2 < VCC - Vsc+ s abs(VtP2) ’ 在 abs(Vtp2)，Vsc 的 Vscrf abs(VtP2)分別係一 啟始電壓的絕對值以及一 PM〇s電晶體P2源極至閘極的電 壓；PM0S電晶體Pl，P2將進入一飽和狀態，因此輸出端 OUT的電壓Vwr仍然拉升至接近vcc。 當輸入訊號VlN的電位等於接地電位時，該電路變成一 電流鏡，因此I,，輸出端OUT的電壓Vm在VCC以及 GND之中。當輸入訊號vIN的電位低於接地電位時，h > I2 ’且Vinfl與VbIAS將使NM0S電晶體N1進入一飽和狀態，輸 出端OUT的電壓Vout仍然維持在低狀態。因此，輸出端out 的電壓Vour將由高轉為低，或是由低轉為高，輸入訊號ViN 交越接地電位時將能夠被偵測到。 上述之實施例係建立於NM0S電晶體N1，N2的大小相 等’若NM0S電晶體N1的大小比例與NM〇s電晶體N2不同， 則可調高交越電位或調低交越電位，不限於接地電位之交 越偵測。 上述電路係也可以如下變化以偵測一交越vcc電位之 輸入訊號IN如第四a圖所示，電晶體的數量，形式以及連 接方式與第三a圖相似’不同之處在於輸入端IN的位置， 請參照第四圖，其係本發明之第二最佳實施例，輸入端IN 係設置於PM0S電晶體P1之源極，跨ν(χ偵測電路之輸入 訊號IN之說明將於以下詳細敘述。 請參照第四圖’當輸入訊號IN之電壓係接地的或低於 接地電位’高於顺〇S電晶體N2電壓VtN2之電壓Vms將應用 於NM0S電晶體N2，N1之閘極，因為y_-vtN2 > 〇，因此 NM0S電晶體N2係呈開啟狀態，且使其進入三態，此時電 壓 VD2 < VCC - VSGp2+ abs(Vtp2)，一恆定電流 12流通過 NMOS 電晶體N2至接地，沒有電流流通過PMOS電晶體Pi (I1 = 〇)，輸出電壓OUT係維持低狀態。 當輸入訊號IN之電位由接地電位拉升時（仍然低於 VCC) ’電流I,開始流動，且流通過NM0S電晶體N1至接地， Vms電壓以及電流I,使NM0S電晶體N1進入三態，此時I,〈〈 I2 ’因此輸出端OUT之電壓係維持低狀態。當輸入訊號in 之電位等於VCC時，該電路變為一電流鏡，該電流鏡具有 一鏡像電流L·’通過PM0S電晶體P1之鏡像電流I,係與通 過PM0S電晶體P2之參考電流I2相等的，輸出端0ϋτ之電 位被拉升至VCC，因此跨VCC電位之輸入訊號IN將被偵測 到’請參照第四b圖以及第四c圖，該輸入訊號改變且該 輸出訊號改變。 本發明之優點如下： 1. 因為本發明之電路僅由四個電晶體所構成，因此相對於 習知技術，本發明可大大減少電流消耗。 2. 只需改變電晶體之通道寬度長度比(w/l)ni/(w/l)n2，即 可調高或調低交越電位之偵測點。 本發明雖以較佳實例闡明如上，然其並非用以限定本 發明之精神與發·體僅止於上述實施烟。是以，在不 脫離本發明之精神與範__之敍，均應包括在下述 申請專利範圍内。 1342402 【圖式簡單說明】 第一圖’傳統接地電位交越之偵測電路； 第二a圖以及第二b圖，依據第一圖電路之輸入以及輸出 之電位改變； 第三a圖，依據本發明第一實施例交越接地電位之偵測電 路； 第三b圖以及第三c圖，依據第三a圖電路之輸入以及輸 出之電位改變； 第四a圖’依據本發明第二實施例偵測交越Vcc電位之偵 測電路； 第四b圖以及第四c圖，依據第四a圖電路之輪入以及 輸出之電位改變。 【主要元件符號說明】 1342402 1、IN輸入端 ^ /~\Τ ΤΤ» 4tK .1 I * A* z ' uu i ψήΐΆ^ F第一輸入端 E第二輸入端 3電源電位 6、8、9、13 N型電晶體 5、7、10、H、12、15、16、17、18 P 型電晶體 A、B、C、D、D2 電壓點 14差動放大電路 I〇、Iref、II、h 電流 L ' LI ' L2、L3、L4 訊號An input signal IN is connected to the drain of the NM0S transistor N1 as a round out terminal. 'Month' J The operation of the grounding potential detection circuit is as follows: Please refer to the third b and third c diagrams simultaneously, when the potential of an input signal Vin is higher than the ground potential or the input is floating 'When higher than The potential VBIAS of the NM0S transistor N2 start potential VtN2 is applied to the gates of the NM0S transistors N1 and N2, that is, the NM〇s transistor N2 is activated and %' and enters the binary state, but the transistor Ni is turned off. 'Because Vbias-Vwi - ViN< 〇, therefore produces 12 and 0 'no current flows through the PM0S transistor P1 ' and thus pulls the potential of the output 〇υτ to VCC. When the potential of the input signal νΙΝ decreases to near ground potential (>〇+), the sum of VBiAS-VtN丨-Vin is slightly larger than 〇' and the current ^ starts to flow i e., 1#0 'but still less than 12 In this case, vD2 < VCC - Vsc+ s abs(VtP2) ' In abs(Vtp2), Vsc's Vscrf abs (VtP2) are the absolute values of a starting voltage and a PM 〇s transistor P2 source, respectively. The voltage to the gate; the PM0S transistors P1, P2 will enter a saturation state, so the voltage Vwr at the output terminal OUT is still pulled up to near vcc. When the potential of the input signal V1N is equal to the ground potential, the circuit becomes a current mirror, so I, the voltage Vm of the output terminal OUT is between VCC and GND. When the potential of the input signal vIN is lower than the ground potential, h > I2 ' and Vinfl and VbIAS will bring the NM0S transistor N1 into a saturated state, and the voltage Vout of the output terminal OUT remains at a low state. Therefore, the voltage Vour of the output terminal out will change from high to low, or from low to high, and the input signal ViN will be detected when it crosses the ground potential. The above embodiments are established in the NM0S transistor N1, and the size of N2 is equal. 'If the size ratio of the NM0S transistor N1 is different from that of the NM〇s transistor N2, the high crossover potential or the crossover potential can be adjusted, not limited to The crossover detection of the ground potential. The above circuit system can also be changed as follows to detect an input signal IN of the crossover vcc potential. As shown in the fourth diagram, the number, form and connection mode of the transistor are similar to those of the third a diagram. The difference is that the input terminal IN Please refer to the fourth figure, which is a second preferred embodiment of the present invention. The input terminal IN is disposed at the source of the PIO transistor P1, and the crossover ν (the description of the input signal IN of the detection circuit will be Please refer to the fourth figure. 'When the voltage of the input signal IN is grounded or lower than the ground potential', the voltage Vms higher than the voltage of the transistor N2, VtN2, will be applied to the gate of the NM0S transistor N2, N1. Because y_-vtN2 > 〇, the NM0S transistor N2 is turned on and puts into a three-state, at which time the voltage VD2 < VCC - VSGp2+ abs(Vtp2), a constant current 12 flows through the NMOS transistor N2 To ground, no current flows through the PMOS transistor Pi (I1 = 〇), and the output voltage OUT remains low. When the potential of the input signal IN is pulled up by the ground potential (still below VCC), the current I starts to flow. And flow through the NM0S transistor N1 to ground, Vms The voltage and current I cause the NM0S transistor N1 to enter a three-state state. At this time, I, << I2 ', therefore, the voltage at the output terminal OUT remains low. When the potential of the input signal in is equal to VCC, the circuit becomes a current mirror. The current mirror has a mirror current L·' through the mirror current I of the PMOS transistor P1, which is equal to the reference current I2 passing through the PMOS transistor P2, and the potential of the output terminal ϋτ is pulled up to VCC, thus crossing the VCC potential The input signal IN will be detected. 'Please refer to the fourth b and fourth c diagrams, the input signal changes and the output signal changes. The advantages of the present invention are as follows: 1. Since the circuit of the present invention consists of only four electric The crystal is constructed, so that the present invention can greatly reduce the current consumption compared to the prior art. 2. It is only necessary to change the channel width to length ratio (w/l) ni / (w / l) n2 of the transistor, that is, or The detection point of the crossover potential is lowered. The present invention is exemplified by the preferred embodiment as described above, but it is not intended to limit the spirit and the body of the present invention to the above-mentioned implementation of the smoke. Therefore, without departing from the invention Both the spirit and the paradigm of __ should be included in the following application 1342402 [Simple diagram of the diagram] The first diagram 'traditional ground potential crossover detection circuit; the second a diagram and the second b diagram, according to the input and output potential of the circuit of the first diagram change; FIG. 3 is a diagram showing a detection circuit for crossing a ground potential according to a first embodiment of the present invention; a third b diagram and a third c diagram, wherein the input and output potentials of the circuit are changed according to the third diagram; FIG. 4A is in accordance with the present invention. The second embodiment detects the detection circuit of the crossover Vcc potential; the fourth b diagram and the fourth c diagram change according to the turn-in and output potentials of the circuit of the fourth diagram. [Main component symbol description] 1342402 1. IN input terminal ^ /~\Τ ΤΤ» 4tK .1 I * A* z ' uu i ψήΐΆ^ F First input terminal E Second input terminal 3 Power supply potential 6, 8, 9 , 13 N-type transistors 5, 7, 10, H, 12, 15, 16, 17, 18 P-type transistors A, B, C, D, D2 voltage point 14 differential amplifier circuit I〇, Iref, II, h current L ' LI ' L2, L3, L4 signal
Vin輸入訊號 V〇ut輸出訊號 L2、L3、Δν卜 AV2、VD2、VSG、VSGP2 電壓電位 PI、P2 PMOS電晶體 N1、N2 NMOS電晶體Vin input signal V〇ut output signal L2, L3, Δν Bu AV2, VD2, VSG, VSGP2 voltage potential PI, P2 PMOS transistor N1, N2 NMOS transistor
Vcc電源 BIAS偏壓訊號Vcc power supply BIAS bias signal
VtN2起始電位 GND接地電位VtN2 start potential GND ground potential