201232830 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種發光二極體裝置及其製造方法，特 別關於一種具有垂直電極結構之發光二極體裝置及其萝 方法。 ^。 【先前技術】 發光二極體（Light Emitting Diode，簡稱 LED)因其 具有高亮度、體積小、重量輕、不易破損、低耗電量和壽 命長等優點，所以被廣泛地應用各式顯示產品中，其發光 原理如下：絲一電壓於二極體±，驅使二極體裡的電子 與電洞結合，此結合所產生的能量是以光的形式釋放出來。 第1圖為—f知具有藍寶石（sapphire)基底之發光二極 體10的剖面結構示意圖。該發光二極體1〇包括一藍寶石 基底12、-緩衝層13、—半導體元件層15、—第二電極 20以及第一電極22。半導體元件層15包括一 N型半導體 層14、一發光層16以及—p型半導體層】8。該發光二極 體10的形成方式係在藍寳石基底12上依序形成該缓衝層 13 N 土半導體層、發光層、以及p型半導體層18， 然後再其一側侧一凹槽露出部份之N型半導體層最 後鑛上金屬層後以光罩微影姓刻，以 14及P型半導體刀g 1牛導體層 千等租層18形成弟一電極20及第二電極22。竽 第：電極2〇及第二電極U皆在同-側(基底的反側)，： =安排的原因係為監寳石基底不導電’無法在晶片之反面 裝造電極。如此-來，除了必需犧牲部份發光面積來形成 9109A-A35682TWF__TN201〇〇〇56 4 201232830 N型半導體層14的接觸電極使得該發光二極體10之有效 發光面積減少外，如此結構亦會造成電流集中於兩電極 20、22之間的最短路徑25而無法均勻分佈至整個發光二 極體10，使得發光二極體10的整體發光效率不佳而且發 光不均勻。 為解決上述問題，一習知技術為達到垂直電極的設 計’係先在監寶石基底上形成所需的蟲晶層5然後在猎由 使用雷射剝離(laser lift-off)製程進一步將發光二極體晶片 φ 的藍寶石基底移除，並改以散熱較佳基板如石夕基底取代。 然而，上述作法之製造良率並不高，且使得製造成本大幅 提高。 基於上述，業界亟需一種創新的發光二極體裝置來解 決上述問題。 【發明内容】 本發明提供一種發光二極體裝置，包含一絕緣基底， 鲁 具有一上表面及一下表面；一圖形化導電層，配置於該絕 緣基底之部份上表面；一緩衝層，配置於該絕緣基底未被 該圖形化導電層所覆蓋的上表面；一第一半導體層，配置 於該緩衝層之上；一發光層，配置於該第一半導體層之上； 一第二半導體層，配置於該發光層之上；以及，一電極， 配置於該第二半導體層之上。 此外，本發明亦提供一種發光二極體裝置製造方法， 包含：提供一絕緣基底，該絕緣基底具有一上表面及一下 表面；形成一圖形化導電層於該絕緣基底之部份上表面； 9109A-A35682TWF TN20100056 5 201232830 形成一緩衝層於該絕緣基底未被該圖形化導 上表面；形成一第一半導體層於該緩衝層之上；^一良 ίΐί:第::導體:之上;形成一第二半導體層於該 之上’以及，形成-電極’配置於該第二半導體層之 ，讓本發明之上述和其他目的、特徵、和 顯易个重，下文特舉出較佳實施例，並配合 細說明如下： 八作评 【實施方式】 為解決先前技術所遭遇到的問題，本發明提供 製造方法’使得具有絕緣基底的發光： 極體裝置具有垂直電極的架構，除了不需犧牲部份發光區 域（降低有效發光面積）外’可改善電子流有效注入發光層 的均勻性（使電流流經途徑均勻分佈至整個發光二 : 提昇整體發光效率。 ； 根據本發明一實施例，該發光二極體裝置可包含：一 、'邑緣基底’具有-上表面及一下表面；一圖形化導電層， 配置於該絕緣基底之部份上表面；一緩衝層，配置於該絕 緣基底未被該圖形化導電層所覆蓋的上表面；一第一半導 體層，配置於該緩衝層之上；—發光層，配置於該第一半 導體層之上；-第二半導體層，配置於該發光層之上；以 及，-電極，配置於該第二半導體層之上。根據本發明另 -實施例’該圖形化導電層更可以進一步延伸至該絕緣基 底之侧壁。此外，該圖形化導電層亦可進一步延伸以覆蓋 9109A-A35682TWF_TN201〇〇〇56 6 201232830 .：f 該絕緣基底之部份下表面。 " 本發明所述之發光二極體裝置其絕緣基底之上表 面，係被該圖形化導電層及該緩衝層完全覆蓋，而該緩衝 層係可進一步坦覆性覆蓋該圖形化導電層。值得注意的 是，形成於該基底上表面的圖形化導電層，至少一部份係 緊鄰該上表面的邊界。此外，該圖形化導電層的設計重點 在於，該形成於該基底上表面的圖形化導電層係佔該基板 上表面面積的10-50%。若該圖形化導電層佔該基板上表面 • 面積的比率係小於10%時，則會使得該發光二極體裝置之 電流分布集中，導致電場均勻度降低；相反的，該圖形化 導電層佔該基板上表面面積也不宜太大，否則會使得形成 於基底上表面的緩衝層所佔的基板上表面面積過低，影響 到後續膜層（發光層、第一半導體層、第二半導體層）的磊 晶品質。該圖形化導電層之可配置於該基板上表面的周圍 (緊鄰該上表面的邊界），或是具有格狀結構。該緩衝層之 厚度可大於或等於該圖形化導電層，缓衝層較佳係坦覆性 ® 覆蓋該圖形化導電層。該電極係包含一透明電極、一金屬 電極、或其組合。 本發明所述之發光二極體裝置可更包含一導線架，該 導線架可具有一第一電路及一第二電路，其中該絕緣基底 係配置於該導線架上，且該圖形化導電層與該第一電路電 性接觸。此外，該電極與該第二電路電可藉由一導線達到 電性連結。 以下將配合圖示，以說明根據本發明所提供之發光二 極體裝置及其製造方法。 9109A-A35682TWF TN20100056 7 201232830 根據本發明一實施例，發光二極體裝置的製造方法包 含以下步驟： 首先，請參照第2A圖，提供一絕緣基底102，該絕緣 基底102具有一上表面101、一下表面103、及側壁104， 請參照第2B圖，係為沿第2A圖A-A’切線之剖面結構。該 絕緣基底102可為習知之絕緣基底，例如藍寶石（氧化鋁） 基底、氮化鋁基底、或氧化鋅基底等。 接著，請參照第3A圖，形成導電層於該絕緣基底102 之上表面101，並進行圖形化，得到一圖形化導電層106。 值得注意的是，該圖形化導電層106並未覆蓋該絕緣基底 102之整個上表面101因此，在形成該圖形化導電層106 於基板後，仍會露出未被覆蓋的絕緣基底102上表面101， 請參照第3B圖，係為沿第3A圖A-A’切線之剖面結構。該 圖形化導電層106可具有格狀、螺旋、圓環、指叉等、點 狀或條狀結構，具體圖形並無限定，可視需要加以變化， 如第4圖及第5圖所示。此外，該圖形化導電層亦可僅配 置於該基板上表面的周圍（緊鄰該上表面的邊界），或再進 一步的覆蓋該基板的侧邊，如第6圖所示。該圖形化導電 層106可包含透明或不透明之導電材料，例如：銦錫氧化 物（ITO) 、10在辛氧化物（IZO)、在辛在呂氧化物（AZO)、氧化在辛 (ΖηΟ))、纪、始、鎳、金、銀、I呂、鎮、銅、或其組合。 此外，該圖形化導電層106亦可為一複合膜層，例如進一 步包含歐姆接觸材料、擴散阻障層、金屬結合層（metal bonding layer)、反射層、或上述之組合。 根據本發明另一實施例，請參照第7A圖，在形成該 9109A-A35682TWF TN20100056 8 201232830 圖形化導電層106時，較佳’可同時將該圖形化導電層106 形成於該絕緣基底102之側壁1〇4，以利後續發光二極體 裝置的電性連結。請參照第7B圖，係為沿第7A圖A-A’ 切線之剖面結構’該圖形化導電層1〇6係由該絕緣基底102 上表面101的邊界處進一步延伸至該絕緣基底1〇2之側壁 104。該圖形化導電層1〇6可在晶圓步驟（未進行切割前）或 晶片步驟（將晶圓切割成數片晶片後）中形成，形成方式可 為熱蒸鍍、濺射或電漿強化式化學氣相沉積方式。舉例來 # 說，若為晶圓步驟中形成，請參照第8圖，可預先在該晶 圓200上形成溝道或複數個貫孔15〇，當形成該導電層於 晶圓200之時’該導電層材料除了會形成於基底1〇2之上 表面外’更可藉由該溝道或貫孔丨5〇而延伸並覆蓋該絕緣 基底102之侧壁104。再者，在形成該圖形化導電層1〇6 於該絕緣基底102之上表面丨〇丨及側壁1〇4的步驟後，可 更包含形成一底導電層107於該絕緣基底1〇2之部份下表 面103並與形成於側壁的圖形化導電層1〇6電性接觸，換 籲 言之，可使得該圖形化導電層106進一步延伸至覆蓋該絕 緣基底102之部份下表面1 ，請參照第9圖。 在此以第3A圖所示結構為例，接續描述本發明所述 之該發光二極體裝置的製造。接著，請參照第10A圖，形 成一緩衝層108於該絕緣基底ι〇2未被該圖形化導電層ι〇6 所覆蓋的上表面101。該缓衝層108之厚度可大於或等於 該圖形化導電層106，請參照第10B圖，係為沿第丨〇A圖 A-A’切線之剖面結構。此外，根據本發明另一實施例，該 緩衝層108的厚度較佳係大於該圖形化導電層1〇6,並坦 9109A-A35682TWF TN20100056 n201232830 VI. Description of the Invention: [Technical Field] The present invention relates to a light-emitting diode device and a method of fabricating the same, and more particularly to a light-emitting diode device having a vertical electrode structure and a method thereof. ^. [Prior Art] Light Emitting Diode (LED) is widely used in various display products because of its high brightness, small size, light weight, low damage, low power consumption and long life. The principle of illumination is as follows: the filament voltage is applied to the diode ±, which drives the electrons in the diode to combine with the hole, and the energy generated by the combination is released in the form of light. Fig. 1 is a schematic cross-sectional view showing a light-emitting diode 10 having a sapphire substrate. The light-emitting diode 1 includes a sapphire substrate 12, a buffer layer 13, a semiconductor element layer 15, a second electrode 20, and a first electrode 22. The semiconductor element layer 15 includes an N-type semiconductor layer 14, a light-emitting layer 16, and a -p-type semiconductor layer 8. The light-emitting diode 10 is formed by sequentially forming the buffer layer 13 N-semiconductor layer, the light-emitting layer, and the p-type semiconductor layer 18 on the sapphire substrate 12, and then forming a recessed portion on one side thereof. After the N-type semiconductor layer is finally mineralized on the metal layer, the photoreceptor is engraved with a photomask, and the first electrode 20 and the second electrode 22 are formed by a 14-layer and a P-type semiconductor knife g1.竽 No.: Electrode 2〇 and second electrode U are all on the same side (the opposite side of the substrate), : = The reason for the arrangement is that the gemstone substrate is not electrically conductive. 'The electrode cannot be fabricated on the reverse side of the wafer. In this way, in addition to having to sacrifice part of the light-emitting area to form the contact electrode of the 9109A-A35682TWF__TN201〇〇〇56 4 201232830 N-type semiconductor layer 14, the effective light-emitting area of the light-emitting diode 10 is reduced, and the structure also causes current. The shortest path 25 between the two electrodes 20, 22 is concentrated and cannot be uniformly distributed to the entire light emitting diode 10, so that the overall luminous efficiency of the light emitting diode 10 is poor and the light emission is uneven. In order to solve the above problems, a conventional technique for achieving the design of a vertical electrode is to form a desired crystal layer 5 on a gemstone substrate and then further emit light by using a laser lift-off process. The sapphire substrate of the polar body wafer φ is removed and replaced with a heat-dissipating substrate such as a stone substrate. However, the manufacturing yield of the above method is not high, and the manufacturing cost is greatly increased. Based on the above, there is an urgent need in the industry for an innovative light-emitting diode device to solve the above problems. SUMMARY OF THE INVENTION The present invention provides a light emitting diode device including an insulating substrate having an upper surface and a lower surface, a patterned conductive layer disposed on a portion of the upper surface of the insulating substrate, and a buffer layer disposed An upper surface of the insulating substrate that is not covered by the patterned conductive layer; a first semiconductor layer disposed on the buffer layer; a light emitting layer disposed on the first semiconductor layer; a second semiconductor layer And disposed on the light emitting layer; and an electrode disposed on the second semiconductor layer. In addition, the present invention also provides a method for fabricating a light emitting diode device, comprising: providing an insulating substrate having an upper surface and a lower surface; forming a patterned conductive layer on a portion of the upper surface of the insulating substrate; 9109A -A35682TWF TN20100056 5 201232830 Forming a buffer layer on the insulating substrate without the patterned upper surface; forming a first semiconductor layer over the buffer layer; ^一良ίΐί::: conductor: above; forming a The above and other objects, features, and advantages of the present invention are set forth above, and the forming -electrode is disposed on the second semiconductor layer. Preferred embodiments are described below. In order to solve the problems encountered in the prior art, the present invention provides a manufacturing method to enable illumination with an insulating substrate: the polar body device has a vertical electrode structure, except that no sacrificial portion is required. The portion of the illuminating region (reducing the effective illuminating area) can improve the uniformity of the effective injection of the electron flow into the luminescent layer (to make the current flow evenly distributed to According to an embodiment of the invention, the light emitting diode device may include: a 'bending edge substrate' having an upper surface and a lower surface; a patterned conductive layer disposed on the light emitting diode device a portion of the upper surface of the insulating substrate; a buffer layer disposed on the upper surface of the insulating substrate not covered by the patterned conductive layer; a first semiconductor layer disposed on the buffer layer; - a light emitting layer disposed on Above the first semiconductor layer; a second semiconductor layer disposed on the light emitting layer; and an - electrode disposed on the second semiconductor layer. According to another embodiment of the present invention, the patterned conductive layer Further, the patterned conductive layer may further extend to cover 9109A-A35682TWF_TN201〇〇〇56 6 201232830 .:f part of the lower surface of the insulating substrate. The upper surface of the insulating substrate of the light emitting diode device is completely covered by the patterned conductive layer and the buffer layer, and the buffer layer can further cover the graphic Conductive layer. It is noted that at least a portion of the patterned conductive layer formed on the upper surface of the substrate is adjacent to the boundary of the upper surface. Further, the patterned conductive layer is designed to be formed on the substrate. The patterned conductive layer of the surface accounts for 10-50% of the surface area of the substrate. If the ratio of the patterned conductive layer to the upper surface area of the substrate is less than 10%, the light-emitting diode device is The current distribution is concentrated, resulting in a decrease in the uniformity of the electric field; on the contrary, the patterned conductive layer occupies the upper surface area of the substrate, and the surface area of the substrate occupied by the buffer layer formed on the upper surface of the substrate is too low. The epitaxial quality of the subsequent film layers (the light emitting layer, the first semiconductor layer, and the second semiconductor layer) is affected. The patterned conductive layer may be disposed around the upper surface of the substrate (close to the boundary of the upper surface) or have a lattice structure. The buffer layer may have a thickness greater than or equal to the patterned conductive layer, and the buffer layer preferably satisfies the patterned conductive layer. The electrode comprises a transparent electrode, a metal electrode, or a combination thereof. The LED device of the present invention may further include a lead frame, the lead frame may have a first circuit and a second circuit, wherein the insulating substrate is disposed on the lead frame, and the patterned conductive layer Electrically contacting the first circuit. In addition, the electrode and the second circuit can be electrically connected by a wire. Hereinafter, the illustration will be made to illustrate a light-emitting diode device and a method of manufacturing the same according to the present invention. 9109A-A35682TWF TN20100056 7 201232830 According to an embodiment of the invention, a method of manufacturing a light emitting diode device comprises the following steps: First, referring to FIG. 2A, an insulating substrate 102 having an upper surface 101 and a lower surface is provided. For the surface 103 and the side wall 104, refer to FIG. 2B, which is a cross-sectional structure taken along line AA' of FIG. 2A. The insulating substrate 102 may be a conventional insulating substrate such as a sapphire (alumina) substrate, an aluminum nitride substrate, or a zinc oxide substrate. Next, referring to FIG. 3A, a conductive layer is formed on the upper surface 101 of the insulating substrate 102, and patterned to obtain a patterned conductive layer 106. It should be noted that the patterned conductive layer 106 does not cover the entire upper surface 101 of the insulating substrate 102. Therefore, after the patterned conductive layer 106 is formed on the substrate, the uncovered insulating substrate 102 upper surface 101 is still exposed. Please refer to Figure 3B for the cross-sectional structure along the line A-A' of Figure 3A. The patterned conductive layer 106 may have a lattice, a spiral, a ring, a finger, etc., a dot or a strip structure, and the specific pattern is not limited, and may be changed as needed, as shown in Figs. 4 and 5. In addition, the patterned conductive layer may also be disposed only around the upper surface of the substrate (near the boundary of the upper surface), or further cover the sides of the substrate, as shown in Fig. 6. The patterned conductive layer 106 may comprise a transparent or opaque conductive material, such as: indium tin oxide (ITO), 10 in octyl oxide (IZO), in osmium oxide (AZO), oxidized in xin (ΖηΟ) ), Ji, Shi, Nickel, Gold, Silver, Ilu, Town, Copper, or a combination thereof. In addition, the patterned conductive layer 106 can also be a composite film layer, for example, further comprising an ohmic contact material, a diffusion barrier layer, a metal bonding layer, a reflective layer, or a combination thereof. According to another embodiment of the present invention, referring to FIG. 7A, in forming the 9109A-A35682TWF TN20100056 8 201232830 patterned conductive layer 106, it is preferable to simultaneously form the patterned conductive layer 106 on the sidewall of the insulating substrate 102. 1〇4, in order to facilitate the electrical connection of the subsequent light-emitting diode device. Please refer to FIG. 7B, which is a cross-sectional structure along the line AA' of FIG. 7A. The patterned conductive layer 1〇6 further extends from the boundary of the upper surface 101 of the insulating substrate 102 to the insulating substrate 1〇2. Side wall 104. The patterned conductive layer 1〇6 can be formed in a wafer step (before cutting) or a wafer step (after cutting the wafer into a plurality of wafers), which can be formed by thermal evaporation, sputtering or plasma strengthening. Chemical vapor deposition. For example, if it is formed in the wafer step, please refer to FIG. 8 , a channel or a plurality of through holes 15 形成 may be formed on the wafer 200 in advance, when the conductive layer is formed on the wafer 200 The conductive layer material may be formed by the channel or the via hole 〇5〇 and may cover the sidewall 104 of the insulating substrate 102 except for being formed on the upper surface of the substrate 1〇2. Furthermore, after the step of forming the patterned conductive layer 1〇6 on the upper surface of the insulating substrate 102 and the sidewalls 1〇4, the bottom conductive layer 107 may be further formed on the insulating substrate 1〇2. a portion of the lower surface 103 is in electrical contact with the patterned conductive layer 1〇6 formed on the sidewall, in other words, the patterned conductive layer 106 is further extended to cover a portion of the lower surface 1 of the insulating substrate 102. Please refer to Figure 9. Here, the structure shown in Fig. 3A will be taken as an example to describe the manufacture of the light-emitting diode device of the present invention. Next, referring to Fig. 10A, a buffer layer 108 is formed on the upper surface 101 of the insulating substrate ι2 which is not covered by the patterned conductive layer ι6. The buffer layer 108 may have a thickness greater than or equal to the patterned conductive layer 106. Referring to FIG. 10B, it is a cross-sectional structure along the line A-A' of FIG. In addition, according to another embodiment of the present invention, the thickness of the buffer layer 108 is preferably greater than that of the patterned conductive layer 1〇6, and is 9109A-A35682TWF TN20100056 n
一 U 201232830 覆性覆蓋該圖形化導電層1〇6,請參照第UA圖及第11B 圖（係為沿第11A圖A-A，切線之剖面結構）。本發明對所使 用之緩衝層108材質並無限定，可為習知之任何用於發光 二極體的緩衝材料，例如未摻雜的半導體層（可選自於皿— V族之化學元素、π —VI族之化學元素、贝族之化學元素、 IV-IV族之化學元素之任意組合）。 在此以第11A圖所示結構為例，接續描述本發明所述 之該發光二極體裝置的製造。接著，請參照第丨2A圖，形 成一半導體元件複合層115於該緩衝層1〇8,該半導體元 件複合層115依序包含一第一半導體層uo、一發光層 112、及一第二半導體層114，請參照第12B圖（係為沿第 12A圖A-A’切線之剖面結構）。該發光層in係為一半導體 材料層’可具有為多重量子井（Multiple Quantun Well， MQW)結構，可選自於]I —V族之化學元素、Π —VI族之 化學元素、IV族之化學元素、IV —IV族之化學元素、或其 組合，例如：AIN、GaN、AlGaN、InGaN、AlInGaN、GaP、 GaAsP、GalnP、AlGalnP、或 AlGaAs。該第一半導體層 110 及該第二半導體層114可分別為一 N型磊晶層及一 P型磊 晶層，當然其亦可互換，於此並不加以限制，其材質同樣 可分別選自於m — v族之化學元素、π — vi族之化學元 素、IV族之化學元素、IV_IV族之化學元素、或其組合。 舉例來說，若第一半導體層110為N型氮化鎵系半導體， 則第二半導體層114係為P型氮化鎵系半導體，若第一半 導體層110係為P型氮化鎵系半導體，則第二半導體層114 係為N型氮化鎵系半導體，且發光層112可為氮化鎵系半 9109A-A35682TWF TN20100056 10 201232830 導體。在形成該半導體元件複合層ii5的步驟後，接著， 形成一透明電極116於該第二半導體層114上，請參照第 13A圖及第13B圖（係為沿第13A圖A-A’切線之剖面結 構）。該透明電極116可為銦錫氧化物（ITO)、銦鋅氧化物 (IZO)、鋅铭氧化物（AZO)、氧化鋅（ZnO)或其結合，而其形 成方式可為熱蒸鍍、濺射或電漿強化式化學氣相沉積方 式。接著，形成一金屬電極118於該透明電極116之上， 得到一發光二極體晶片300，請參照第14A圖及第14B圖 • (係為沿第13A圖A-A’切線之剖面結構）。該金屬電極118 可為把、銘、鎳、金、銀、銘、鎢、銅、或其組合，而其 形成方式可為熱蒸鍍、濺射或電漿強化式化學氣相沉積方 式。 在完成該發光二極體晶片300之製造後，本發明所述 之該發光二極體裝置製造方法可更包含將該發光二極體晶 片300固合於一導線架120上，請參照第15圖，該導線架 上配置有已預先設計好之一第一電路125及一第二電路 • 127。在將該發光二極體晶片300固合於該導線架120，需 使該圖形化導電層106與該第一電路125的突出部接觸。 再者，可利用一導線129將該金屬電極118與該第二電路 127進行電性連結，請參照第16圖，如此一來，可達到驅 動該發光二極體晶片300的目的，得到一發光二極體裝置 400。A U 201232830 covers the patterned conductive layer 1〇6, please refer to the UA diagram and the 11B diagram (the section structure along the tangential line along the A-A of FIG. 11A). The present invention is not limited to the material of the buffer layer 108 used, and may be any buffer material for a light-emitting diode, such as an undoped semiconductor layer (which may be selected from a chemical element of the V-V group, π). - any combination of the chemical elements of the VI family, the chemical elements of the Be family, and the chemical elements of the IV-IV group). Here, the structure shown in Fig. 11A will be taken as an example to describe the manufacture of the light-emitting diode device of the present invention. Next, referring to FIG. 2A, a semiconductor device composite layer 115 is formed on the buffer layer 1〇8. The semiconductor device composite layer 115 sequentially includes a first semiconductor layer uo, a light emitting layer 112, and a second semiconductor. For layer 114, please refer to Fig. 12B (which is a cross-sectional structure along the line AA' of Fig. 12A). The light-emitting layer in is a semiconductor material layer' which may have a multiple quantum well ( MQW) structure, and may be selected from the group consisting of chemical elements of the group I-V, chemical elements of the group VI, and groups IV. A chemical element, a chemical element of Group IV-IV, or a combination thereof, for example, AIN, GaN, AlGaN, InGaN, AlInGaN, GaP, GaAsP, GalnP, AlGalnP, or AlGaAs. The first semiconductor layer 110 and the second semiconductor layer 114 are respectively an N-type epitaxial layer and a P-type epitaxial layer. Of course, they may be interchanged, and are not limited thereto, and the materials may also be respectively selected from the same. a chemical element of the m-va group, a chemical element of the π-vi group, a chemical element of the group IV, a chemical element of the group IV-IV, or a combination thereof. For example, when the first semiconductor layer 110 is an N-type gallium nitride-based semiconductor, the second semiconductor layer 114 is a P-type gallium nitride-based semiconductor, and the first semiconductor layer 110 is a P-type gallium nitride-based semiconductor. The second semiconductor layer 114 is an N-type gallium nitride-based semiconductor, and the light-emitting layer 112 may be a gallium nitride-based half 9109A-A35682TWF TN20100056 10 201232830 conductor. After the step of forming the semiconductor device composite layer ii5, a transparent electrode 116 is formed on the second semiconductor layer 114. Please refer to FIG. 13A and FIG. 13B (which is tangent to A-A' along FIG. 13A). Section structure). The transparent electrode 116 may be indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (AZO), zinc oxide (ZnO) or a combination thereof, and may be formed by thermal evaporation or sputtering. Shot or plasma enhanced chemical vapor deposition. Next, a metal electrode 118 is formed on the transparent electrode 116 to obtain a light-emitting diode wafer 300. Please refer to FIG. 14A and FIG. 14B (which is a cross-sectional structure along the line A-A' of FIG. 13A). . The metal electrode 118 may be a handle, a nickel, a gold, a silver, a metal, a tungsten, a copper, or a combination thereof, and may be formed by a thermal evaporation, sputtering or plasma enhanced chemical vapor deposition method. After the fabrication of the LED substrate 300 is completed, the method for fabricating the LED device of the present invention may further include bonding the LED wafer 300 to a lead frame 120. The lead frame is provided with a first circuit 125 and a second circuit 127 which are pre-designed. When the LED array 300 is bonded to the lead frame 120, the patterned conductive layer 106 is brought into contact with the protruding portion of the first circuit 125. Furthermore, the metal electrode 118 and the second circuit 127 can be electrically connected by a wire 129. Referring to FIG. 16, the LED chip 300 can be driven to obtain a light-emitting diode. Diode device 400.
此外，在本發明另一實施例中，係利用第7A圖所示 結構（圖形化導電層延伸至該絕緣基底102的側壁104)經由 第11A圖至14A圖所示之製造流程（依續成長緩衝層、N 9109A-A35682TWF TN20100056 11 201232830 型半導體層、發光層、p型半導體層、及電極層），得到一 發光二極體晶片300。接著，將該發光二極體晶片3〇〇固 合於一導線架120上，該導線架上配置有已預先設計好之 一第一電路125及一第二電路127。在將該發光二極體晶 片300固合於該導線架120,該圖形化導電層覆蓋該絕= 基底102之部份下表面1〇3與該第一電路125接觸。再者， 可利用一導線129將該金屬電極118與該第二電路127進 行電性連結，請爹照第17圖，得到一發光二極體裝置4〇〇。 由於該發光二極體晶片300本身具有延伸至該絕緣基底 102側壁104的圖形化導電層1〇6，因此可直接與平坦的第 一電路125接觸，達到電性連結。 根據本發明另一實施例，係利用第9圖所示結構（圖形 化導電層106除延伸至該絕緣基底1〇2的側壁1〇4外，— 形成於該絕緣基底102之部份下表面1〇3的底導電層1〇7 係進一步與該圖形化導電層106電性連結）經由第UA圖至 14A圖所示之製造流程，得到一發光二極體晶片3〇〇。接 者，將δ亥發光一極體晶片300固合於一導線架12〇上，兮 導線架上配置有已預先設計好之一第一電路丨25及一第二 電路127。在將該發光二極體晶片3〇〇固合於該導線架 120，該圖形化導電層覆蓋該絕緣基底1〇2之部份下表面 103與該第-電路125接觸。再者，可—導線129將 該金屬電極118與該第二電路127進行電性連結，請參照 第18圖’得到一發光二極體裝置4〇〇。由於該發光二極體 晶片300本身具有延伸至該絕緣基底1〇2側壁1〇4及底部 103的圖形化導電㉟廳，目此可直接與平坦的第一電路 9109A-A35682TWF_TN20 ] 00056 12 201232830 125接觸，達到電性連結。 基於上述，藉由本發明所提供之發光二極 製造方法’可使得具有絕緣基底的發光二拖 ^置及其 直電極的架構’除了不需犧牲部份發光區域：、有垂 面籍u卜，Μ + 7 争低有效發光 積）卜了改D電子流有效注入發光層的均勻性 流經途徑均勻分佈至整個發光二極體），提昇整體發^ 率。 雖然本發明已以數個較佳實施例揭露如上，然其並非 籲以限定本發明’任何所屬技術領域中具有通常知識者， 在不脫離本發明之精神和範圍内，當可作任意之更動與潤 飾，因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 1 【圖式簡單說明】In addition, in another embodiment of the present invention, the structure shown in FIG. 7A (the patterned conductive layer extends to the sidewall 104 of the insulating substrate 102) is continued through the manufacturing process shown in FIGS. 11A to 14A. A buffer layer, N 9109A-A35682TWF TN20100056 11 201232830 type semiconductor layer, light emitting layer, p type semiconductor layer, and electrode layer), a light emitting diode wafer 300 is obtained. Then, the LED chip 3 is fixed to a lead frame 120. The lead frame is provided with a first circuit 125 and a second circuit 127 which are pre-designed. The LED array 300 is bonded to the lead frame 120, and the patterned conductive layer covers a portion of the lower surface 1?3 of the substrate 102 in contact with the first circuit 125. Furthermore, the metal electrode 118 and the second circuit 127 can be electrically connected by a wire 129. Referring to Figure 17, a light-emitting diode device 4A is obtained. Since the LED wafer 300 itself has a patterned conductive layer 1〇6 extending to the sidewall 104 of the insulating substrate 102, it can be directly contacted with the flat first circuit 125 to achieve electrical connection. According to another embodiment of the present invention, the structure shown in FIG. 9 is used (the patterned conductive layer 106 is formed on the lower surface of the insulating substrate 102 except for the sidewalls 1〇4 extending to the insulating substrate 1〇2). The bottom conductive layer 1〇7 of the 1〇3 is further electrically connected to the patterned conductive layer 106. A light-emitting diode wafer 3 is obtained through the manufacturing process shown in FIGS. UA to 14A. The first LED circuit 300 is fixed to a lead frame 12, and the first lead circuit 25 and a second circuit 127 are pre-designed on the lead frame. The light-emitting diode chip 3 is fixed to the lead frame 120, and a portion of the lower surface 103 of the patterned conductive layer covering the insulating substrate 1 is in contact with the first circuit 125. Further, the wire 129 electrically connects the metal electrode 118 to the second circuit 127. Referring to Figure 18, a light-emitting diode device 4A is obtained. Since the LED chip 300 itself has a patterned conductive 35 chamber extending to the sidewalls 1〇4 and the bottom 103 of the insulating substrate 1〇2, the first circuit can be directly and flatly 9109A-A35682TWF_TN20] 00056 12 201232830 125 Contact and reach electrical connection. Based on the above, the light-emitting diode manufacturing method provided by the present invention can make the structure of the light-emitting diode with the insulating substrate and the structure of the straight electrode 'without sacrificing part of the light-emitting area: Μ + 7 strives for low effective illuminating product.) The uniformity of the effective flow of the D electron stream into the luminescent layer is uniformly distributed to the entire illuminating diode, and the overall emission rate is improved. The present invention has been disclosed in the above-described preferred embodiments, and is not intended to limit the scope of the present invention, and may be modified in any way without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. 1 [Simple description of the diagram]
第1圖係一剖面結構圖，繪示習知技術所述之發光二 極體結構。 X • 第 2A、3A、7A、l〇A、11A、12A、13A、及 14A 圖 係為一系列的上示圖，用以說明本發明實施例之發光二極 體裝置的製造流程。 第 2B、3B、7B、_、11B、12B、13B、及 14B 圖係 為第 2A、3A、7A、l〇A、11A、12A、13A、及 14A 圖沿 的A-A’切線的剖面結構圖。 第4、5、及6圖係為一系列的上示圖，用以說明本發 明其他實施例所述之發光二極體裝置其圖形化導電層的設 計。 9109A-A35682TWF TN20100056 201232830 第8圖係為一上示圖，.用以… 述之配置於絕緣基底侧面的圖^本發明另-實施例所 第9圖係為-剖面結構圖圖之形成方式》 例所述之發光二極體裝置其圖 况月本發明另一實施 第15及關係為一系^化導電層的設計。 明另一實施例所述之發光-極俨=、，、°構圖，用以說明本發 知尤—極體裝置的製造流程。 二Π圖係-剖面結構圖’繪示本發明 述之發光二極體裝置。 貫施 第18圖係-剖面結構圖，緣示本發明又 述之發光二極體裝置。 【主要元件符號說明】 10〜發光二極體； 12〜藍寶石基底； 13〜緩衝層； 14〜N型半導體層； 15〜半導體元件層； 16〜發光層； 18〜P型半導體層； 20〜第一電極； 22〜第二電極； 25〜最短路徑； 101〜上表面； 102〜絕緣基底； 1〇3〜下表面； 9109A-A35682TWF_TN201〇〇〇56 14 201232830 104〜側壁； 106〜圖形化導電層， 108〜緩衝層； 110〜第一半導體層； 112〜發光層； 114〜第二半導體層； 115〜半導體元件複合層； 116〜透明電極； • II8〜金屬電極； 120〜導線架； 125〜第一電路； 127〜第二電路； 129〜導線； 150〜貫孔； 200〜晶圓， 300〜發光二極體晶片； • 400〜發光二極體裝置；以及 A-A’〜切線。 9109A-A35682TWF TN20100056 15Figure 1 is a cross-sectional structural view showing the structure of a light-emitting diode according to the prior art. X • The 2A, 3A, 7A, 10A, 11A, 12A, 13A, and 14A drawings are a series of above diagrams for explaining the manufacturing process of the light emitting diode device of the embodiment of the present invention. 2B, 3B, 7B, _, 11B, 12B, 13B, and 14B are the cross-sectional structures of the A-A' tangent of the 2A, 3A, 7A, 10A, 11A, 12A, 13A, and 14A edges. Figure. Figures 4, 5, and 6 are a series of above diagrams for illustrating the design of the patterned conductive layer of the light emitting diode device of other embodiments of the present invention. 9109A-A35682TWF TN20100056 201232830 Fig. 8 is a top view, which is used for the side surface of the insulating substrate, and the ninth drawing of the present invention is a method of forming a sectional structure drawing. The light-emitting diode device described in the above is another embodiment of the present invention and the relationship is a design of a conductive layer. The illuminating-pole 俨=, 、,° composition described in another embodiment is used to illustrate the manufacturing process of the present invention. The bismuth diagram-section structure diagram </ RTI> shows the illuminating diode device of the present invention. Fig. 18 is a cross-sectional structural view showing a light-emitting diode device according to the present invention. [Major component symbol description] 10~ light emitting diode; 12~ sapphire substrate; 13~ buffer layer; 14~N type semiconductor layer; 15~ semiconductor element layer; 16~ light emitting layer; 18~P type semiconductor layer; First electrode; 22~second electrode; 25~ shortest path; 101~ upper surface; 102~insulating substrate; 1〇3~lower surface; 9109A-A35682TWF_TN201〇〇〇56 14 201232830 104~sidewall; 106~graphic conductive Layer, 108 to buffer layer; 110 to first semiconductor layer; 112 to light emitting layer; 114 to second semiconductor layer; 115 to semiconductor element composite layer; 116 to transparent electrode; • II8 to metal electrode; ~ first circuit; 127 ~ second circuit; 129 ~ wire; 150 ~ through hole; 200 ~ wafer, 300 ~ LED chip; • 400 ~ LED device; and A-A' ~ tangent. 9109A-A35682TWF TN20100056 15