TW201225212A - Method for fabricating shallow trench isolation - Google Patents

Abstract

A method for fabricating shallow trench isolations is provided. A patterned pad layer and a patterned mask layer are sequentially formed on a substrate, wherein the substrate includes a memory region and a periphery region. By using the patterned mask layer as a mask, the substrate is partially removed to form a plurality of trenches. A first liner is formed on the substrate to cover surfaces of the patterned mask layer, patterned pad layer and the trenches. After removing the first liner in the periphery region, a pull-back process is performed to the patterned mask layer, and a pull-back amount of the patterned mask layer in the periphery region is larger than a pull-back amount of the patterned mask layer in the memory region. An insulation layer is formed in the trenches to form a plurality of shallow trench isolations.

Description

201225212 VI. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating an isolation structure, and more particularly to a method of fabricating a shallow trench isolation structure. [Prior Art] With the advancement of semiconductor technology, the size of components has been continuously reduced. Therefore, in order to prevent a short circuit between adjacent elements, the isolation between the elements and the elements becomes quite important. The more commonly used method today is the Shallow Trench Isolation (STI) process. In general, the step of forming the shallow trench isolation structure includes forming a pad oxide layer and a patterned mask layer on the substrate, and then removing the portion of the substrate by the patterned mask layer as a mask. Then, the shallow trench is filled with an insulating material to form a shallow trench isolation structure to remove the tantalum oxide layer and the patterned mask layer. Where

201225212

99-008 35114twf.doc/I After the shallow trench, the I domain partially patterned the mask layer, causing the edge of the mask to retract relative to the edge of the shallow trench (Pull Baek). Because of the patterning of the mask layer; the remnants of the remaining ^ 'continued will fill the (four) shaped money trench isolation sister insulation (four), the purpose of this part of the insulation material can be delayed, ς oxide layer Injury caused by switching over the axle structure / avoiding depressions at the corners above the shallow trench isolation structure. In this way, when the shallow trench isolation structure is formed at the edge of the formation of the passivation layer and the gate oxide layer

The oxidized genus and the gate oxide layer have the same domain as the transitional energy - there is no angular thinning. And in the shrinking of the size of the memory element, the amount of shrinkage of the above-mentioned patterned layer in the cell area must also be reduced. The formation of the n-gate oxide layer is generally The memory cell area is a large amount 'plus the limitation of the operating voltage, so that the thickness of the high-voltage gate-layer is reduced or the amount of the thickness is quite limited, resulting in the problem that the surrounding area faces a shortage of the patterned mask layer. In other words, shallow trenches are isolated, '. The corners above the structure may be recessed due to excessive exposure, so that the gate oxide layer formed on the side of the shallow trench isolation structure has an angular thinning problem, and even grows in the depression. In this way, the component characteristics and reliability of the memory component are seriously deteriorated. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a shallow trench isolation structure that provides better memory characteristics for the memory device. The invention provides a method for manufacturing a shallow trench isolation structure. First of all,

201225212 99-008 35U4twf.doc/T sequence formation - patterned mat and - patterned mask layer, including μ cell area and peripheral area. Next, to pattern the mask; ^ In addition to a portion of the substrate 'to form a plurality of trenches', then a -first liner is formed on the bottom to cover the surface of the mask layer, the patterning layer, and the trench. Next, the first lining covering the surface of the surrounding area/== and the ditch is removed. Then the second case turns off the (10) process, so that the shrinkage of the (4) mask in the surrounding area is larger than the (10) amount of the mask layer (4), and the insulating layer is formed in the channel to form a plurality of shallow layers. Ditch isolation structure. w In the actual closure of the present invention, the above-mentioned lining layer comprises an oxidation. In the embodiment of the present invention, the material of the first layer is an oxide of High Temperature Oxide (HTO) or an oxide formed of tetraeth 〇 〇 〇 TE (TEOS). In the embodiment, the embodiment further comprises a uniform densification process of the first liner in nitrogen and at a high temperature. In the embodiment, the above-mentioned patterned mask layer covering the peripheral region, the patterned pad layer, and the trench_table_first layer are formed on the memory cell region to cover a photoresist layer. a memory cell; a first liner; and a first liner removed from the peripheral region. In one embodiment of the invention, the removal includes a wet process. Method of Viewing Layer In one embodiment of the present invention, the above-described shrinking process includes a wet wire. In one embodiment of the present invention, before forming the first layer,

201225212 99-008 35114twf.doc/I == lining 'to cover the patterned mask layer' pattern In the embodiment of the invention, the material of the second lining layer comprises nitrite. In the case of the ancient and the moon, the first liner was subjected to a uniform densification process in nitrogen or oxygen and under the same fox. In an embodiment, when the above-mentioned shrinking process is performed, the second lining layer and the first lining layer 1 and the patterned mask of the peripheral region are sequentially covered on the mask layer. The curtain layer is covered with a second lining. Figure 荦: The manufacturing method of the shallow trench isolation structure of the 'February' makes the amount of memory cells have appropriate internal shrinkage, so that d ΐ avoids the formation of concave oxidization at the upper corner of the shallow trench isolation structure.嶋佳==赖度例实施实施例, and with the accompanying drawings for easy understanding, the following [Embodiment] components, S B:: in the peripheral area is usually used to form a high-voltage component disk between the low-voltage components Lin, the surrounding t New Zealand is also more serious in the surrounding area 'low _ extreme oxygen 201225212 yy-υυ» 35H4twf.d〇c / i depression. As such, the component of the memory component is reduced. Therefore, the present invention is directed to the characteristics of the memory element to form a shallow trench isolation structure to avoid ^ =, the cell: the through-structure layer and the gate oxide oxidation angle are thin; = Figure 1A to Figure 1F are in accordance with this EMBODIMENT OF THE INVENTION - EMBODIMENT OF THE INVENTION - A schematic cross-sectional view of a method of manufacturing a trench isolation structure. Referring to FIG. 1A, first, a patterned pad layer and a patterned mask layer 120' are sequentially formed on a substrate 100. The substrate loo includes a memory cell region 1 and a peripheral region 104. The substrate 1 is, for example, a ruthenium-doped ruthenium substrate, a ruthenium-doped ruthenium substrate, an epitaxial germanium substrate, a gallium arsenide substrate, an indium telluride substrate, or a germanium telluride substrate. The material of the patterned underlayer 110 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method or a chemical vapor deposition method. The material of the patterned mask layer is, for example, tantalum nitride. The method of forming the film is, for example, a chemical vapor deposition method. Referring to FIG. 1A, next, a portion of the substrate 100 is removed by patterning the mask layer 120 as a mask to form a plurality of trenches 130. In the present embodiment, the method of removing a portion of the substrate 100 is, for example, a reactive ion etching method. Then, in the present embodiment, after the trench 130 is formed, a rapid thermal oxidization process (RTO) is performed on the substrate raft and the patterned mask layer 120. Referring to FIG. 1C, a first liner 140 is formed on the substrate 100 to cover the surface of the patterned mask layer 120, the patterned pad layer 110, and the trenches. In other words, the first lining layer 140 simultaneously covers the memory cell 201225212

99-008 35114 twf.doc/I The patterned mask layer 120 of the region 102 and the peripheral region 104, the patterned pad layer 110, and the surface of the trench 130. In the present embodiment, the first underlayer 140 includes, for example, an oxide layer, wherein the oxide layer is, for example, an oxide including high temperature oxide (HTO) or tetraethosiloxane (TEOS). The thickness of the first layer 140 is, for example, about 150 angstroms. The method of forming the first layer 140 is, for example, a low pressure chemical vapor deposition process. In this embodiment, after the first liner layer 140 is formed, the pair is further included

The first liner 140 is subjected to a uniform densification process. In the present embodiment, the densification process is carried out, for example, under nitrogen and at a high temperature, for example, a high temperature of about 900 °C. In particular, in one embodiment, the material of the first liner 14A includes, for example, ruthenium oxide, and the densification process enables the first liner 14 to be entangled in hydrofluoric acid/ethylene glycol or hydrofluoric acid/propylene. The button engraving rate in the engraving of the triol is as close as possible to tantalum nitride. Referring to Fig. 1D, next, the first liner 140 covering the patterned mask layer 120 of the peripheral region 1-4, the patterned enamel layer 11 〇, and the surface of the trench 13 移除 is removed. In detail, in the embodiment, for example, a photoresist layer 15 is formed on the memory cell region 102 to cover the first sound H0 of the memory cell device and then the first region 104 is removed. The level is 14 〇. In this way, since the first lining layer (10) placed in the memory cell area is protected by the photoresist layer 15 ,, it can be retained, and the first layer 140 located in the peripheral area 1 〇 4 is removed. . The wet etching process of the first layer 14 移除 is removed, such as using a spoon t μ ^ u. The use includes buffered hydrofluoric acid (Buffer)

Etchant for Hydrofluonc Acid 'BHF). Referring to Figure 1E, then the photoresist layer i5Q is removed and cleaned.

3) 114twf.doc/I 201225212 procedure to remove residue. Next, the patterned mask layer 12 is subjected to a shrinking process so that the indentation of the patterned mask layer 12 of the peripheral region 104 is greater than the amount of shrinkage of the patterned mask layer 120 of the brother cell region 1 () 2 In some cases, the shrinking process includes, for example, a wet process, such as a liquid preparation comprising fluoric acid/ethylene glycol or hydrofluoric acid/glycerol. Compared with the patterned mask layer 120 of the peripheral region 104, the patterned mask layer 120 of the memory cell region 102 is covered by the first liner layer 14 , so that the patterned mask layer 120 of the cell region 102 is The shrinkage C2 will be smaller than the shrinkage amount c of the patterned mask layer 12G of the week 1〇4, and the parameters such as the thickness of the liner and the _time in the shrinking process can be controlled to make the memory area of the film The patterned mask layer U0 of 1〇2 has an appropriate indentation Cb C2, respectively. In addition, the thickness of the patterned mask layer (3) of the peripheral region will be smaller than the thickness of the patterned mask layer 12 of the memory cell region 102. Referring to FIG. 1F, an insulating layer is formed in the trench 13A to form a plurality of shallow trench isolation structures 17A. In this embodiment, for example, the substrate 100 is first oxidized to form an oxide layer 160' on the surface of the trench 13 and then an insulating layer is formed in the trench no to form a shallow trench isolation structure. The material of the insulating layer is, for example, cerium oxide, and the forming method is, for example, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD) or high density plasma chemical vapor deposition (HDPCVD). After deposition of the insulating layer, it was planarized by chemical mechanical polishing (chemicaimechanicai p〇hshing, CMP). After the shallow trench isolation structure 170 is formed, the removal of the patterned mask layer 120 and the patterned pad layer 110 is continued to form in the memory cell region 102. 201225212

Yy-we J5114twf.d〇c/I Forming the floating interpole and forming the inter-polar oxide layer and the control electrode in the peripheral region to complete the memory component (4), and the steps are common knowledge in the field. It is well known, so it is not stated. In particular - mentioning 'in general' because the peripheral zone 1 () 4 is usually used to make 4 components and the health component 'before oxygen formation, the peripheral zone is more wet than the memory zone The amount, plus the thickness of the two-voltage gate oxide layer in the peripheral zone of 1〇4 is relatively difficult to reduce or reduce the amount is quite limited, so

The problem of the thinning of the gate oxide layer is also severe in the surrounding area 1G4. However, in the present embodiment, the first liner layer 14 is used to make the peripheral region _ and the patterned mask layer 12 of the memory cell region 102 have different amounts of retraction a, C2 after performing the shrinking process, and The amount of contraction C1 of the patterned mask layer 12 of the peripheral region 1〇4 is larger than the amount of contraction C2 of the patterned mask layer 120 of the memory cell region 1〇2. In this way, the space left by the patterned mask layer 12 can be filled with the insulating material to prevent the etching liquid from removing the patterned germanium layer 110 from damaging the upper corner of the shallow trench isolation structure 17〇. Seventh, avoiding the problem that the tunneling oxide layer and the gate oxide layer formed on the Π0 side of the shallow trench isolation structure are thinned or formed in the recess. For details, please refer to FIG. 4A to FIG. 4D simultaneously, FIG. 4A and FIG. 4B are respectively a partial schematic view of a conventional south and low pressure region, and FIGS. 4C and 4D are respectively a part of the high pressure region and the low pressure region of the present invention. A schematic diagram in which a gate oxide layer 18A and a control gate ι90 have been formed on the substrate 100. 4C and 4D, the shallow trench isolation structure ι7〇 11 formed by the method of the present embodiment compared to the shallow trench isolation structure 170' formed by the conventional method.

The upper corner 170b of 3M14twf.doc/I 201225212 does not have a depression, so the gate oxide layer 180 formed on the shallow trench 170 has a uniform thickness and does not have an angle thinning phenomenon or a problem such as formation in a recess. In particular, since the amount of contraction C1 of the patterned mask layer 120 of the perimeter & region 1〇4 is large, the gate oxide layer 18 subsequently formed on the side of the shallow trench isolation structure 17 of the peripheral region 104 can have A relatively large thickness is known in the prior art to provide good gate oxide insulating properties. Hey. 2A through 2E are schematic cross-sectional views showing a process of fabricating a shallow trench isolation structure in accordance with a second embodiment of the present invention. Referring to FIG. 2A, first, a patterned pad layer ιι and a patterned mask layer 120 are sequentially formed on a substrate 1 , wherein the substrate includes a memory cell region 1 〇 2 and a peripheral region 104 . Next, a portion of the substrate 100' is removed by patterning the mask layer 12 as a mask to form a plurality of trenches 130. The above steps may be referred to in the first embodiment, and are not described herein. Referring to FIG. 2B, a second liner layer 142 is then formed on the substrate 100 to cover the patterned mask layer 120, the patterned pad layer 11 and the surface of the trench 130. In the present embodiment, the second underlayer 142 includes, for example, a nitride layer, the material of which is, for example, tantalum nitride. The second liner layer 142 is formed by, for example, a low pressure chemical vapor deposition process, and the second liner layer 142 has a thickness of, for example, about 100 angstroms. In particular, in an embodiment (not shown), a thin oxide layer may be formed on the substrate 100 before the second liner layer 142 is formed, wherein the thickness of the thin oxide layer is, for example, about 1 〇. A first layer is formed on the first layer 142. In the present embodiment, the first liner 140 includes, for example, an oxide layer, and its material example 12 201225212

99-008 35114twf.doc/I = an oxide formed by a warm oxide or tetraethoxy decane. The thickness of the lining layer 140 is, for example, about 15 angstroms. The first layer is just a low pressure chemical vapor deposition process. In the present embodiment, after the lining layer 140 is further included, the first lining layer 140 is further subjected to a dense densification process such as in nitrogen or oxygen and a high temperature =, wherein the south temperature is, for example, about 9G. (rc. Special - mentioning that it is sensitive

The process can make the (IV) ratio of the first liner 14G in the side liquid of hydrofluoric acid/ethylene glycol or hydrofluoric acid/propylene triphosphate as close as possible to the nitrogen cut. In particular, the first lining layer (10) in which the material is nitrided η 14 - 2 and the material is oxidized stone is sequentially formed on the substrate 1 〇 0. An oxidation technique such as on-site vapor generation (Ιη SKU Steam Ge tiGn ' ISSG) oxidation is performed on the second layer 142 of forming the material as a nitride to convert a portion of the second liner layer 142 into an oxide layer to form The material is a first liner 140 of oxide. Or, for example, first depositing the first oxide layer on the surface of the second liner layer 142 by low pressure chemical vapor deposition, and then performing oxidation or other oxidation techniques to cause the oxidizing gas to penetrate the first oxide layer: = lining 142 Conversion to a second oxide layer 'This first oxide layer is combined with a second oxide layer to form a first liner 14 of material oxide. In this way, the second liner layer 142 and the first layer layer just as shown in FIG. 2B can also be formed. Please refer to 2C'. Next, the patterned lining layer 120 covering the peripheral area 1-4, the patterned enamel layer 110, and the surface lining fMO of the trench 13 移除 are removed. In detail, in the present implementation, for example, a photoresist layer 15 is formed on the memory cell region 1 to cover the first layer 13 of the memory cell region 1〇2.

5Dll4twf.doc/I 201225212 140, and then remove the first layer (10) of the perimeter area 104. In this way, the cell 1G2 (four)-liner (10) is covered by the photoresist layer 150, tt, !1 can be retained, and the first layer 66 in the surrounding area is ancient, and the second layer is exposed. 142. The first liner 140 acid = 3_filaments is removed, such as by _ buffering nitrogen r 2D ' and then removing the photoresist layer 15G and performing a cleaning process. After the photoresist layer 150 is removed, the memory cell region 102 covers the right side *=layer 140 and the second layer 142' while the peripheral region 104 is only covered with the second liner layer 142. The edge 13⁄4 t ΐ = the case mask layer 120 performs a shrinking process, so that the circumference 102°: the rounded amount C1 of the mask layer 120 is larger than the memory cell area... In the butterfly embodiment, the inner 7 ^ ^ ' An etching process such as the use of a button engraving solution comprising hydrofluoric acid/L-H-acid/glycerol. Wherein, compared with the surrounding area, the area _1, the mask layer 12Gjl only has the second lining layer 142 covering the protection, and the Z ^ ing mask layer 120 has the first lining layer 140 and the 衬 120 曰The disk is protected, so the patterned mask of the memory cell 1G2/SC2 will be smaller than the patterned mask layer 120 of the peripheral region 1G4, so that the peripheral region can be controlled by controlling the thickness of the liner and the shrinkage process ^ ^ > And the memory cell area 1〇2; 120 has the appropriate amount of shrinkage Cl, C2. In addition, the thickness of the perimeter mask layer 120 may be less than the thickness of the patterned mask layer 120 of the memory cell region 102. 201225212

yy-UU8 351l4twf.d〇c/I Please refer to Fig. 2E, and then form a multi-domain hexagram if/make m edge layer 160' as an oxide layer. This: Step 冓 170. The 'insulation layer 160' is not described here. θ ° to refer to the first embodiment, after the mask 170, continue to remove the pattern tunnel oxide layer and the material gate 1111, in the memory cell region 1 (32 forming the through layer and the control gate The steps of forming the interpolar oxygen in the = region 104 are well known to the person skilled in the art: (4) = 1 "Because the peripheral region 104 is usually formed with a gate oxide layer, the surrounding region is a wet money amount. In addition, the thickness of the oxygen layer in the peripheral region 104 is relatively difficult to reduce or the amount of reduction is relatively limited, so that the problem of the (four) layer of the inter-electrode (10) layer is also strict in the peripheral region. In the present embodiment, the first liner is utilized. 140 causes the peripheral region to be removed from the memory cell region by the same amount of contraction C1, C2, and the peripheral region = the masking layer 120 has a retraction fC1 greater than the memory cell region's patterned mask layer no. The shrinkage amount C2. In this way, the patterned mask layer 12〇 is retracted by the empty and filled insulating material to avoid removing the etching liquid of the patterned germanium layer U0 and the like, thereby damaging the shallow trench isolation structure 17〇 At the upper corner, to avoid tunneling oxygen layer and gate formed later on the side of the shallow trench isolation structure 17 Problems angle formed at the thinning phenomenon or the like depression layer occurs. For 15,201,225,212

Yy-υυδ i5114twf.d〇cA For example, as shown in FIG. 4C and FIG. 4D, the upper corner corner 17〇a of the shallow trench isolation structure 170 formed by the method of the present embodiment does not have a depression, and thus is formed in The gate oxide layer 180 on the shallow trench isolation structure 170 has a thickness of a uniform sentence and does not have a problem of corner thinning or formation in a recess. In particular, 'since the amount of shrinkage C1 of the patterned mask layer 12 of the peripheral region 104 is large', the idle oxide layer 180 subsequently formed on the side of the shallow trench isolation structure 170 of the peripheral region 104 can have a more conventional technique. Large thickness to provide good gate oxide insulation properties. In particular, in the above embodiments, the second liner layer 142 is formed directly on the substrate 100. However, in other embodiments, an oxide layer may be formed on the substrate 1 . A second liner 142 of material nitride is formed over the oxide layer. 3A to 3D are schematic cross-sectional views showing a method of manufacturing a shallow trench isolation structure according to a third embodiment of the present invention. The manufacturing process of this embodiment is substantially the same as that described in FIGS. 2A to 2E. Explain in different places. Referring to FIG. 3A, first, an oxide layer 138 is formed on the substrate 100, and a method of forming the oxide layer 138 is, for example, a low pressure chemical vapor deposition method. Then, the oxide layer 138 is subjected to a uniform densification process under nitrogen and high temperature, so that the etching rate of the oxide layer 138 in the etching solution of hydrofluoric acid/ethylene glycol or hydrofluoric acid/glycerol is as close as possible to nitrogen. Phlegm. Then, a second liner layer 142 and a first liner layer 140 are formed on the oxide layer 138 in sequence. In the present embodiment, the second liner layer 142 is formed by, for example, forming a tantalum nitride layer by low pressure chemical vapor deposition. The first liner layer is formed by, for example, performing an oxidation technique such as in-situ steam generation (ISSG) oxidation on the second liner layer 142 to

201225212 ^^-υυο 35114twf.doc/I The second underlayer 142 is converted into an oxide layer to form a second liner #140 of the material oxide. In this way, in this embodiment, the substrate ι is formed sequentially. The oxide layer 138, the second liner layer 142 whose material is nitride, and the first layer 14 of the material are oxides. Referring to FIG. 3B, next, the first, 40, and second liner layers 142 covering the patterned mask layer no of the peripheral region 104, the patterned germanium layer 11 and the surface of the trench 13 are removed. In detail, in the present embodiment, for example, a photoresist layer is formed on the cell-reduction region 1〇2 (the first liner layer 140 of the cell region 102 is not depicted, and then the 14G of the peripheral region is removed). ° then 'removing the photoresist layer and performing a cleaning process to remove the residue. Then 'removing the second liner 142 of the peripheral region 104. The method includes: for example, including a wet-type process, such as = = money enrichment of hydrofluoric acid. A method of removing the second liner 142, such as a first layer of a crucible including a pickled acid 4, a layer of the removed memory cell (10), and a removal of the peripheral region Immediately after the second lining layer 142, the first lining layer of the m〇2 layer is just adjacent to the oxide layer of the peripheral region (3). The M0 plaque is used, and the 軎3C 'then' then removes the memory cell region 102. A liner layer (10)it of the oxide layer 138. The removal of the first liner layer 140 and the oxidative release include, for example, a wet process such as the use of a dilute == engraving. In particular, in the embodiment, The patterned patterned mask layer 120 has 120 first liner layer 142 and oxide layer 138 covering 17 201225212

----- 35114twf.doc/I Protection. Referring to FIG. 3D, the patterned mask layer 12 is subjected to a shrinking process such that the patterning mask layer 12 of the peripheral region 104 has a larger amount of indentation than the patterned mask layer 12 of the memory cell region 102. The amount of contraction of the sputum is C2. In the present embodiment, the shrinking process includes, for example, a wet etching process such as using a money engraving solution including fluorofluoric acid/ethylene glycol or hydrofluoric acid/glycerin. Wherein, compared to the patterned mask layer 120 of the peripheral region 104, the memory layer 102 is exposed, and the patterned mask layer 120 has a second layer 142 and an oxidized layer 138 for protection, thus memory The amount of shrinkage C2 of the patterned mask layer of the cell region 1〇2 is smaller than the amount of shrinkage ci of the patterned mask layer 12〇θ of the peripheral region 1〇4. In addition, the thickness of the patterned mask layer 12 of the peripheral region 104 may be less than the thickness of the patterned mask layer 12 of the memory cell region 102. In particular, the patterned mask layer 12 of the peripheral region 104 and the memory cell region 〇2 can have an appropriate amount of shrinkage cn, C2 by controlling the thickness of the liner and the etching day in the shrinking process. After the completion of this step, the subsequent processes for forming a plurality of shallow trench isolation structures can be referred to the previous embodiment, and will not be described herein. In summary, the method for fabricating the shallow trench isolation structure of the present invention is such that the patterned mask layer has a different amount of retraction in the peripheral region and the sinter cell region according to the element characteristics of the peripheral region and the memory cell region. In this way, it can be avoided that the upper corner of the shallow trench isolation structure is recessed due to the removal of the patterned pad layer, etc., so that the tunnel oxide layer and the gate oxide layer which are subsequently formed on the side of the shallow trench isolation structure are The corner can have a thickness consistent with the main body without the angle thinning phenomenon. Therefore, the memory element can have better element characteristics. Although the present invention has been disclosed above by way of example, it is not intended to be limiting 18 201225212

Yy-υυ» 35114twf.doc/I The present invention, any one of ordinary skill in the art, without departing from the spirit and scope of the present invention, may be modified and retouched, so the scope of the present invention is This is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. are flow cross-sectional views showing a method of manufacturing a shallow trench isolation structure in accordance with a first embodiment of the present invention. 2A through 2E are schematic cross-sectional views showing a process of fabricating a shallow trench isolation structure in accordance with a second embodiment of the present invention. 3A-3D are schematic cross-sectional views showing a method of fabricating a shallow trench isolation structure in accordance with a third embodiment of the present invention. 4A and 4B are partial schematic views of a conventional high pressure zone and a low pressure zone, respectively, and Figs. 4C and 4D are partial views of the high pressure zone and the low pressure zone of the present invention, respectively. [Main component symbol description] 100 substrate 102 memory cell 104 peripheral region 110 patterned pad layer 120 patterned mask layer 130 trench 138 oxide layer 140 ' 142 : liner

Jjll4twf.doc/I 150 : photoresist layer 160 : oxide layer 170 : shallow trench isolation structure 170a : upper corner 180 : gate oxide layer 190 : control gate

Cl, C2: shrinkage

20

Claims (1)

201225212 35114twf.doc/I VII. Patent Application Range: 1. A method for manufacturing a shallow trench isolation structure, comprising: sequentially forming a patterned underlayer and a patterned mask layer on a substrate, wherein the substrate comprises a a memory cell region and a peripheral region; the patterned mask layer is used as a mask to remove a portion of the substrate to form a plurality of trenches; a first liner layer is formed on the substrate to cover the patterned mask layer, The patterned pad layer and the surfaces of the trenches; • removing the patterned mask layer covering the peripheral region, the patterned pad layer, and the first layer of the surface of the trenches; Performing a shrinking process on the mask layer, such that the patterned mask layer of the peripheral region has a larger amount of shrinkage than the patterned mask layer of the memory cell region; and forming an insulating layer in the trenches To form a plurality of shallow trench isolation structures. 2. The method of fabricating a shallow trench isolation structure according to claim 1, wherein the first layer comprises an oxide layer. 3. The method of fabricating a shallow trench isolation structure according to claim 2, wherein the material of the first liner comprises a high temperature oxide or an oxide formed of tetraethoxysilane. 4. The method for manufacturing a shallow trench isolation structure according to claim 1, further comprising performing a densification process on the first liner in nitrogen and at a high temperature. 5. The method of fabricating the shallow trench isolation structure of claim 1, wherein the first covering the patterned mask layer of the peripheral region, the patterned pad layer, and the surface of the trenches are removed. The step of lining includes: 21 201225212 yy\jKj〇35114twf.doc/I forming a photoresist layer on the memory cell region to cover the first liner layer of the memory cell region; and removing the peripheral region First lining. 6. The method of manufacturing a shallow trench isolation structure according to claim 5, wherein the method of removing the first layer comprises a wet process. 7. The method of fabricating a shallow trench isolation structure according to claim 1, wherein the shrinking process comprises a wet etching process. 8. The method of manufacturing the shallow trench isolation structure of claim 1, further comprising forming a second liner on the substrate to cover the patterned mask layer before forming the first liner layer. The patterned mat and the surface of the trenches. 9. The method of fabricating a shallow trench isolation structure according to claim 8 wherein the material of the second liner comprises tantalum nitride. 10. The method of fabricating a shallow trench isolation structure as described in claim 8 further comprising performing a uniform densification process on the first liner in nitrogen or oxygen and at a high temperature. 11. The method of fabricating a shallow trench isolation structure according to claim 8, wherein the patterned liner layer of the memory cell region is sequentially covered with the second liner layer during the shrinkage process The first liner layer and the patterned mask layer of the peripheral region are covered with the second liner layer. twenty two