TW201225092A - Electronice system, memory and method for providing the same - Google Patents

Abstract

At least one diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow.These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a first end of a memory element coupled to the P terminal of the first diode and to the N terminal of a second diode.The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes.By applying a high voltage to a second end of the memory element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state.Similarly, by applying a low voltage to a second end of the memory element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state.The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

Description

201225092 VI. Description of the invention: [Technical field to which the invention pertains] [The present invention relates to a memory fine unit, particularly a programmable resistance element of a memory array. [Prior Art] 阙彳 Programming a resistance element usually means that the resistance state of the element can be changed after programming. The resistance state can be determined by the resistance value. For example, a resistive component can be a single-programmable (〇ne_Time pr〇grammable, 〇τρ) component (such as an electrical fuse), while a programming method can apply a high voltage to generate a high current through the ΤΡ component. When a high current flows through the 0ΤΡ element via the open programming selector, the 0ΤΡ element will be programmed to burn to a high or low resistance state (depending on the filament or antifuse). [0003] Electrical fuses are a common type of ΤΡ, and such programmable resistive elements can be polycrystalline shi, shixi polycrystalline shi, bismuth, thermally isolated active regions, metals, metal alloys or Their combination. The metal can be a metal, copper or other transition metal. The most commonly used electric melting wire is Shihuahua's polycrystalline stone, which is made of a gate of a complementary MOS transistor (CMOS) for use as an internal connection. Electrical snaking can also be one or more contacts or vias instead of small segments. High current can burn contacts or layers indirectly to a high resistance state. The electrical fuse can be an anti-fuse, where a high voltage reduces the resistance rather than increasing the resistance. The antifuse may be composed of one or more contacts or layer indirect points and has an insulator therebetween. The antifuse can also be coupled to the CMOS body by a CMOS gate that contains a gate oxide layer as an insulator. [0004] FIG. 1 shows a conventional programmable resistive memory cell. Storage 100129641 Form No. A0101 Page 4 of 59 1003436465-0 201225092 单元 Unit 10 includes a resistive element 丨丨 and a MOS transistor (_s) programming selector 12. One end of the resistive element u is lightly coupled to the drain of (10), the other end is switched to the positive voltage V+. The idle surface of the NMOS 12 is coupled to the selection signal SEL, and the source is coupled to the negative voltage v_. When the high voltage is applied to v + and the low voltage is applied to V-, the resistive element 1〇 can be programmed to open the NM〇S 12...the most common resistor by raising the select signal SEL: The piece is Shi Xihua Polycrystalline hair is the same material used in the production of the gate. The area of the NMOS programming selector 12 needs to be large enough to allow the required programming current to last for a few microseconds. The programming current of the deuterated polysilicon is usually from a few milliamperes (for a fuse having a width of about 40 nm) to 2 mA with a hanging width of about 0.6 μm. Therefore, an electric storage unit using a deuterated polycrystalline crucible often requires a large area. ... [0005] The programmable resistive element can be a reversible resistive element that can be reprogrammed and reversibly programmable to a digital logic value T 4 丫 . Programmable electrical parts can be fabricated from phase change materials such as germanium (Ge), germanium (Sb)

The composition of Te) is Ge2Sb2Te5 (GST-225) or a GeSbTe-based material including indium (ΐηΟ), tin (Sn) or selenium (Se). The phase change material can be programmed to an amorphous bear high resistance state or a crystalline low resistance state via a high voltage short pulse or a low voltage long pulse. The reversible resistance element may be a resistive random access memory (resistive memory RRAM), and the memory unit is made of a metal oxide between metal or metal alloy electrodes, such as platinum/nickel oxide/platinum (Pt/NiO/Pt). Or made of titanium nitride/titanium oxide/yttria/titanium nitride (TiN/TiOx/Hf〇2/TiN). The reversible change in resistance state is the generation or elimination of conductive filaments via the polarity, intensity and duration of the voltage or current pulses. Another similar resistive random access memory 100129641 Form No. A0101 Page 5 of 59 1003436465-0 201225092 (am) The programmable resistive element is a conductive bridge random access memory (CB^AM). This memory is based on electrochemical deposition and removal of metal ions in a solid electrolyte film between metal or metal alloy electrodes. The electrode may be an oxidizable anode and an inert cathode' and the electrolyte may be a silver-doped or copper-containing sulfur-based glass such as strontium selenide (GeSe) or selenium sulphide (GeS). The resistance state can be secreted (four) to be (iv) the polarity, intensity and duration of the voltage or current pulse to create or destroy the conductive bridge. [0006] [0007] Round B a shows -

The N-shaped bipolar electric solar illuminator 22 has a P+ active region 23, a shallow well 24, an N+ active region 27, a p-type substrate 25, and a spacer element. A shallow trench isolation (STI) 26βΡ+ active region 23#〇N+ active region η is lightly coupled to the N well 24, which is the P and N terminals of the bipolar electro-crystal Zhao 22 and the base diode The P-type substrate 25 is the collector of the bipolar electro-crystal. This type of memory cell requires the N shallow well 24 to be shallower than the shallow trench isolation 26 to properly separate the memory cells, thus requiring three to four more than the standard CMOS logic process, making the first photomask more expensive. Figure 2b shows a programmable resistive element of another phase change memory (pcM). The phase change memory material has a phase change film 21, a diode 22, and a programming device. The phase change film 21 is coupled between the diode anode 22 and a positive voltage pi. The cathode 22 of the diode is coupled to a negative voltage shame. Death* knows that the appropriate voltage lasts between V+ and V- for an appropriate period of time. The phase change is low and can be programmed to a high or low resistance state, depending on voltage and duration - see "Kwang-Jin Lee et al ., "A 90nra l 8v 512Mb Diode-Switch PRAM with 266ΜΒ/ς r> b Kead

Throughput, M International Solid-.ct 5tate Cir- 100129641 Form No. A0101 Page 6 of 59 1003436465- 201225092 nce, ώυυ,, ρρ 4γ2_273". Figure & D is for use - nucleus as phase change memory ρ Material_子. "This technology can be (4) state edited to ', with 6.8 F2 (F stands for feature size), the production of diodes, such as "SEG" nH re-entry PCM application, It will become very expensive. In contrast to the embedded [0008] Figures 3a and 3b, the display of the new < 丄$ + ββ _, the singularity of the magnetic memory (MRAM) storage 〇β magnetic parallel (or state 0) and magnetic anti-parallel (or State 1). Ο

The MRAM memory cell 210 is comprised of a magnetic tunnel junction (MTJ) 2U and a programming selector 218 of -NM〇S. The magnetic tunnel junction 211 has a multi-layered T-ferromagnetic or antiferromagnetic stack with a metal oxide such as A1203 or MgO as an insulator between the layers. The magnetic track junction 211 includes a free stack layer 212 and a solid stack layer 213. The programming selector CMOS 218 is turned on and a suitable current is applied to the magnetic tunnel junction 211, and the free layer stack 212 can be arranged in magnetic parallel or magnetic anti-parallel to the fixed layer stack 213, depending on the current flowing out or flowing into the fixed layer stack 213. set. Therefore, the magnetic state can be programmed, and the state result can be determined by the resistance value to determine the low resistance of the magnetic parallel state or the high resistance of the magnetic antiparallel state "state 〇 or 1 resistance value is about 5kD or 10 Κ Ω, respectively, and the programming current is about + An example of a /-i〇〇-2〇〇mAe programming MRAM memory cell is described in "2Mb Spin_Transfer Torque RAM with Bit-by-Bit Bidirectional Current Write and Paralleiizing-Direction Current Read," International Solid-State Circuit Conference, 2007, Pp·480-481". [Description of Contents] 100129641 Form No. A0101 Page 7 of 59 1003436465-0 201225092 _9] The present invention is directed to providing a programmable resistor 7L piece stock using two (four) as a programming selector The device can be programmed to use a quasi-CMOS logic process to reduce the size and cost of the memory cell. τ [Therefore, the present invention provides a memory comprising: a plurality of memory storage units, at least one memory storage unit including The memory element has a first end and a second end, the first end being coupled to the first supply voltage line; and a first diode package Including at least a first end and a second end, wherein the first end has a -type-type doping, the second end has a second type of doping, and the first end of the first diode is coupled To the second end of the memory element; a second diode comprising at least a first end and a second end, wherein the first end has a first type of doping and the second end has a second type Doping, the second end of the second diode is coupled to the second end of the memory element, wherein the second end of the first diode is coupled to a second supply voltage line The first end of the second diode is coupled to the second or a third supply voltage line, wherein the memory element is configured to be programmable to a different logic state, via applying a voltage to the _, second And/or a third power voltage line, thereby turning on the first diode to cut the second diode to a logic state, or turning on the second diode to cut the first diode To another logic state. [0011] The present invention therefore provides a memory comprising: a plurality of memory storage units, to A memory storage unit includes: a memory element having a first end and a second end, the first end coupled to a first supply voltage line; and - the second diode includes at least a first end and a second end The first end has a first type doping, the second end has a second type doping, and the first end of the first diode is coupled to the second end of the memory element; 100129641 form No. A0101 Page 8 of 59 1003436465-0 201225092 Ο [0012]

a second diode includes at least a first end and a second end, wherein the first end has a first type of doping 'the second end has a second type of doping, the second dipole The second end is stalked to the first end of the & recall element, wherein the second end of the second diode and the first end of the second diode are coupled to a second a power supply voltage line, wherein the memory element is configured to be programmable to a different logic state, by applying a voltage to the first and second supply voltage lines, thereby turning the first diode off and cutting the second The polar body is in a logic state, or the second diode is turned on to cut off the first diode to another logic state. The present invention provides an electronic system comprising: a processor; and a theater operatively coupled to the processor, the memory comprising at least a f-time element to provide a series (4), each of the π: a memory element having a a - terminal and a second terminal, the first terminal being:: to - a - supply voltage line; and 1 - the diode comprising at least a second end 'where the first end has a first type of miscellaneous The second end has a second type of doping, the first end of the first diode is coupled to the second end of the memory element, and the second end of the first diode is coupled to a second power supply voltage line; a second polar body comprising at least a first end and a second end 'where the first end has a first type doping and the second end has a second type doping The second end of the diode is coupled to the second end of the memory element, and the first end of the second diode is coupled to the second or third supply voltage line; 'The S-remembered component is set to be programmed to a different logic state by applying voltage to the first, second and/or third power supply lines of the S, thereby conducting The first diode cuts the second diode to a logic state 100129641, form number A0101, page 9 / total 59 1003436465-0 page 201225092, or turns on the second diode and t grazes The first diode is broken to another logic state. [0013] The present invention therefore provides a method for providing a memory comprising: providing a plurality of memory cells - at least - a memory storage unit comprising at least (i) - a memory element having a first end and a second end, The first end is coupled to a first-supply voltage line; and (ii) a first diode includes at least a first end and a second end, the first end having a first type of doping, the second The terminal has a first type of doping, the first end of the second diode is coupled to the second end of the memory element and the second end of the first diode is coupled to the second power source a voltage line; (1) the second diode includes at least a first end and a second end, the first end having a first type doping and the second end having a second type doping, the first end providing a first end of the diode, the second end providing a second end of the diode, the second end of the second diode being coupled to the second end of the memory element and the second The first end of the polar body is coupled to the second or third supply voltage line; and [0014] wherein the memory element is configured to be programmable to a different logic a state, cutting the second diode to a logic state, or turning on the second diode by applying a voltage to the first, second, and/or third power voltage lines to turn on the first diode The first diode is cut off to another logic state. [Embodiment] In an embodiment of the present invention, a Ρ + / Ν well junction diode is used as a program selector for a programmable resistive element. This diode can include ρ + and Ν + active regions in the well. Since ρ·^〇Ν+ active area and 1^100129641 Form No. A0101 Page 10 / Total 59 Page 1003436465-0 201225092 Wells are all ready-to-use standard GS logic records, these components can be used in an efficient and cost-effective way It is made and does not require additional masks or process steps to save costs. This programmable resistive element can be included in an electronic system.

_] Then (4) According to the memory of the (IV) to Bu diode of the embodiment, the block diagram is as early as 30. (d) Yes, the memory unit 3() includes a memory element 3a and a diode 32a, 32b. The memory element 3a can be consumed between the anode of the diode 32a and the voltage v. The cathode of the dipole Zhao Xin can be lightly connected to the negative electricity Ο pressure. A few pieces of 30& can be coupled between the cathode of the diode 32b and the voltage V. The anode of the pole 32b can be coupled to a positive voltage 乂+. In an embodiment, the memory cell 3 can be a magnetic memory (MRAM) memory cell that includes a memory element 3A that is a magnetic tunnel junction (MTJ). The diode 32a or 32b can be used as a programming 丨 or 丨 selector. The diode can be constructed using a p+ substrate of a standard CMOS process P+/N well. The P+ and N+ active regions as the diode anode and cathode are the source or drain of the CM〇s component. The n well is the CMOS well used to embed the pM0S component. Alternatively, the diode can be constructed using an N+/P well in the Q process, which uses an N-type substrate. The memory element 3Ga and the diode 32a or 32b are interchangeable between the supply voltages V and V+/V-. Applying the appropriate voltage (between 〇 and V-) via a suitable time 'memory element 30a can be programmed to be high by turning on-diode and cutting off the other diode Or a low resistance state, so the program memory storage unit 30 can store data values (eg, bits of data). The diode 32a or 32b may be a junction diode. The P+ and N+ active regions of the junction diode can use a dummy CMOS gate, shallow trench isolation (STI), local oxidation (LOCOS) or germanide barrier layer (SBl 100129641, Form No. A0101, Page 11 of 59) 1卯3436465-0 201225092) to isolate. If no lithotripsy is adjacent to the boundary of the first and second active regions, the first and second active regions may be butted together or separated by a low dose active region to separate the active regions. [0017] A magnetic tunnel junction (MTJ) memory cell can serve as an example to illustrate the key implementation concepts. Figure 5a shows a cross section of a diode 32 in which a shallow trench isolated P + /N well diode is used as a programming selector in a programmable resistive element. The P+ active region 33 and the N+ active region 37, which respectively constitute the P and N terminals of the diode 32, are the source or drain of the PM0S and NM0S in a standard CMOS logic process. The N+ active region 37 is coupled to the N-well 34, which is embedded in the PMOS in a standard CMOS logic process. Shallow trench isolation 36 isolates the active regions of the different components. A resistive element (not shown in Figure 5a), such as the MTJ, can be coupled to the P+ region 33 at one end and to the high voltage supply V+ at the other end. To program such a programmable resistive component, a high voltage is applied to V+, a low voltage or ground potential is applied to the N+ region 37. Therefore, a high current flows through the fuse element and the diode 32 to program the resistance element. [0018] Figure 5b shows a cross-sectional view of another junction diode 32' embodiment as a programming selector and isolated by a dummy CMOS gate. Shallow trench isolation 36' provides isolation of other active regions. Active region 31' is defined by shallow trench isolation 36'. Here, the N + and P + active regions 37' and 33' are further mixed by a dummy CMOS gate 39', a P + implant layer 38', and an N + implant layer (complementary to the P + implant layer 38'), respectively. To define, the N and P ends of the diode 32' are formed. The diode 32' is fabricated like a PMOS component comprising 37', 39', 33', 34' as the source, gate, drain and N well, whereas the source 37' is covered with N+ implant Into the layer instead of the P+ implant layer 38' covered by the real PIOS. The dummy M0S gate 39' is preferably biased at a fixed electrical 100129641 Form No. A0101 Page 12 / Total 59 Page 1003436465-0 201225092 Pressure 'The purpose is to treat the active area 33 during the production process, and! ^+ isolation between active areas 37'. The Ν+active region 37 is coupled to the well 34', which is the body embedded in the PM 〇s in a standard CMOS logic process. The ρ substrate 35 is a matrix of p-type 矽. The resistive element (not shown in Figure 5b, such as the MTJ) can be lightly coupled to the P+ zone 33' and the other end to the high voltage supply. In order to program such a programmable resistive element, a high voltage is applied to the low voltage or junction active region 37'. Therefore, a high current flows through the dissolver element [0020] Ο [0020] and the diode 32, Program the resistive element. This embodiment has an ideal small size and low resistance. A cross-section of another embodiment, shown in Figure 5c, in which the junction diode 32" is made as a braided material. Fig. 5 is similar to Fig. 5b, however, the dummy (10)s gate 39 in the figure is "replaced" by the halide barrier layer 39 in the figure to prevent the growth of the ceramsite at the top of the active region 31". If there is no false (10) s gate or a lithiation barrier, the NW+ active region will be short-circuited by the active region 31 "the surface of the stone compound. 嶋The other-dip (four) face, its towel, the second pole ship, As a programming selector, and using a technique of a (four) substrate (for example), in the technique, the substrate 35'' is an insulator such as a dioxide dioxide or similar material, and the insulator contains a thin layer of stone grown on top. Both _S and PM0S are isolated from each other and the substrate 35 by a dioxotomy or similar material. One piece of active region 31" via a dummy CMOS gate 39", a P+ implant layer 38" and The mixing of the entry layer (1) the complementary layers of the implant layer 38" is divided into an N+ active region π", an active region 33'' and a body 34, '. Therefore, Ν+active area 3?,, and ρ+ active area 100129641 Form No. 1010101 Page 13/59 pages 1003436465-0 201225092 33', respectively forming the N-terminal and P-terminal of the junction diode 32". N+ The active region 37', and the P+ active region 33'' can be the same as the source or the pole of the NM0S and PM0S in the standard (3) (10) logic process. Similarly, the dummy gate can be constructed with a standard CMOS process. The s gate is the same. The dummy M〇s gate 39 can be biased at a fixed voltage for the purpose of isolation between the P+ active region 33" and the N + active region 37" during the fabrication process. Zone 37 is fitted to the low voltage and N well 34. This N well is embedded in the body of the PM0S in the standard CMOS logic process. The resistor component (not shown in Figure 6a) 'such as MTJ' can be integrated into p+ active Zone 33, and the other end is coupled to a high voltage power supply V+. To program such an electrical fuse memory cell, high and low voltages are applied to V+ and V-, respectively, and a large current is conducted through the MTJ and the junction diode. 32 to program resistive elements. Other embodiments of CMOS isolation techniques, such as shallow trench isolation, dummy CMOS gates or The barrier layer can be easily applied to the corresponding CMOS SOI technology on one to four sides or on either side. [0021] FIG. 6b shows a carrier diagram of another embodiment of the junction diode 45, the junction diode 45 Programming selector using FinFET technology. FinFET is a basic multi-gate transistor with FIN (FIN) technology. FinFET technology is similar to traditional CMOS, but has a high lean island, which rises in The main body is like a main body of a CMOS component. The main body is in a traditional CMOS, which is divided into a source, a drain, and a channel of a polycrystalline or non-metal gate. The main difference is the body of the M0S component in FinFET technology. Being lifted onto the substrate, the height of the island is the width of the channel, although the direction of current flow is still parallel to the surface of the crucible. Figure 6b shows an example of FinFET technology, which is an epitaxial layer. , built in class 100129641 Form No. A0101 Page 14 / Total 59 Page 1003436465-0 201225092 Like SOI insulation or other high-resistance Shi Xi matrix. Dream base (10) can be surnamed into several Nanda rectangular islands Zones 3Η, 31_2, and 3卜3. Through the growth of the gate oxide layer of the field, the island regions 31_1, 3丨_2, that is, 31_3 can be covered by the M0S gates 39-1, 39-2, and 39-3. Elevated islands = both sides and the source and the annihilation zone. The source and drain regions are formed in the islands 31-1, 31-2, and 31-3, and then filled with 矽, such as filled in the fill $ 〇1 and 40-2, so that the combined source and drain areas are large enough to drop the contacts. In Figure 6b, the filled areas of 40-1 and 40-2 are only used to illustrate the 横截 revealing cross-sections. The surfaces of the island regions 31丄1, and 313 are filled. In this embodiment, the active regions 33_1, 2 3 and I 2' 3 are respectively covered by the P+ implant layer 38 and the N + implant layer (p + implant layer 38 ^ complementary) to form the junction diode. The PMOS, which is not like a conventional FinFET, is all covered by the p+ implant layer 38. The N+ active zone 仏 1, 2, 3 is consumed by the low voltage power supply. The resistive element (嶋 not shown), such as the MTJ, is switched to the p+ active region at one end and to the high voltage supply V+ at the other end. In order to program such an electrical fuse wire 'high and the voltage is applied to V-, respectively, a large current flows through the resistor element and the junction diode 45 to program the resistor element. Other embodiments of the CM〇s main body isolation, such as shallow trench isolation, or Weigong material, can be easily applied to the corresponding operation. [0022] FIG. 7 shows an embodiment of a magnetic memory (MRAM) memory cell 31, using diodes 317 and 318 as programming selectors. According to this embodiment, the 'MRAM memory cell 310 is a three-terminal MRAM memory cell in FIG. 7 and has a magnetic tunnel junction (MTJ) 311 including a free-stacking layer 312, a fixture 100129641, a form number A0101, page 15/ Total 59 pages ^03436465-0 201225092 ^ The dielectric layer between the stacked layers 313 and the two diodes 317 and 318. Free stack layer 312 is coupled to supply voltage v and coupled to fixed stack layer 313 via a dielectric film such as aluminum oxide (A1203) or magnesium oxide (MgO). The N terminal of diode 317 is coupled to fixed stack layer 313 and the P terminal is coupled to v+ to program (logic) 1. The P terminal of diode 318 is coupled to fixed stack layer 313 and the N terminal is coupled to V- to program (logic). If the V+ voltage is higher than v, the current flows from V+ to V to program MTJ 311 to state 1. Similarly, if the V-voltage is lower than V, the current flows from V to V- to program the MTJ 311 into state 〇. During the programming process, the other diode should be in the cutoff area. At the time of reading, both V + and V- can be set to 0V and the resistance between nodes V and V+/V- can be sensed to determine that the magnetic tunnel junction 311 is in state 0 or 1. [023] Figure 8a shows a cross-sectional view of an example of an MRAM memory cell 310 that includes an MTJ 311 and junction diodes 317 and 318 as programming selectors. According to this embodiment, the MTJ 311 has a free stack layer 312, a fixed stack layer 313, and a dielectric therebetween to form a magnetic tunnel junction. The diode 317 is used for programming 1 and the diode 318 is used for programming. 0. Dipoles 31 7 and 318 have p + and N + active regions in wells 321 and 320, respectively, which can be used to embed PM〇s in standard CMOS processes. The diode 317 has a P+ active region 315 and an N+ active region 314' to form the P and N terminals of the diode 317. Similarly, diode 318 has a P+ active region 316 and an N+ active region 319 to form the P and N terminals of the programming zero diode 318. The p and N terminals of diodes 317 and 318 shown in Figure 8a are isolated by STI 330. It is known to those skilled in the art that 'different isolation methods (e.g., dummy MOS gates or SBLs) can also be applied. [0024] The free stacking layer 312 of the MTJ 311 can be coupled to a supply voltage v, dipole 100129641 Form No. A0101 Page 16 / Total 59 Page 1003436465-0 201225092 Ο _ The end of the body 318 can be coupled to the supply voltage ν_, The 1> terminal of the diode 317 can be coupled to another power supply V+. In Figure 8a, the programmer can achieve this by applying high dust (ie 2V) to V+ and [while keeping ¥ at ground or (10). For programming 1, current flows from diode 317 through MTJ 311, while diode 318 is in an off state. Similarly, programming can be achieved by applying a high-power waste (ie 2V) to V and keeping VH〇v_grounded. In this situation, the peach flows from the '311 through the dipole Zhao 318, while the diode 317 is in the off state. Figure (4) shows a ship-time storage unit 31G, (d) - a cross-sectional view of the embodiment ο. According to this embodiment, it includes the MTJ 311' and the junction diodes 3', and 318' as programming selectors. The anode 311 has a free stacking layer =, a fixed stack layer 313, and a dielectric between them to form a magnetic junction. The diode 317, which is used to program 1 and the diode, is used for Cheng Cheng. The diodes 317' and 318' have P+ and N+ active regions at _21, and 320, respectively, and the N well must be. % is made with shallow wells that are additionally processed, although ‘, , and still require more processing steps. Two _17, there is P + active area 315, the volume can be composed to program i dipole 317, ° + active area 31, right p + 士 and W Similarly, diode 318 has P + active area 316, and _ two (10) end of the polar body 318. ^ , to form programming 〇 used to isolate different active areas 0 [0026] MTJ 311 free heap is sound 312 ' · 5τ, diode 318, material source voltage VW〗 7, _ & source voltage V- And the diode 3 can be consumed to the power supply voltage v, when it can be used. In Figure 11b, the voltage is achieved by applying a high voltage (ie (7) to V+ and v_, while 100129641 form number fiber ^ 17 I / * 59 I 1003436465-0 201225092 keep V ground or GV. For programming 1, current through MTJ 3U, flowing through the diode 317', while the diode 318 is in an off state. Similarly, the 'engraving can be achieved by applying a high voltage (ie, 4 2v) M and maintaining V + and V - ground. In this case, the current will flow from the MTJ 3H through the diode 318, and the diode will be in the off state. [0027] Figure 9a shows an embodiment of a two-terminal 2 Χ 2 _ storage cell array The diodes 3 and 318 are used as programming selectors, and the conditions for programming the memory cells are displayed. The memory cells 31 (a) g, 3 ι〇〇ι, 310-10, and 310-11 constitute a two-dimensional array. The memory is single (10) 〇 _ 〇〇 has a blunder 31 (10), - programming 1 diode 3 Π - 00 and - programming 〇 diode 318 GG. Order 311 - GQ - the end is turned to the power supply voltage v, the other end is face to programming The N-terminal of the diode is P and the P terminal of the 〇 diode 318-00 is programmed. Programming! The p-side of the diode 317_〇〇 is bonded to A power supply voltage V+ programming G_ pole body 318_Q () _ end she is connected to a power supply voltage. Other memory units 31Q, 3UM 〇 and 31 (j_u have similar coupling σ in the peer storage unit 31 10 one (10) and The voltage v is connected to the bit 7C line 〇 (BL 〇). The voltage V at the same-line memory cells 31 〇〇 1 and 310 -11 is connected to the bit line (10) (1). The memory cells 310 in the same column are 〇〇 and 310_01 The voltages V+ and V- are connected to the word line movements P and WLGN, respectively. The voltages V+ and V- of the same-column memory cells 31〇_1〇 and 31011 are respectively connected to the word line WLlpiaWUN. To the memory cell 3H1-G Bu hole (4) set to high voltage, BL1 is set to low voltage, and set the other and the appropriate voltage, as shown in Figure 9a 'to make other programming 1 and programming 0 diodes Disable»The thick black line in Figure 9a shows the direction of current flow. 100129641 Form No. A0101 Page 18 of 59 1003436465-0 201225092 LUUZ»J This is another embodiment, the description will be a 2X2 In the MRAM memory cell array, the memory cell 31 〇~〇1 is programmed to another condition of 1. For example, BL1 and WL0P are respectively set. The voltage and the high voltage are used to program the memory cell 31 to 1. If BL is set to a high voltage in Condition 1, η 〇Ν and WL1N may be high voltage or floating, and wup may be low voltage or floating. The high and low voltages of MRAM in today's technology are approximately: high voltage 2 - 3V and low voltage 〇. If 乩〇 is floating in condition 2, 扎(10) and WL1N can be high voltage, low voltage, or floating, and WL1P can be low ❹ voltage or ocean wave. In practice, floating nodes are typically coupled to a fixed voltage via very weak components to prevent leakage. In the embodiment shown in Fig. 93 programmed to 1 condition, there is no floating node. Figure 10a shows an embodiment of a three-terminal 2X2 MRAM memory cell array that includes MTJ 311 and junction diodes 317 and 318 as programming selectors, and displays the conditions for programming memory cells. These memory cells 310-00, 310'01, 310-10, and 310-11 form a two-dimensional array. The storage unit 31G has - commits 31 divination () 'programming! Diode Ο 317-00 and programming 0 diode 318-00 〇 MTJ 311-00 - terminal is coupled to the supply voltage V 'the other end is connected to the {^ terminal of the programming 1 diode 317-〇〇 And program the P terminal of the diode 318-00. The P terminal of the programming 丨 diode 317_〇〇 is coupled to the supply voltage V+. The 1^ terminal of the programming 0 diode 318-〇〇 is coupled to a supply voltage v_. Other memory cells 31〇_〇1, 310-10, and 31〇-11 have similar couplings. The voltage v at the same row of memory cells 310-00 and 31〇-10 is connected to the bit line BL〇. In the same -' hit the memory early tc31〇-〇h〇310-U voltage is connected to Bu. The voltages 卩+ and ¥ in the same column of memory cells 310 00 and 310_01 are respectively 100129641 Form No. A0101 Page 19 of 59 1003436465-0 201225092 is connected to the word lines WL0P and WL0N. The voltages V + and V - of the memory cells 310-10 and 31 0-11 in the same column are connected to the word lines WL1P and WL1N, respectively. As shown in Figure l〇a, in order to write to memory cell 310-01, WL0N is set to low voltage 'BL1 is set to high voltage, while other BL and WL are set to the appropriate voltage for other programming 1 and programming 〇 Dipole depletion. The thick black line in Figure 1a shows the direction of current flow. [0030] FIG. 10b shows another embodiment for explaining the condition of programming the memory cell 310-01 in the 2χ2 mram# memory cell array of the three terminals to the 〇. For example, setting BL1 and WL0N to a low voltage and a high voltage, respectively, can store memory cell 310-01 as 〇. In Condition 1, if BL〇 is set to a low voltage, WL0P and WL1P may be low voltage or floating, and the hole (7) may be high voltage or floating. The high and low voltages of MRAM in today's technology are approximately: high voltage 2-3V and low voltage 〇. In condition 2, if (10) is floating, WL0P and WL1P can be high voltage, low voltage, or floating and WL1N can be high power or floating. In actual implementation, the floating node is covered by a very weak component to a fixed voltage to prevent thirst. Figure 10a shows an embodiment programmed to the 〇 condition, wherein there is no [0031] one by one m "dry gate storage unit is the end storage unit, that is, the storage element has V, V leaching node, ^ fruit programming power TMP is less than Double the critical electric charge of the diode ΓΓΓ 'R—the v^v of the storage unit—the node can be connected as the double-ended fine unit. Since the Tvd is about 6_^ at room temperature, 100129641 is low in age. 2V, this kind of double-ended memory unit can work normally. UMRAM array is common in advanced circle technology, form number A0101 page 20/59 page 1003436465-0 201225092 [0032] Ο

[0033] It has a power supply voltage of m.GV. Figure 11a and the circuit diagrams showing programming 1 and 〇 in a 2X2 MRAM array with two ends, respectively. Figures A and m show examples of programming 1 and 分别, respectively, in an m-array with MRAM memory cells at both ends. These memory cells 31〇〇〇, 3ι〇〇ι, 310-10 and “dipoles form a two-dimensional array. The memory cell has ΜΠ3U-00, a programming 丨 diode 317_QG and a programming 〇 diode 318- 00. The terminal of the MTJ 31 00 is coupled to the power supply voltage v, and the other end is coupled to the terminal of the programming 1 diode 317 - and the terminal P of the programming diode 318 - 00. The 13 terminal of the polar body 317_〇〇 is coupled to a power supply voltage V+. The N terminal of the programming 〇 diode 318_00 is coupled to another power source. The voltage V- 〇 if the condition of VDDP<2*ν(} is satisfied, the voltage ^+ and 乂_ can be connected together at the storage unit level. Other storage units 31 (&gt;_〇1, 31〇~10, and 310-11 have similar couplings. In the same row of storage units 31〇-〇0 and 310 The voltage ν of -10 is connected to bl. The voltage v of the memory cells 310-01 and 310-11 in the same row is connected to the BU. The voltages of the memory cells 310-00 and 31〇-01 in the same column ^ and Is connected to WL0. The voltage and V- of the memory cell Μ q_ 1〇 in the same column are connected to WL1. In order to write 1 to the memory cell 3l0-0l, wL0 is set to a high voltage, and BL1 is set to low. Press and set other 虬 and 虬 at the appropriate voltage, as shown in Figure 11a to disable the other programming 1 and programming 〇 diode. The thick black line in the figure shows the direction of current flow. 310-01 ' WL0 is set to low voltage, BL1 is set to high voltage, and other BL and WL are set to the appropriate voltage, as shown in Figure llb, to disable other programming 1 and programming 0 diodes. The thick black line in llb shows the flow of current 100129641 Form No. A0101 Page 21 / Total 59 Page 1003436465-0 201225092 Direction [0035] [0036] As shown in Figures 9a-llb, the MRAM memory cell is constructed The examples in a 2 χ 2 array are for illustrative purposes only. Those skilled in the art can arbitrarily change the number of rows or columns of memory cells in a memory, and the rows and columns are interchangeable 0 magnetic memory (MRAM) memory cells. Parallel or magnetic anti-parallel may change the stability of the memory cell with β. However, most applications need to retain data for ίο, and from operating temperature 0 to 85 γ or in order to be in the lifetime of the device and in Maintaining in such a wide temperature range The stability of the storage unit, the magnetic memory can be read out periodically, and then the data is written back to the same storage unit, which is an update mechanism. The update cycle can be quite long, such as more than one second (eg, minutes, hours, The day of the week, or even the month. The update mechanism can be generated internally by the memory or triggered from the outside of the memory. The long-term update cycle to maintain the stability of the memory cell can also be used to (4) other emerging memories such as resistive memory ( RRAM), conductive bridge random access memory (CBRAM) and phase change memory (PCM). According to another embodiment, a programmable resistive element can be used to create a memory. Figure 12a shows a portion of a programmable resistive memory 1''''''''''''''''''' 151-i (i = 〇1 is constructed. Memory array 101 has „! normal line and — reference line share a 100129641 sense amplifier for differential sensing. Each memory storage unit 11 has a resistive element 111 coupled to one. Programming the p-terminal of the diode 112 and the N-terminal of the programming diode 113. Programming the u diode u 2 and programming the diode u 3

Form No. A010I Page 22 of 59 1003436465-0 201225092 Select as a programming option 11. Each of the resistive elements 111 in the same-line of those memory storage units 11G is also transferred to the bit line BLj i7Q_j (Bu O'1' . .m) or the reference bit line BLR0 175-0. For those memories, the memory τοο HG is merged into the same-line two-pole m N-end of the same column, then 1 152] 'via the local word it line LWLNi 154-i (i 0'1, ,11丨). Those memory cells are coupled to the -word line WLPi 153_i at the p-side of the same-pole diode 113 via the local word line Ο LWLP1 155 1 (1 = Ο'1, ···, !!]). Each word line WLNi or WLPi is coupled to at least _ local word line LWLNe LWLP1 (1 = Ο, 1, , . . , n-l), respectively. The LWLNi 154-i and LWLPi 155-1 are generally constructed of _ high-resistance materials (such as N-well or polysilicon) and connected to the thin cells, and are hidden by conductive contacts or layers of indirect points, buffers or after The numerator 172-i or 173 _i (i = 0, 1, ..., nl) is coupled to the ritual or 叽^ (for example, the low resistance metal WLNi or WLPi). When a diode is used as the programming selector, a buffer 172-i or a post-decoder 173-i may be necessary because of the current flowing through WLNi or WLPi; especially in some embodiments when one WLNi or WLPi drives multiple Memory cells are used for simultaneous programming and reading. The word lines WLNi and WLPi are driven by the word line driver - i, respectively. For programming and reading, the supply voltage vddi can be switched between different voltages. Each BLj i7〇_j or BLR〇ι75_〇 is programmed via a Y-write-Ο channel closed (2) spoon or (3) coupled to a supply voltage VDDP, where each BLj 170-j or BLR0 175-0 They are selected by YS0WBj = 〇, 1, ..., ra-1) or YS0WRB0, respectively. Y-write-Ο channel gate 12 〇 ((^,...,^) or 125 can be constructed with PMOS; however NM〇s, diode or bipolar element is also 100129641 1003436465-0 Form No. A0101 Page 23 / A total of 59 pages 201225092 can be used in some embodiments. Similarly, each BLj 17〇—』 or BLRO 175-0 is programmed via a Y-write — ! channel gate 121j or 126 to a supply voltage of 0 V to program 1, where each rainbow j 170-j or BLR0 175-0 is selected by YSIWj ( j = 0, i, ) or YS1WR0, respectively. The Y-write-1 channel gate i2 j or 126 can be constructed with NM0S' whereas the PMOS, diode or bipolar element can also be used in some embodiments. Each BL or BLR is coupled to the data line or reference data line DLR0 via a Y-read channel gate 130-j or 135, selected by YSRj (j = 〇, 1, , ) or YSRR0, respectively. In the portion of the memory array ι〇1, the m normal data line DLj (j = 0, 1, ..., m-1) is connected to an input terminal 160 of a sense amplifier 140. The reference data line dlro provides the other input 161 of the inductive amplifier 140, however, no multiplexer is typically required in the reference subsection. The output of sense amplifier 140 is Q〇. [0037] To program a 0 to a memory cell, as shown in FIG. 1A or 10b, the specific WLNi, WLPi, and BLj are selected by the word line driver i5〇-i, 15 and the Y-pass channel gate. 120-j is selected by YSOWBj, where i = 0'1'.., nl and j = 〇, l, ..., mi, and other word lines and bit lines are also set appropriately. A high voltage is applied to VDDP. In an example, the reference memory early element can be programmed to zero by setting the appropriate voltage to WLRNi 158-i, WLRPi 159-i and YS0WRB0, where i = 〇, 1, ..., η-1. To program a 1 to a memory cell, as shown in Figure 仏 or 9b, the specific WLNi, WLPi and BLj are selected by the word line drivers 150-i, 15i, and the Y-pass channel gates 121-j are YslWB. i select 'where i = 〇, 1.. n - 1 and j = 〇, l, ..., m_l, and its 100129641 form number A0101 page 24 / total 59 pages 1003436465-0 201225092 his character line and The bit line is also set as appropriate. In some embodiments, the reference memory cell can be programmed to one by setting the appropriate voltage to WLRNi 158-i, WLRPi 159-i and YSlWROCi = 0'1, ..., n-i). To read a memory location, the data row 16 can be selected by opening a specific WLNi, WLPi and YSRj (where i = 0", and j = 0, 1, . . . , ml), and a reference data Line DLR 161 can be turned on by a particular reference memory cell, coupled to sense amplifier 140 to sense and compare the difference in resistance between 160 and DLR 161 and ground, while dividing all YSOWBj, YS0WRB0, ysiw 彳 and YS1WR0 I Yes, where j = 〇, 1,..., ml. [0038] FIG. 12b shows another embodiment of a two-terminal MRAM memory cell to form a memory. According to this embodiment, the VDDP voltage difference between the high and low states must be less than twice the threshold voltage Vd of the dipole, i.e., VDDP < 2 * Vd. As shown in Fig. 12b, the two word lines WLNi 152-i and WLPi 153-i of each column originally in Fig. 12a can be combined into a word line driver WLNi 152-i' where i = Ο, ΐ, .' ΗΗ. Further, as shown in FIG. 12 12b, the local word lines ULNi 154-i and LWLP 155-i of each column originally in FIG. 12a can be merged into a local word line LWLNi 154-i, where divination, 1, ' Nl. Further, the two word line drivers 150~i and 151-i in Fig. 12a can be combined into one, i.e., word line driver 150-1. The 61 groups and WLN groups of unselected memory cells are arranged with appropriate programming 1 and 〇 conditions, as shown in Ua and ub, respectively. Since half of the word lines, local word lines and word line drivers can be removed in this embodiment, the area of the memory cells and memory can be greatly reduced. 100129641 Form No. A0101 Page 25 of 59 1003436465-0 201225092 [0039] Figures 13 &amp; and 13b show flowchart embodiments depicting a programmable memory Jj and a memory memory programming method S700 and a reading method S800, respectively. Methods S7A and S800 describe the programming and reading of the programmable resistive memory 100 as shown in Figures 12a and 12b in the case of a programmable resistive memory. In addition, although it is a step-by-step process, it is known to those skilled in the art that at least some of the steps may be performed in a different order, including simultaneous or skipping. [_] Figure 13a depicts a flow chart of a programming method in a programmable resistor memory. According to this embodiment, in a first step S710, an appropriate power supply selector is selected to apply a high voltage power supply to the word line and bit line drivers. In a second step S720, the data to be programmed is analyzed in the control logic (in Figures 12a and i2b), depending on what type of programmable resistive element. For MRAM, the direction in which current flows through the MTJ is more important than the duration. The control logic determines the appropriate power selector for the word line and bit line and initiates a control signal to ensure that the current flows through the desired direction for the desired amount of time. In a third step S73, a column (group) of memory cells is selected, so that the relative local word lines can be turned on. At the fourth + step S740, the sense amplifier is deactivated to save power and prevent interference to the programming operation. In a fifth step S750, the row (group) of memory cells can be selected and the corresponding Y-Write channel gate can be opened to rotate the selected bit line to a supply voltage. At the last step 576, the programmed operation is completed at the time that the established path has been established by Q to drive the required current for a period of time. For most programmable resistor memories, this conduction path is made by a high voltage supply, through the selected bit (10), the resistive element, the diode as the programming selector, and the NMOS pull-down element of the local word line driver to ground. Especially for the compilation #present i to one 隠m, pass 100129641 Form No. A0101 Page 26 / Total 59 Page 1003436465-0 201225092 Guide path 尚 by Shangwu power supply, through the pull-up component of the local word line driver' as a programming choice The diode of the device, the resistive element, the selected bit line to ground. [0041] FIG. 13b depicts a flow of a programmable resistive memory read method S800 in accordance with an embodiment. In a first step S810, a suitable power selector is provided to select the supply voltage to the local word line driver, the inductive amplifier and other circuitry. In a second step S820, all gamma-write channel gates, such as bit line programming selectors, can be turned off. The local word line driver (group) required in the third step S830' can be selected such that the diode (group) as a program selector (group) has a conductive path to ground. In a fourth step S840, the sense amplifier (group) and the input signal for the induction are activated. In a fifth step S850, the data line and the reference data line are precharged to the V-voltage of the programmable resistive element memory cell. In a sixth step S860, the desired Y_read channel gate is selected to cause the desired bit line to be tapped to an input of the sense amplifier. A conduction trajectory is then established, from the bit line (group) to the resistive element of the desired memory cell, as a diode (group) of the programming selector (group) and a pull-down element of the local word line driver (group) To ground. The same applies to the reference branch. In the last step S870, the sense amplifier can determine the difference between the current and the reference current to determine whether the logic output is 〇 or! To complete the read operation [0042] Figure 14 shows a processor system 7A in accordance with another embodiment. In accordance with this embodiment, processor system 7A can include a programmable electrical component 744 in memory cell array 742 in memory 740. Processor system 700 may, for example, be a computer system. The computer system 4 includes a central unit 100129641, form number A0101, page 27, page 59, 1003436465-0, 201225092, a unit (CPU) 710, which communicates with various memory and peripheral devices via a common bus 715, such as an input/output unit. 720, hard disk drive 730, optical disk 750, memory 740, and other memory 760. Other memory 760 is a conventional memory such as static memory (SRAM), dynamic memory (DRAM) or flash memory that is typically communicated to central processing unit 710 via a memory controller. Central processing unit 710 is typically a microprocessor, digital signal processor, or other programmable digital logic component. Memory 740 is preferably constructed in an integrated circuit that includes a memory array 742 having at least programmable resistive elements 744. Typically, memory 740 contacts central processing unit 710 via a memory controller. If desired, the memory 740 can be combined with a processor (e.g., central processing unit 710) in a monolithic integrated circuit. [0043] The invention may be implemented in part or in whole on an integrated circuit, on a printed circuit board (PCB), or on a system. The programmable resistive element can be a fuse, an anti-fuse or an emerging non-volatile memory. The fuse may be a deuterated or non-deuterated polysilicon fuse, a thermally isolated active region fuse, a metal fuse, a contact fuse, or a layer indirect fuse. The antifuse can be a gate oxide breakdown antifuse, a dielectric junction or a layer indirect antifuse. Emerging non-volatile memory devices can be magnetic memory (MRAM), phase change memory (PCM), conductive bridge random access memory (CBRAM) or resistive random access memory (RRAM). Although the programming mechanisms are different, their logic states can be distinguished by different resistance values. [0044] The above description and drawings are merely illustrative of implementations that are believed to be illustrative of the features and advantages of the invention. The specific process conditions, structural modifications and alternatives can be achieved by the form number A0101, page 28 of 59, 1003436465-0 201225092 [0045] ο ο 100129641 1003436465-0 without departing from the spirit and scope of the present invention. [Simple description of the diagram] The circuit of the circuit can be edited (4) Resistive memory storage element. Another traditionally used resistor for the =ar phase change memory (PCM) is a circuit diagram that uses a bipolar transistor as a programming selector. Figure 2b shows another conventional phase change memory (PCM) memory cell circuit diagram which employs a three-pole_program selector. 2^31&gt; The readout is programmed by the current direction to the conventional magnetic memory (10) AM): the early magnetic solution (or „W and anti-parallel (filamental 丨) magnetic direction schematic. Figure 4 shows a block diagram, including according to the invention The use of at least a two-pole memory cell is a cross-section of a junctionless diode. According to this embodiment, a two-pole wash trench isolation (STI) is used to isolate the anode and cathode, and when programming is selected The cross-section of the junction diode is shown. According to this embodiment, the two use a dummy CMOS gate to isolate the anode and cathode, and when programming the selector Figure 5c_ + » 横截 a cross-section of the junction diode. In this embodiment, the Dreaming Barrier Layer (SBL) is used to isolate the anode and cathode, and when programming the selector, Figure 6 a li; .. the shoulder is not connected to the cross-section of the diode. According to this embodiment, This diode isolates the anode and cathode with a dummy CMOS gate in the Insulator Base (SOI) technique and when the selector is programmed. Figure 6b shows a cross section of a junction diode. According to this embodiment, Fake-type field effect transistor (FINFET) technology in the polar body CMOS gate to form A0101 Page 29 of 59 201225092 Isolating the anode and cathode, and when programming the selector. Figure 7 shows the circuit diagram of the programming selector used in the embodiment of the AM memory cell. - Pole, display - top of the MRAM cell View. According to this junction, the magnetic tunnel-pole W light resistance and the standard (10) S process Ρ + / one pole body as a programming selector. The well diagram shows the top view of the other - MRAM memory unit. According to this _ Use the magnetic tunnel junction (Mm you "Wa Shishi" (1) as the resistor element and the shallow well CM0S process well one as the programming selector. Figure 9a shows one and two 嫂w diagram, B memory cell array The embodiment &quot; uses a polar body as a program selector. And according to this embodiment, the upper right storage unit is set to a condition of 1. - Figure 9b shows another _ embodiment status list, which is stored along the mRAM The upper right storage element _ is a condition of 1. The l array l_0a shows a three-terminal 2 χ 2 just storage unit array does not think 'the (four) surface diode as a braided chest. Example 'programming the upper right storage unit is a strip Figure (10) shows another embodiment status list, the conditions of the upper right storage unit of the 2X2 coffee storage array are programmed &amp; 0. Figures 1U and Ub show a schematic view of the embodiment, at the 2nd end of the 2 Χ 2 MRAM storage In the elementary position, the upper right side of the storage element and the 0 〇 π 1 picture display - the schematic diagram of the part of the shoe-resistant resistive memory. According to this embodiment, the MRAM array is composed of three end-point memory cells. A schematic diagram of another embodiment is shown in which a memory of a part of MR AM is formed by a memory of two endpoints. 100129641 Form number leg 01 page 30/59 page ^03436465 201225092 Figure 1 3 a depicts a method to program Flowchart of Programmable Resistive Memory Figure 13b depicts a flow diagram for reading a programmable resistive memory. Figure 14 shows a schematic diagram of an embodiment of a processor system. [Main component symbol description]

[0014] Memory Cell 10 [0048] NMOS Device Selector 12 [0050] Programmable Resistive Element 20, 20, [0051] Phase Change Film 21, 21' [0052] Bipolar Transistor 22 [0053] P+ Emitter 2 3 [0054] N-type Base 27 [0055] Collector 25 [0056] Diode 22' [0057] Memory Cell 210 [0058] Magnetic Tunnel Junction 211 [0059] Programming selector 218 of NM0S Form No. A0101 100129641 Page 31/59 page 1003436465-0 201225092 [0060] Freely stacked layer 2 1 2 [0061] Fixed stacked layer 213 [0062] [Invention] [0063] Memory storage unit 30 [0064] Memory element 3 0a [0065] Diode 3 2a, 32b [0066] Diode 32, 32', 32" [0067] P+ active area 33, 33', 33" [0068 N Well 34, 34', 34" [0069] N+ Active Region 37, 37', 37" [0070] Shallow Trench Isolation 36, 36' [0071] Active Region 31', 3Γ [0072] Gate 39' [0073] Telluride Barrier Layer 39" [0074] Substrate 35, 35', 35" [0075] Junction Dipole 45 [0076] Island Region 31-1, 3 Bu 2, 3 Bu 3 [0077] MOS Gate 39-1, 39-2, 39-3 [0078] 矽Zone 40-1 and Zone 40-2 100129641 Form No. A0101 Page 32 of 59 1003436465-0 201225092

L0079J P+ active area 33-1, 2, 3, [0080] N+ active area 37-1, 2, 3 [0081] P + implanted layer 38' [0082] MRAM memory unit 310, 310' [0083] MTJ 311 , 311' [0084] junction diodes 317, 318, 317', 318, [0085] freely stacked layers 312, 312' [0086] fixed stacked layers 313, 313 ' [0087] N wells 321, 320, 321 '320, [0088] P+ active area 315, 316, 315', 316' [0089] N+ active area 314, 319, 314', 319' [0090] STI 330, 330' [0091] storage unit 310-00, 310-01, 310-10, [0092] Programming 1 Diode 317-00 [0093] Programming 0 Diode 318-00 [0094] Programmable Resistor Memory 10 [0095] Array 101 [0096] Memory Memory Unit 110 [0097] Resistive Element 111 310-11 Form No. A0101 Page 33 / Total 59 Page 100129641 1003436465-0 201225092 [0098] Programming 0 Dipole 11 2 [0099] Programming 1 Diode 11 3 [0100] Reference Bit Line BLR0 175-0 [0101] Word Line Driver 150-i [0102] Bit Line BLj 170-j [0103] Local Word Line LWLNi 154-i [0104] Word Line WLPi 153-i [ 0105] Local word line LWLNi, LWLPi [0106] Y-write-〇 channel gate 12〇-〇j, 125 [0107] Y-write-1 channel gate 121-j, 126 [0108] sense amplifier 140 [0109] input terminal 1 60, 1 61 [0110 Y-read channel gate 130-j, 135 [0111] Step S700-S760, S800-S870 [0112] Processor system 700 [0113] Memory 740 [0114] Programmable resistance element 7 4 4 [0115] Memory unit Array 742 [0116] Central Processing Unit 710 100129641 Form Number A0101 Page 34 / Total 59 Page 1003436465-0 201225092

LUll/J

[0120] [0122] [0122] 共同 Common bus 715 Input/output unit 720 Hard disk drive 730 Optical disk 750 Memory 740 Other memory 760 ο 100129641 Form number Α 0101 Page 35 / Total 59 pages 1003436465- 0

Claims (1)

201225092 VII. Patent application scope: 1 · A memory comprising: a plurality of memory storage units, at least - the memory storage unit comprises: - the memory element has a first end and a second end, the first end is faceted to the first a power supply voltage line; and - the second diode includes at least a first end and a second end, wherein the first end has a -type-type doping, and the second end has a second type of doping, the first The first end of the diode is coupled to the second end of the memory component, and the second diode includes at least a first end and a second end, wherein the first end has a first type Doping, the second end has a second type of doping, the second end of the second diode is coupled to the second end of the memory element; wherein the second of the first diode The end is coupled to a second supply voltage line, wherein the first end of the second diode is summed to the second or third supply voltage line; wherein 'the memory element is configured to be programmable to different Logic state by applying a voltage to the first, second and/or third power source Pressure line, thereby turning on the first diode and a cut off of the logic state of the second diode, or the second conducting diode is cut off the first diode to the other logic state. 2. The memory of claim 1, wherein the memory element is a magnetic tunnel junction (MTJ) consisting of a fixed stack of multi-layered ferromagnetic or antiferromagnetic stacks, and a multi-layered iron Free stacking layer of magnetic or antiferromagnetic stacks 100129641 Form No. A0101 Page 36 / Total 59 pages 1003436465-0 201225092 'The insulator is between the two stacked layers. According to the claim 2, the memory element is a magnetic tunnel junction (MTJ) on the surface of the hair. The memory of claim 2, wherein the memory element is a magnetic tunnel junction (MTJ) and the first or second source voltage line is obliquely elliptical on the surface of the crucible. The memory of claim 1, wherein the memory element is a metal oxide between a metal or metal alloy electrode and an electrode. The memory of claim 1, wherein the memory element is a solid electrolyte membrane between the electrode and the electrode. The memory of claim 1, wherein at least one of the diodes is a junction diode, and the first and second active regions are present in the well as both ends of the diode. The memory of claim 1, wherein at least one of the two poles is a junction diode, and the first and second active regions are present in the well as the ends of the diode, and the The well is used to manufacture a MOS semiconductor ((1108) component. 9. The memory of claim 1, wherein at least one of the diodes is a junction diode, and the two active regions are The two ends of the diode are separated by a dummy MOS gate. 10. The memory of claim 2, wherein at least one of the diodes is a junction diode, and two active regions thereof The two ends of the diode are separated by a shallow trench. 11 The memory of claim 1, wherein at least one of the diodes is a junction diode, and the two main pure As the two ends of the triode, and separated by a telluride barrier layer. 100129641 Form No. A0101 Page 37 / Total 59 Page 1003436465-0 201225092 12 . — Memory 'includes: Multiple memory storage units, at least one memory The storage unit includes: a memory element having a first end and The first end is turned to a first power voltage line; and the first one body includes at least a first end and a second end, wherein the first end has a first type of doping, The second end has a second type of doping, the first end of the first diode is coupled to the second end of the memory element; and the first diode includes at least a first end and a second An end, wherein the first end has a first type doping, the second end has a second type doping, and the second end of the second diode is coupled to the second end of the memory element) Wherein the second end of the second diode and the first end of the second diode are coupled to a second supply voltage line; wherein the TL component is configured to be programmable to a different one a logic state, by applying a voltage to the first and second supply voltage lines to turn on the first body, cutting the second diode to a logic state or turning on the second diode (10) The first-secondary body to another-logic state. Ϊ 3. An electronic system comprising: a processor; and a memory operatively coupled to the processor, the memory comprising at least a plurality of hidden memory sheets 70 for providing data storage, each memory The wrong unit includes a first memory element having a first end _ 鸲 and a second end, the first end being coupled to a first supply voltage line; and a first diode comprising at least one end having a first type of doping Miscellaneous form number A0101 when - first end and second end, wherein the first 100129641 'the second end has a second type of doping page / total 59 pages 1003436465-0 201225092, β Xuan first diode The first end is coupled to the second end of the memory component, the second end of the first diode is coupled to the second power voltage line 9 Ο a second pole body includes at least one first And a second end, wherein the first end has a first type doping, the second end has a second type doping, and the second end of the second diode is coupled to the memory element The second end, and the first end of the S衾 second diode is coupled to the first a second or a third supply voltage line; wherein the memory element is configured to be programmable to a different logic state, by applying a voltage to the first, second, and/or third supply voltage lines, thereby turning on the second The pole body cuts off the second diode to a logic state, or turns on the second diode to cut the first diode to another logic state. 14. The electronic system of claim 13, wherein the electronic system is configured to periodically read the contents of each of the storage units and write back the content. 15 · A method for providing a memory, comprising: ο 100129641 providing a plurality of memory storage units, at least one memory storage unit comprising at least (1)-memory elements having first and second ends, the first end being flanked by - a power supply voltage line; and (ii) a first diode comprising at least a first end and a second end, the first μ having a first type doping and the second end having a first type doping The first end of the first diode is engaged to the first end of the Z It 7G member and the second end of the second diode is engaged to the second power voltage line; The second diode comprises at least a first end and a second end 'the first end having a first type doping, the second end having a second type doping, the first providing a second (four) - The first end, the first one of the first-second diode-Chu-λΟι, the second end of the second diode form number Α0101, page 39/total 5q hundred' y Ά 1003436465-0 201225092 Coupled to the second end of the memory element and the first end of the second diode is coupled to the second or a third supply voltage line; The memory element is configured to be programmable to a different logic state, by applying a voltage to the first, second, and/or third supply voltage lines, thereby turning the first diode off and cutting the second The diode is in a logic state, or the second diode is turned on to cut the first diode to another logic state. 100129641 Form No. A0101 Page 40 of 59 1003436465-0