201221004 六、發明說明： 【發明所屬之技術領域】 本發明係關於配線基板的製造方法。 【先前技術】 ^近年來，盛行使用一種分別至少積層一層導體層及 樹脂絕緣層且於最表面形成有阻焊劑層而構成的配線基 板即所5胃樹脂製配線基板，並於此基板上搭載丨c晶片 而藉以製造半導體封裝體。 1C晶片係經由形成於配線基板之主表面上的晶 片搭載σ卩的焊墊上之焊料凸塊而與配線基板電性連捿。 另方面’於配線基板之背面側形成有用以與底基板電 性連接或者插入於插座内而電性連接的外部端子。 該焊料凸塊係藉由於配線基板之主表面上印刷糊狀 焊料並進行迴焊而形成為半球形。 然而’該糊狀焊料之迴焊係將配線基板放入加熱裝 置内而進行者，所以，於該焊料凸塊之形成時，會有因 配線基板受熱而發生翹曲的問題。此種翹曲尤其是在配 線基板之1C晶片搭載部上特別會造成問題，因該晶 2格載部之翹曲的緣故而會產生導致無法充分地進行Ic 曰曰片與配線基板間的經焊料凸塊之電性連接的問題。 、。鑒於此種問題，於專利文獻丨中，嘗試在糊狀焊料 之迴焊時，使用保持治具將配線基板固定於底座上，以 減低加熱引起之配線基板的翹曲。 .然而’該配線基板不僅僅是在該糊狀焊料之迴焊時 破進行加熱處理，於其整個製造過程中亦會經過各種之 -4 - 理亦會產生趣 時，需要對經 減小此勉曲之 此禋俊加热處 201221004 熱處理及機械處理，最終因這些處 此，在提供配線基板作為最終產品 製造方法而獲得之配線基板進行能 處理。 線基板，藉由將此配線基板固定於支撐台上，』 線基f加熱至阻焊劑層之玻璃轉移點的溫度以」 藉規定之按壓治具將配線基板整體向支撐台按肩 者:根據此方法’雖可充分減小配線基板之㈣ 為是在阻焊劑層t玻璃轉移點以上的溫度下進;f 曲之操作’所以，會於配線基板之表面、即阻上 表面形成該按壓治具的接觸痕跡。 立此種接觸痕跡將使外觀性變差，&而不截 、"疋在Ic晶片搭載部上，會將進行ic g 線基板之雷，14 $ α , U 接的焊料凸塊壓潰，而有無法〖 灯這些電性連接之問題。 專利文獻 專利文獻1 Β 士 4士 ea。 【發明内容】 1 3-234366號公報 [發明所欲解決之課題]201221004 6. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of manufacturing a wiring board. [Prior Art] In recent years, a wiring board made of at least one layer of a conductor layer and a resin insulating layer and having a solder resist layer formed on the outermost surface thereof has been widely used, and is mounted on the substrate. The c-chip is used to fabricate a semiconductor package. The 1C wafer is electrically connected to the wiring substrate via solder bumps on the pads of the σ卩 mounted on the main surface of the wiring substrate. On the other hand, an external terminal for electrically connecting to the base substrate or being electrically inserted into the socket is formed on the back side of the wiring board. The solder bump is formed into a hemispherical shape by printing paste solder on the main surface of the wiring substrate and performing reflow soldering. However, the reflow soldering of the cream solder is carried out by placing the wiring board in the heating device. Therefore, when the solder bump is formed, there is a problem that the wiring board is warped due to heat. Such warpage particularly causes a problem in the 1C wafer mounting portion of the wiring board, and the warpage of the crystal 2 carrier portion may cause the Ic film and the wiring substrate to be insufficiently formed. The problem of electrical connection of solder bumps. ,. In view of such a problem, in the patent document, attempts have been made to fix the wiring board to the chassis by using a holding jig during reflow of the paste solder to reduce warpage of the wiring substrate due to heating. However, the wiring substrate is not only subjected to heat treatment during the reflow of the cream solder, but also undergoes various kinds of processing during the entire manufacturing process. This is the heat treatment and mechanical treatment of the 禋Jun heating unit 201221004. Finally, the wiring board obtained by providing the wiring board as the final product manufacturing method can be processed. The wire substrate is fixed to the support table by the wiring substrate, and the wire base f is heated to the temperature of the glass transfer point of the solder resist layer by pressing the jig to the support table by the predetermined pressing jig: This method can sufficiently reduce the (4) of the wiring substrate to be at a temperature higher than the transfer point of the solder resist layer t; the operation of the f-curve, so that the press treatment is formed on the surface of the wiring substrate, that is, the upper surface of the resist With traces of contact. The appearance of such contact marks will deteriorate the appearance. & not cut, " on the Ic chip mounting portion, the solder bumps of the ic g-line substrate will be crushed, 14 $ α , U solder bumps will be crushed However, there is a problem that these electrical connections cannot be made. Patent Literature Patent Document 1 Β士 4士 ea. SUMMARY OF THE INVENTION 1 3-234366 [Problem to be solved by the invention]
本發明$ a λα I β之目的在於提供一種新穎製造方法 分別至少積芦— a 層導體層及樹脂絕緣層且於最^ 有阻焊劑居& 1 續而構成的配線基板作為最終產品時 其表面形虏+ 要觸痕跡而可減小配線基板的翹曲 達成平坦化。 曲。因 過上述 後加熱 層的配 在將配 之後， 而進行 ，但因 減小翹 劑層之 讓人滿 片與配 好地進 在提供 面形成 不會於 進而可 -5- 201221004 [解決課題之手段] 為了達成上述目的，本發明係關於一種配線基板的 製造方法，其特徵為具備以下製程： 將分別至少積層一層導體層及樹脂絕緣層且於最表 面形成有阻焊劑層而構成的配線基板配置於支撐台上的 製程；及 藉由形成有凹部之平板狀治具，使該凹部位於該配 線基板之1C晶片搭載部上，且在該1C晶片搭載部與該 治具分離的狀態下，加熱該配線基板並對該支撐台進行 按壓的製程； 且該治具之位於該凹部外側的按壓面的表面粗度係 與該阻焊劑層的表面粗度對應而被粗化。 根據本發明’在將分別至少積層一層導體層及樹脂 絕緣層且於最表面形成有阻焊劑層而構成的配線基板配 置於規定之支撐台上之後，使用形成有凹部之平板狀治 具’使此治具之凹部位於配線基板之1C晶片搭載部上， 且在此IC晶片搭載部與治具分離而不接觸的狀態下，藉 由治具將配線基板按壓於支撐台上，以減小翹曲。 此時’治具之位於凹部外側的按壓面的表面粗度係 與P «I層之表面粗度對應.而被粗化，所以，如上述， 即使在藉治具按壓配線基板時’仍不會因該按壓面之按 壓而於該阻烊劑層上產生接觸痕跡。The purpose of the present invention is to provide a novel manufacturing method in which at least a layer of a conductor layer and a resin insulating layer are formed, and the wiring substrate composed of the most solder resist is used as a final product. The surface shape 虏+ can be traced to reduce the warpage of the wiring substrate to achieve flattening. song. Since the distribution of the above-mentioned post-heating layer is carried out after the dispensing, the formation of the full-faced sheet and the matching surface of the warping layer is not formed in the form of the supply surface -5 - 201221004 [Solution of the problem] In order to achieve the above object, the present invention relates to a method of manufacturing a wiring board, comprising the steps of: forming a wiring substrate in which at least one conductor layer and a resin insulating layer are laminated and a solder resist layer is formed on the outermost surface; a process disposed on the support table; and a flat-shaped jig having a concave portion formed on the 1C chip mounting portion of the wiring substrate, and in a state in which the 1C wafer mounting portion is separated from the jig a process of heating the wiring board and pressing the support table; and a surface roughness of the pressing surface of the jig outside the concave portion is roughened corresponding to a surface roughness of the solder resist layer. According to the present invention, after a wiring board having at least one conductor layer and a resin insulating layer laminated thereon and a solder resist layer formed on the outermost surface is disposed on a predetermined support base, a flat jig formed with a concave portion is used. The recessed portion of the jig is placed on the 1C chip mounting portion of the wiring board, and the wiring board is pressed against the support table by the jig in a state where the IC wafer mounting portion is separated from the jig, and the warp is reduced. song. At this time, the surface roughness of the pressing surface on the outside of the concave portion of the jig is corresponding to the surface roughness of the P «I layer, and is roughened. Therefore, as described above, even when the wiring board is pressed by the jig, it is not Contact marks are formed on the resist layer due to the pressing of the pressing surface.
另外’配線基板之1C晶片搭載部一般係位於其中心 部，在像習知技術那樣以整個治具全部按壓配線基板的 隋'兄下，貫質上會被施加很大的外力，從而會將進行IC 201221004 晶片與配線基板之電性連接的焊料凸塊壓潰，而無法良 好地進行這些電性連接。 另方面於本發明令，使用形成有凹部之平板狀 治具，使此平板狀治具之凹部位於配線基板之ic晶片搭 載部上，且以ic晶片搭載部與平板狀治具不接觸的方式 配置之後進行按麼。因此在按壓.時，實質上不會按壓到 配線基板之1C晶片搭載部，所以，不會有將進行IC晶 片與配線基板之電性連接的焊料凸塊壓潰的情況。結果 可良好地進行這些電性連I。 、於本發明之-例中，以在將該阻焊劑層表面區分為 與治具之該按壓面接觸沾拉 觸的接觸面及不與治具接觸的非接 觸面的情況下’於藉平板狀治具進行按塵之製程之後， 以接觸面之算術平均矣 表面粗度Ra與非接觸面之算術平 、句表面粗度Ra的差成為〇 〇3叫以内且接觸面之十點 平均表面粗度Rz斑非技經 ’ 、非接觸面之十點平均表面粗度Rz的 圭成马0.3μιη以内的古斗、&广 丄L 的方式對按壓面進行粗化較為適宜。 如此，以使接觸面鱼非 、且 ，、非接觸面之表面粗度的差成為如上 述之較小值的方式斜姑；@ I & 飞對按壓面進行粗化，所以， 地抑制將治具按壓於两 更有效 …冰基板時的接觸痕跡的產生。 另外，於本發明之一例中，以於 按壓之製程之前，相 千板狀具進行 ^平板狀治罝之Γ 層之算術平均表面粗度 面粗度為：:〇〇心。”卜側的按麼面的算術平均表 層之十點平Μ面+ _ 33·00倍以下’相對於阻焊劑 的按壓面的十點平β ⑺八之位於凹部外側 十點干均表面粗度Rz“.〇〇倍以上14〇〇 201221004 倍以下較為適宜。藉由將平板狀治具之按壓面的表面粗 度，如上述適宜地設定為比阻焊劑層表面大的值，可在 將治具按壓於配線基板時減小配線基板的翹曲，並可更 有效地抑制接觸痕跡的產生。 又，於本發明之一例中，以在阻焊劑層之玻璃轉移 溫度以上的溫度下，執行以該平板狀治具按壓配線基板 時的溫度較為適宜。藉此，可更有效地抑制因該按壓造 成之配線基板的翹曲。另外，即使在以此種溫度進行按 壓的情況下，藉由採用本發明之方法’仍可抑制例如因 上述作用效果所引起之對配線基板產生的接觸痕跡。 [發明效果] 如上述說明，根據本發明，可提供一種新穎製造方 =，在提供分別至少積層一層導體層及樹脂絕緣層且於 =表面形成有阻焊劑層而構成的配線基板作為最終產品 ¥不會於其表面形成接觸痕跡而可減小配線基板的翹 曲’進而可達成平坦化。 【實施方式】 以下，參照圖面，針對本發明之實施形態進行說 (配線基板） 先’針對使用於本發明之方法的配線基板的構成 進仃說明。但以下所示之配線基板僅為例示，只要是分 別至少積層-層導體層及樹脂絕緣層且於最表面形：： 阻焊劑層而構成的樹脂製配線基板，並無特別之限制。 第1及第2圖為本實施形‘態之配線基板的俯視圖， 弟1圖顯示從上側觀察該配線基板時的狀態，第2圖顯 -8 - 201221004 示從下側觀察該配綠萁 土板時的狀態。另外，第3圖為沿 I-Ι線切斷第1及篦？_ 次笫2圖所不之該配線基板時的截面之一 部分的放大示意圖，第4圖為沿Π-Π線切斷帛i及第2 圖所示之該配線基板時的截面之-部分的放大示意圖。 第4圖所示之配線基板1係於由耐熱性樹脂 板（例如，雙馬來醯亞胺三啩樹脂板）、纖維強化樹脂板㈠列 如，玻璃纖維強化環氧樹脂）等構成之板狀芯基板2的兩 表面藉由錢銅分別形成有構成形成為規定圖案之金屬 配線7a的芯導體層M1、M1丨（亦簡稱為導體層）。這些芯 導體層1VH、Ml 1係作為覆蓋板狀芯基板2表面之大部分 的面導體圖案而被形成，且用作為電源層或接地層。 另外，於板狀芯基板2上形成有藉鑕頭等所穿設之 通孔1 2，並於此通孔之内壁面形成有使芯導體層M工、 Μ1 1相互導通的通孔導體3 〇。另外，通孔1 2被環氧樹 脂等之樹脂製填孔材3 1所填埋。 另外’於芯導體層Μ 1、Μ 1 1之上層分別形成有以熱 硬化性樹脂組合物6構成之第一導孔層（表面積層；絕緣 層）VI、VII。又，於其表面藉由鍍銅分別形成有構成已 圖案化之金屬配線7b的第一導體層M2、Μ12。尚且， 芯導體層Μ1、Μ 11與第一導體層μ 2、Μ 1 2係分別藉由 導孔34而形成層間連接。同樣，於第一導體層m2、Μ1 2 之上層分別形成有使用了熱硬化性樹脂組合物6之第二 導孔層（表面積層；絕緣層）V 2、V 1 2。 於第二導孔層V2、V12上分別形成有具有金屬端子 焊墊10、17之第二導體層M3、Μ13。這些第一導體層 201221004 M2、M12與第二導體層M3、M13係分別藉由導孔34而 形成層間連接。導孔3 4係具有：導通孔3 4h、設於其内周 面之導孔導體34s、在底面側以與導孔導體3乜連通之方 式而設的導孔焊墊3 4p、及在導孔焊墊3 4p之相反側從 導孔導體34h的開口周緣朝外側突出之導孔焊盤341。 如上述，於板狀芯基板2之第一主表面MP 1上依序 積層有芯導體層Ml、第一導孔層 VI、第一導體層 及第二導孔層V2，藉以形成第一配線積層部l 1。另外， 於板狀思基板2之第二主表面MP2上依序積層有芯導體 層Mil、第一導孔層VII、第一導體層M12及第二導孔 層V12，藉以形成第二配線積層部L2。另外，於第_主 表面CP1上形成有複數個金屬端子焊墊1〇，於第二主表 面CP2上形成有複數個金屬端子焊墊17。 又，金屬端子焊墊1 0係用以經後面形成之焊料凸塊 而將未圖示的IC晶片進行覆晶連接的焊塾（ρ c焊墊），其 構成IC晶片搭載部。如第1圖所示，金屬端子焊塾1 〇 係形成於配線基板1之大致中央部而呈矩形排列。 另外’金屬端子焊墊1 7係作為用以藉由針柵陣列 (PGA)或球柵陣列（BGA)將配線基板1連接於母基板或插 座等上的背面焊盤（PGA焊墊、BGA焊墊）而被利用者， 其形成於配線基板1之除大致中心部以外的外周部上， 以包圍該大致中央部之方式呈矩形排列。 又，於第一主表面CP1上形成有具開口部8a之阻焊 劑層8 ’金屬端子焊墊1 〇係經開口部8a而從阻焊劑層8 露出。另外’於第二主表面CP2上亦形成有具開口部i8a 金屬端子焊塾 出。 201221004 之阻焊劑層j 8 阻焊劑層1 8露 另外，於pq ^ 、開口部8a内以與金屬端 接之方式形虑古 有焊料凸塊11，焊料凸 Sn-Pb、Sn-A 十凸塊 g Sn-Ag-CU等的焊料所構 部18a内以斑全 丨稱成 、主屬鈿子焊墊17電性連接 圖示之焊球或針腳等。 钱之 少 攸第1至第4圖可知，本實施形 1係呈矩形之大致板狀，其大小可為例^ 3 5mmx 約 1 mm。 (配線基板的製造方法） 其次，針對本發明之配線基板的製； 明第5及第6圖為在本實施形態中使用 的概略構成之示意圖，第7及第8圖為用 形中之製造方法之製程圖。 第5圖為顯示本實施形態中之平板狀 成之概略構成圖。第5圖所示之平板狀治』 心部形成有凹部21 ’且以界定凹部21之 22。凹部21之大小，如後續之說明，係作 線基板1之焊料凸塊U所界定的1C晶 小，且其深度係作成使焊料凸塊丨丨上部不 21之底面21A的深度。 另外，如以下之說明，因外框22係fl 之平坦化操作時的按壓面，所以，需要使 配線基板1之阻焊劑層的表面粗度對應而 口部1 8 a而從 L墊1 0電性連 11係由例如 。又，於開口 方式形成有未 悲之配線基板 1約 3 5 m m X約 查方法進行說 之平板狀治具 於說明本實施 治具的基本構 ^ 20係於其中 方式设置外框 成能圈入藉配 片搭載部的大 會接觸於凹部 F為配線基板1 其表面粗度與 被粗化。 -11- 201221004 弟6圖為相當於第5圖所示之平板狀治具的變化例 之概略構成圖。第6圖所示之平板狀治具3 〇係於其中心 部形成有凹部31，且在其四角設有用以界定凹部31之 柱狀部3 2。凹部31之大小’如後續之說明，係作成能 圈入猎配線基板1之焊料凸塊11所界定的ic晶片於載 部的大小’且其深度即柱狀部32之高度係作成使焊料凸 塊11之上部不會接觸於凹部21之底面21a的高度。 另外’如以下之說明’因柱狀部32係作為配線基板 1之平坦化操作時的按壓面’所以’需要使其表面粗度 與配線基板1之阻焊劑層的表面粗度對應而被粗化。 又’平板狀治具20及30分別除了鋁、不錄鋼等之 金屬材料外，還可由玻璃或陶瓷材料構成。 再者，針對使用第5圖所示之平板狀治具時的配線 基板的製造方法、即減小配線基板之翹曲的方法進行說 明。 首先，如第7圖所示，準備設有形成沿配線基板之 外形的凹形之設置部41之支撐台40，並將如第1至第4 圖所示之配線基板1設置於此支撐台4〇的設置部4 i 上。配線基板1係以使焊料凸塊丨丨所界定的Ic晶片搭 載部位於上面、且阻焊劑層1 8位於下面的方式所配置。 又’設置部4 1可藉由例如淺槽所形成。 又，支撐台40除了鋁、不鏽鋼等之金屬材料外，還 可由破璃或陶瓷材料構成。 接著，如第8圖所示，在將配線基板1配置於支樓 台40之設置部41上之後，將配線基板丨加熱至規定溫 201221004 度、例如8G°C〜28Gt：、即阻焊劑層8之玻璃轉移點以 上的溫度，並藉由第5圖所示之平板狀治具2〇對配線基 板1進行按壓。 ' 1 又’阻焊劑層8係可於環氧樹脂、聚醯亞胺樹脂、 苯酚樹脂、雙馬來醯亞胺三啩樹脂、氰酸鹽樹脂、聚醯 胺樹脂等之樹脂組合物中含右翁外z办 T 3有虱化矽、氧化鋁等的益機 填充.物而構成。In addition, the 1C wafer mounting portion of the wiring board is generally located at the center portion thereof, and a large external force is applied to the entire surface of the wiring board in the entire fixture as in the prior art. The solder bumps electrically connected to the wafer and the wiring substrate of the IC 201221004 are crushed, and these electrical connections cannot be performed satisfactorily. According to another aspect of the invention, the flat-shaped jig in which the concave portion is formed is used, and the concave portion of the flat jig is placed on the ic wafer mounting portion of the wiring substrate, and the ic wafer mounting portion is not in contact with the flat jig. After the configuration, press it. Therefore, when pressing, the 1C wafer mounting portion of the wiring board is not substantially pressed. Therefore, the solder bumps for electrically connecting the IC wafer and the wiring substrate are not crushed. As a result, these electrical connections I can be performed well. In the case of the present invention, in the case where the surface of the solder resist layer is divided into a contact surface which is in contact with the pressing surface of the jig and a non-contact surface which is not in contact with the jig, After the rule of the jig is pressed, the difference between the arithmetic mean 矣 surface roughness Ra of the contact surface and the arithmetic flat and the surface roughness Ra of the non-contact surface becomes the average surface of the contact surface and the ten-point average surface of the contact surface. It is preferable to roughen the pressing surface in the manner of the rough Rz spot non-technical ', the ten-point average surface roughness Rz of the non-contact surface, and the coarse surface of the gemstone 0.3 μm. In this way, the difference in the surface roughness of the contact surface is such that the difference in the surface roughness of the non-contact surface is as small as the above-mentioned value; @I & flying to the pressing surface is roughened, so the suppression is The jig is pressed against two more effective...the generation of contact marks on the ice substrate. Further, in an example of the present invention, before the pressing process, the arithmetic mean surface roughness of the 层 layer of the slab-like layer is: 〇〇 center. "The arithmetic average surface of the surface of the side of the surface is 10 points flat surface + _ 33·00 times or less '10 points flat with respect to the pressing surface of the solder resist β (7) 8 is located at the outer side of the concave portion 10 dry surface roughness Rz ".〇〇 more than 14〇〇201221004 times less suitable. By setting the surface roughness of the pressing surface of the flat jig to a value larger than the surface of the solder resist layer as described above, the warpage of the wiring substrate can be reduced when the jig is pressed against the wiring substrate, and The generation of contact marks is more effectively suppressed. Further, in an example of the present invention, it is preferable to perform a temperature at which the wiring board is pressed by the flat jig at a temperature equal to or higher than the glass transition temperature of the solder resist layer. Thereby, the warpage of the wiring board caused by the pressing can be more effectively suppressed. Further, even in the case where the pressing is performed at such a temperature, it is possible to suppress the contact marks on the wiring substrate caused by the above-described effects, for example, by the method of the present invention. [Effects of the Invention] As described above, according to the present invention, it is possible to provide a wiring board which is formed by providing a conductor layer having at least one conductor layer and a resin insulating layer and having a solder resist layer formed on the surface as a final product. The formation of contact marks on the surface thereof can reduce the warpage of the wiring substrate, and flattening can be achieved. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings (a wiring board). The configuration of a wiring board used in the method of the present invention will be described. The wiring board shown in the following is merely an example, and is not particularly limited as long as it is a resin wiring board which is formed by forming at least the layer-layer conductor layer and the resin insulating layer and having the outermost surface shape: a solder resist layer. 1 and 2 are plan views of the wiring board of the present embodiment, and FIG. 1 shows a state in which the wiring board is viewed from the upper side, and FIG. 2 is a view showing the green clay from the lower side. The state of the board. In addition, the third figure is to cut the first and the 沿 along the I-Ι line? _ 放大 笫 图 图 图 图 图 图 图 图 图 图 图 图 该 该 该 该 该 该 该 该 该 图 图 图 图 图 图 图 图 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该Zoom in on the schematic. The wiring board 1 shown in Fig. 4 is a board composed of a heat resistant resin sheet (for example, a bismaleimide triterpenoid resin sheet), a fiber reinforced resin sheet (a) such as a glass fiber reinforced epoxy resin, or the like. The core conductor layers M1 and M1 (which are also simply referred to as conductor layers) constituting the metal wiring 7a formed in a predetermined pattern are formed on both surfaces of the core substrate 2 by the copper. These core conductor layers 1VH and M11 are formed as a surface conductor pattern covering most of the surface of the plate-like core substrate 2, and are used as a power source layer or a ground layer. Further, a through hole 1 2 through which a boring head or the like is formed is formed on the plate-shaped core substrate 2, and a via-hole conductor 3 through which the core conductor layer M and the Μ1 1 are electrically connected to each other is formed on the inner wall surface of the through hole. Hey. Further, the through hole 1 2 is filled with a resin-filled hole material 31 such as an epoxy resin. Further, a first via layer (surface layer; insulating layer) VI, VII composed of a thermosetting resin composition 6 is formed on each of the core conductor layers Μ 1 and Μ 1 1 . Further, first conductor layers M2 and Μ12 constituting the patterned metal wiring 7b are formed on the surface thereof by copper plating. Further, the core conductor layers Μ1, Μ11 and the first conductor layers μ2, Μ1 2 are respectively connected by the via holes 34 to form an interlayer connection. Similarly, a second via layer (surface area layer; insulating layer) V 2 and V 1 2 using the thermosetting resin composition 6 is formed on each of the first conductor layers m2 and Μ1 2 . Second conductor layers M3 and Μ13 having metal terminal pads 10, 17 are formed on the second via layers V2, V12, respectively. The first conductor layers 201221004 M2, M12 and the second conductor layers M3, M13 are respectively formed by interlayer vias via via holes 34. The via hole 34 has a via hole 34h, a via hole conductor 34s provided on the inner peripheral surface thereof, and a via pad 3 4p provided to communicate with the via hole conductor 3 on the bottom surface side, and On the opposite side of the hole pad 3 4p, the via hole 341 protrudes outward from the opening periphery of the via hole conductor 34h. As described above, the core conductor layer M1, the first via layer VI, the first conductor layer, and the second via layer V2 are sequentially laminated on the first main surface MP1 of the plate core substrate 2, thereby forming the first wiring. The layered portion l1. In addition, a core conductor layer Mil, a first via layer VII, a first conductor layer M12, and a second via layer V12 are sequentially stacked on the second main surface MP2 of the board substrate 2 to form a second wiring layer. Part L2. Further, a plurality of metal terminal pads 1A are formed on the first main surface CP1, and a plurality of metal terminal pads 17 are formed on the second main surface CP2. Further, the metal terminal pad 10 is a solder raft (p c pad) for flip chip bonding of an IC wafer (not shown) via a solder bump formed later, and constitutes an IC wafer mounting portion. As shown in Fig. 1, the metal terminal pads 1 are formed in a rectangular shape in the substantially central portion of the wiring board 1. Further, the 'metal terminal pad 17' is used as a back pad (PGA pad, BGA solder) for connecting the wiring substrate 1 to a mother substrate or a socket by a pin grid array (PGA) or a ball grid array (BGA). The user who is used as the pad is formed on the outer peripheral portion of the wiring board 1 except for the substantially central portion, and is arranged in a rectangular shape so as to surround the substantially central portion. Further, the solder resist layer 8' having the opening portion 8a is formed on the first main surface CP1. The metal terminal pad 1 is exposed from the solder resist layer 8 through the opening portion 8a. Further, a metal terminal soldering opening having an opening portion i8a is formed on the second main surface CP2. 201221004 solder resist layer j 8 solder resist layer 18 is additionally exposed, in the pq ^, the opening portion 8a is in contact with the metal to consider the ancient solder bump 11, solder bump Sn-Pb, Sn-A ten convex In the solder structure portion 18a of the block g Sn-Ag-CU or the like, the spot is nicked, and the main die pad 17 is electrically connected to the solder ball or the stitch of the figure. It can be seen from the first to fourth figures that the present embodiment 1 has a substantially rectangular plate shape, and its size can be, for example, 3 5 mmx and about 1 mm. (Manufacturing Method of Wiring Substrate) Next, the wiring board of the present invention is manufactured. Figs. 5 and 6 are schematic views showing a schematic configuration used in the present embodiment, and Figs. 7 and 8 are manufacturing in the form. Process map of the method. Fig. 5 is a view showing a schematic configuration of a flat plate in the present embodiment. The flat portion shown in Fig. 5 is formed with a recess 21' and defines a recess 21 of 22. The size of the recess 21, as will be described later, is 1C crystal defined by the solder bump U of the wire substrate 1, and its depth is formed so that the solder bump is not deeper than the bottom surface 21A of the upper portion. In addition, as described below, since the outer frame 22 is a pressing surface during the flattening operation of the fl, it is necessary to make the surface roughness of the solder resist layer of the wiring substrate 1 corresponding to the mouth portion 18 a from the L pad 10 The electrical connection 11 is for example. Moreover, the wiring board 1 is formed in an opening manner by about 35 mm. X is a flat-shaped jig. The basic structure of the present embodiment is shown in the figure. The assembly of the wafer mounting portion contacts the concave portion F to make the surface of the wiring substrate 1 rough and rough. -11-201221004 Figure 6 is a schematic configuration diagram corresponding to a variation of the flat jig shown in Fig. 5. The flat jig 3 shown in Fig. 6 is formed with a concave portion 31 at its center portion, and a columnar portion 32 for defining the concave portion 31 at its four corners. The size of the recessed portion 31 is formed as a size of the carrier portion of the ic chip defined by the solder bumps 11 that can be looped into the wiring board 1 and the depth of the columnar portion 32 is made to make the solder bump. The upper portion of the block 11 does not contact the height of the bottom surface 21a of the recess 21. In the following description, the columnar portion 32 serves as a pressing surface for the flattening operation of the wiring substrate 1. Therefore, it is necessary to make the surface roughness corresponding to the surface roughness of the solder resist layer of the wiring substrate 1 to be coarse. Chemical. Further, the flat-shaped jigs 20 and 30 may be made of glass or ceramic material in addition to metal materials such as aluminum or non-recorded steel. Further, a method of manufacturing a wiring board when the flat jig shown in Fig. 5 is used, that is, a method of reducing warpage of the wiring board will be described. First, as shown in FIG. 7, a support table 40 in which a concave portion 41 is formed along the outer shape of the wiring substrate is prepared, and the wiring substrate 1 as shown in the first to fourth figures is placed on the support table. 4〇 on the setting part 4 i. The wiring board 1 is disposed such that the Ic wafer mounting portion defined by the solder bumps is positioned on the upper surface and the solder resist layer 18 is positioned below. Further, the setting portion 4 1 can be formed by, for example, a shallow groove. Further, the support table 40 may be made of a glass material or a ceramic material in addition to a metal material such as aluminum or stainless steel. Next, as shown in FIG. 8, after the wiring board 1 is placed on the installation portion 41 of the branch building 40, the wiring board 丨 is heated to a predetermined temperature of 201221004 degrees, for example, 8 G ° C to 28 Gt: that is, the solder resist layer 8 The temperature above the glass transition point is pressed against the wiring board 1 by the flat jig 2 shown in FIG. The '1' solder resist layer 8 can be contained in a resin composition such as an epoxy resin, a polyimide resin, a phenol resin, a bismaleimide triterpene resin, a cyanate resin, or a polyamide resin. The right to the outside of the office, the T 3 is composed of a sputum, alum, and the like.
平板狀治具20之凹部21I u。丨21的大小，如上述，係可圈 入配線基板1之1C晶片搭載邱的士 , ^ A怜戰0卩的大小，且其深度亦為使 桿料凸塊11之上部不舍接 會接觸於底面21A的深度，所以， 在藉由平板狀治具20按壓配螬A+ 炊&配線基板丨時，將凹部2丨之The recess 21I u of the flat jig 20 . As described above, the size of the crucible 21 is such that the 1C wafer that can be looped into the wiring substrate 1 is loaded with a Qiu taxi, and the depth is also such that the upper portion of the rod bump 11 is not in contact with each other. Since the depth of the bottom surface 21A is the same, when the patch A 2 炊 & wiring board 按压 is pressed by the flat jig 20, the recess 2 is folded.
開口側的第-面20A作為下側，並將相對向之第二面2〇B 作為上側’而以該IC晶片搭載部位於凹部Μ内之方式 進行。 另外，將平板狀治具20之位於nn加 ;凹邛21外側的外框 22、即按壓面的表面粗度^ ^ ^ ^ ^ ^ ^ ^ ^ /L 坪Μ增8的表面粗度對應 而進订粗化’所以，在藉由平板 a ,p+ a 卞孜狀/σ具20按壓配線基板 1時，不會因外框22、即 r ^ ^囟之按壓而於阻焊劑層8 產生接觸痕跡。藉此，平板狀 λ. ^ . , τ 狀/〇八2〇之外框22係對配 、-土板1之1C晶片搭載部外側的 不會於配線基板i之…域1八進行按壓，而 可们配绩其j 焊劑層8產生接觸痕跡， 了減小配線基板丨之翹曲而達成平坦化。 另外，因為未按壓到.Ic晶片搭 蔣推许ΤΓ曰W t 戰4 ’所以，不會有 曰日片/、配線基板1之電性 μ :眚沾沣r生連接的焊料凸塊1 1 貝的情況。結果可良好地 适仃些電性連接。 -13- 201221004 於本實施形態中，如上述，在阻焊劑層之玻璃轉移 溫度以上的溫度下，執行以平板狀治具2〇按壓配線基板 1時的溫度’所以，可更有效地抑制因該按壓造成之配 線基板1的翹曲。另外，即使在以此種溫度進行按壓的 情況下，仍可抑制因上述作用效果所引起之對配線基板 1產生的接觸痕跡。 又’以相對於配線基板1之外側區域1 A、即成為平 板狀治具2 0之接觸面的阻焊劑層8表面之算術平均表面 粗度Ra，將平板狀治具20之位於凹部2丨外側的外框 22，即按壓面的算術平均表面粗度Ra設為4 〇〇倍以上 33.00倍以下，相對於阻焊劑層8表面之算術平均表面粗 度’將按壓面的十點平均表面粗度設為2·00倍以上 1 4.0 〇彳。以下較為適宜。在此情況下，可更有效地抑制平 板狀治具20之按壓造成的接觸痕跡的產生。 另外，以將阻焊劑層8表面區分為與平板狀治具2〇 之按壓面（外框22)接觸的接觸面及不與平板狀治且2、〇之 按壓面（外框22)接觸的非接觸面，於藉平板狀治具2〇按 壓配線基板1之後，以接觸面之算術平均表面粗度。 與非接觸面之算術平均表面粗度Ra的差成為q构出以 内，且接觸面之十點平均表面粗度Rz與非接觸面之十點 千=表面粗纟Rz的差成為Q 3叫以内的方式對按壓面 (卜框2 2)進行粗化較為適宜。 :由以接觸面與非接觸面之表面粗度的差成為如上 :/小值的方式設定平板狀治具2〇之表面粗度，可更 痕將平板狀治具2。按麼於配線基板的接觸 -14- 201221004 如上述之平板狀治具20的表面粗度例如可 對平板狀治具2G實施噴砂法等來實現。另外，平板 具之表面粗度可藉由適宜地變更喷砂法中之砂粒的^ 小、處理時間來進行調整。 [實施例] 作為實施例及比較例，在使用按壓面（外框22)之表 面粗度不同的·平板狀治# 2G進行按壓的情況下，將對有 無產生接觸痕跡進行調查的結果出示於表i。配線基板 係使用按壓前之阻焊劑層8表面之算術平均表面粗度^ 為Ο.ΙΟμΓη，十點平均表面粗度Rz為2 42μιη者。 又，有關實施例及比較例中之平板狀治具2〇的位於 凹部21外侧之按壓面(外框22)的算術平均表面粗度Ra 與阻焊制8之算術平均表面粗度Ra之比，平板狀治具 20的位於凹部21外側之按壓面（外框22)的十點平均表 面粗度Rz與阻焊劑層8(SR)表面之十點平均表面粗度Rz 之比等的諸多條件，出示於表2。在表2 果中，將觀察到接觸痕跡者標記為⑽，將未觀察= 痕跡者標記為NG。 另外，表面觀察結果中有無產生接觸痕跡，係以放 大鏡且10倍之倍率來觀察按壓後的阻焊劑層8表面而進 行判斷。 -15- 201221004 [表i] 按壓面之Ra〇am) 按壓面之ΙΙζ(μπι) 表面觀察結果 實施例1 2.4 10.35 無接觸痕跡 實施例2 3.28 9.65 無接觸痕跡 比較例1 0.01 0.01 無接觸痕跡 比較例2 0.39 3.94 有接觸痕跡 比較例3 2.23 36.2 有接觸痕跡 比較例4 1.05 4.73 有接觸痕跡 [表2]The first surface 20A on the opening side is a lower side, and the second surface 2B is opposed to the upper side, and the IC wafer mounting portion is located in the concave portion. In addition, the flat jig 20 is located at nn plus; the outer frame 22 on the outer side of the concavity 21, that is, the surface roughness of the pressing surface is ^^^^^^^^^L, and the surface roughness of the flat plate is increased. When the wiring board 1 is pressed by the flat plate a, p+ a //σ 20, the solder resist layer 8 is not contacted by the outer frame 22, that is, the pressing of r ^ ^ 囟trace. In this way, the outer frame 22 of the flat plate λ. ^ . , τ shape / 〇 〇 〇 系 对 , , , , , , , , , , , , , , , , , , , , , , On the other hand, the j-flux layer 8 can be made to have contact marks, and the warpage of the wiring board can be reduced to achieve flattening. In addition, since the .Ic wafer is not pressed, it is not possible to have the electric film of the wiring board 1 and the wiring of the wiring board 1 : the solder bump 1 1 of the wiring Case. As a result, some electrical connections are well suited. In the present embodiment, as described above, the temperature at which the wiring board 2 is pressed by the flat jig 2 is performed at a temperature equal to or higher than the glass transition temperature of the solder resist layer. Therefore, the cause can be more effectively suppressed. This pressing causes warpage of the wiring substrate 1. Further, even in the case of pressing at such a temperature, the contact marks on the wiring substrate 1 due to the above-described effects can be suppressed. Further, the flat-shaped jig 20 is located in the concave portion 2 with respect to the arithmetic mean surface roughness Ra of the surface of the solder resist layer 8 which is the contact surface of the flat-shaped jig 20 with respect to the outer region 1A of the wiring board 1. The outer outer frame 22, that is, the arithmetic mean surface roughness Ra of the pressing surface is set to be 4 〇〇 or more and 33.00 times or less, and the arithmetic mean surface roughness of the surface of the solder resist layer 8 is set to be ten points of the pressing surface. The degree is set to 2·00 times or more and 1 4.0 〇彳. The following is more appropriate. In this case, the generation of contact marks caused by the pressing of the flat jig 20 can be more effectively suppressed. Further, the surface of the solder resist layer 8 is divided into a contact surface which is in contact with the pressing surface (outer frame 22) of the flat jig 2, and a contact surface which is not in contact with the flat plate and the pressing surface (outer frame 22). The non-contact surface is an arithmetic mean surface roughness of the contact surface after the wiring board 1 is pressed by the flat jig 2 . The difference between the arithmetic mean surface roughness Ra of the non-contact surface is within q, and the difference between the ten-point average surface roughness Rz of the contact surface and the ten-thousand-zero surface roughness Rz of the non-contact surface becomes Q 3 It is preferable to roughen the pressing surface (frame 2 2). The flatness of the flat jig 2 can be further improved by setting the surface roughness of the flat jig 2 so that the difference in surface roughness between the contact surface and the non-contact surface is as above: /. Contact with the wiring board - 14 - 201221004 The surface roughness of the flat jig 20 as described above can be realized, for example, by performing a sand blast method or the like on the flat jig 2G. Further, the surface roughness of the flat plate can be adjusted by appropriately changing the amount of sand in the blasting method and the processing time. [Examples] As an example and a comparative example, when the pressing surface (outer frame 22) was pressed with a flat surface-like thickness 2 2G, the result of investigating the presence or absence of a contact trace was shown. Table i. Wiring substrate The arithmetic mean surface roughness of the surface of the solder resist layer 8 before pressing is Ο.ΙΟμΓη, and the ten-point average surface roughness Rz is 2 42 μm. Further, the ratio of the arithmetic mean surface roughness Ra of the pressing surface (outer frame 22) on the outer side of the concave portion 21 of the flat jig 2 of the embodiment and the comparative example to the arithmetic mean surface roughness Ra of the solder resist 8 The conditions of the ratio of the ten-point average surface roughness Rz of the pressing surface (outer frame 22) of the flat jig 20 located outside the concave portion 21 to the ten-point average surface roughness Rz of the surface of the solder resist layer 8 (SR) , shown in Table 2. In Table 2, the person who observed the contact mark was marked as (10), and the person who did not observe the mark was marked as NG. Further, whether or not a contact mark was formed in the surface observation result was judged by observing the surface of the solder resist layer 8 after pressing with an amplification mirror at a magnification of 10 times. -15- 201221004 [Table i] Ra按压am of the pressing surface) 按压 (μπι) of the pressing surface Surface observation Example 1 2.4 10.35 No contact trace Example 2 3.28 9.65 No contact trace comparison Example 1 0.01 0.01 No contact trace comparison Example 2 0.39 3.94 Contact traces Comparative Example 3 2.23 36.2 Contact traces Comparative Example 4 1.05 4.73 Contact traces [Table 2]
試樣 實施例1 實施例2 比較例1 比較例2 比較例3 比較例4 治具之按壓面的Ra( // m) 2.4 3.28 0.01 0.39 2.23 1.05 按壓前之SR表面的Ra(/zm) 0.1 0.1 0.1 0.1 0.1 0.1 按壓後之SR表面的Ra(；am) 0.13 0.12 0.06 0.2 0.5 0.17 治具之按壓面的Ra/按壓面之SR表面的Ra 24 32.8 0.1 3.9 22.3 10.5 治具之按壓面的R2(//ΠΊ) 10.35 9.65 0.01 3.94 36.2 4.73 按壓前之SR表面的Rz(#m) 2.42 2.42 2.42 2.42 2.42 2.42 按壓後之SR表面的Rz(//m) 2,7 2.61 1.45 3.94 7.82 3.03 治具之按壓面的Rz/按壓面之SR表面的Rz 4.3 3.98 0.004 1.628 14.96 1.95 表面觀察結果 OK OK NG NG NG NG 在採用處於本發明之範圍内的，相對於按壓前之阻 焊劑層表面之算術平均表面粗度Ra，按壓面的算術平均 表面粗度Ra為4.00倍以上33.00倍以下，相對於按壓 前之阻焊劑層8表面之十點平均表面粗度Rz，按壓面的 十點平均表面粗度Rz為2.00倍以上14.00倍以下而構 成的平板狀治具進行按壓的配線基板上，與平板狀治具 接觸之阻焊劑層8的接觸面及不接觸之非接觸面之間的 表面粗度之差值小，尤其是在藉平板狀治具20按壓配線 基板1之後，接觸面之算術平均表面粗度Ra與非接觸面 -16- 201221004 之算術平均砉；，上 表面粗度Ra的差古、& ΛΛ·2 之十點平均表面 成為〇.03μηι以内，接觸面 度RZ的差成為0 , ”非接觸面之十點平均表面粗 另 · _以内’而未觀察到接觸痕跡。 在採用處於本發明之範圍外τ 具之情況下，阻煜制s 發月之㈣外的平板狀治 ,Ή . ^ ^ 接觸面與非接觸面之間& a % 粗度之差變大，而有觀察到接觸痕跡。 的表面 配線針對使用第5圖所示之平板狀構件來製造 配線基板1的愔 表le_ 平板… 說明，但在使用第6圖所示之 平扳狀構件3 〇的情，丁 〈 摔：兄伤於货 月况下，亦同樣可製造配線基板丨。此 隋/兄係於第8圖所千·夕制 斤不之製知中，將平板狀構件30的第— 面3 0 A作為下側，並 1將與弟—面30A相對向之第二面3〇r 作為上側，取代平切灿拔π 代千板狀構件2〇之外框22，藉由柱狀 32對配線基板1之外側區域1 Α進行按壓。 ° 以上，以具體例為例詳細地說明了本發明，但本發 明不限定於上述内容，只要是在未超出本發明之實質範 圍的情況下’即可作各種之變形及變更。 已 例如，於上述具體例中，針對使用形成有單一凹部 2 1及3 1之平；I：反狀治具2 〇及3 〇來製造單一之配線基板1 的方法’即減小翹曲之方法進行了說明，但也可使用連 結有複數個平板狀治具20及30而具有複數個凹部之治 具’一次性地製造複數片配線基板i (翹曲之減小）。 另外，於上述具體例中，針對具有芯基板2之配線 基板1進行了說明，但本發明之製造方法當然亦可應用 於不具有芯基板2之配線基板。 -17- 201221004 【圖式簡單說明】 第1 圖 為貫施形態之配線基 板的 術視 圖 〇 第2 圖 同樣為實施形態之配 線基: 板的 俯 視 圖 0 第3 圖 為沿I-Ι線切斷第1及 第2 圖所 示 之 配 線 時的 截面 之 一部分的放大示意圖 〇 第4 圖 為沿II-II線切斷第1 及第 2圖 所 示 之 配 板時 的截 面 之一部分的放大示意 圖。 第5 圖 為在實施形態中使用 之平 板狀 治 具 的 概 成之 示意 圖 0 第6 圖 同樣為在實施形態中 使用 之平 板 狀 治 具 略構 成之 示 意圖。 第7 圖 為用於說明實施形態 中之 配線 基 板 的 製 法之 製程 圖 〇 第8 圖 同樣為用於說明實施 形態 中之 製 造 方 法 程圖 〇 [主 •要元件符號說明】 1 配線基板 8、 18 阻焊劑 11 焊料凸塊 20 '30 平板狀構件 21 、31 凹部 22 外框 32 柱狀部 40 支撐台 41 設置部 基板 線基 略構 的概 造方 之製 c- -18·Sample Example 1 Example 2 Comparative Example 1 Comparative Example 2 Comparative Example 3 Comparative Example 4 Ra ( // m) of the pressing surface of the fixture 2.4 3.28 0.01 0.39 2.23 1.05 Ra (/zm) of the SR surface before pressing 0.1 0.1 0.1 0.1 0.1 0.1 Ra (;am) of the SR surface after pressing 0.13 0.12 0.06 0.2 0.5 0.17 Ra of the pressing surface of the fixture/Ra surface of the SR surface of the pressing surface 3 24 0.1 3.9 22.3 10.5 R2 of the pressing surface of the fixture (//ΠΊ) 10.35 9.65 0.01 3.94 36.2 4.73 Rz(#m) of the SR surface before pressing 2.42 2.42 2.42 2.42 2.42 2.42 Rz(//m) of the SR surface after pressing 2,7 2.61 1.45 3.94 7.82 3.03 Fixture Rz of the pressing surface Rz/R surface of the SR surface of the pressing surface Rz 4.3 3.98 0.004 1.628 14.96 1.95 Surface observation OK OK NG NG NG NG In the range of the present invention, the arithmetic mean of the surface of the solder resist layer before pressing The surface roughness Ra, the arithmetic mean surface roughness Ra of the pressing surface is 4.00 times or more and 33.00 times or less, and the ten-point average surface roughness Rz of the surface of the solder resist layer 8 before pressing, the ten-point average surface roughness of the pressing surface A flat jig formed by setting Rz to 2.00 times or more and 14.00 times or less On the pressed wiring substrate, the difference in surface roughness between the contact surface of the solder resist layer 8 in contact with the flat jig and the non-contact non-contact surface is small, in particular, pressing the wiring substrate by the flat jig 20 After 1 , the arithmetic mean surface roughness Ra of the contact surface and the arithmetic mean 非 of the non-contact surface-16-201221004; the difference between the upper surface roughness Ra and the average surface of the amp·2 of ΛΛ·2 becomes 〇.03μηι The difference of the contact surface degree RZ becomes 0, "the ten-point average surface of the non-contact surface is thicker than the inside of the _" and no contact marks are observed. In the case of using the τ outside the range of the present invention, the stagnation system s The flat shape of the moon (4), Ή . ^ ^ The difference between the contact surface and the non-contact surface is larger, and the contact mark is observed. The surface wiring is shown in Figure 5. The flat member is used to manufacture the le table of the wiring board 1. The description is made, but in the case of using the flat member 3 shown in Fig. 6, it is also possible to use the same. Manufacture of wiring board 丨. This 隋 / brother is in the figure 8 In the known method, the first surface 30A of the flat member 30 is taken as the lower side, and the second surface 3〇r opposite to the younger face 30A is used as the upper side instead of the flat cut π 代代板The outer frame 2 of the member 2 is pressed by the columnar shape 32 to the outer side region 1 of the wiring substrate 1. The present invention has been described in detail by way of specific examples. However, the present invention is not limited thereto, and various modifications and changes can be made without departing from the spirit and scope of the invention. For example, in the above specific example, the method of manufacturing a single wiring substrate 1 by using a flat formed with a single recess 2 1 and 31; I: a reverse jig 2 〇 and 3 ' is reduced in warpage. Although the method has been described, a plurality of wiring boards i (reduction in warpage) can be manufactured at one time by using a jig having a plurality of flat jigs 20 and 30 and having a plurality of concave portions. Further, in the above specific example, the wiring board 1 having the core substrate 2 has been described. However, the manufacturing method of the present invention can of course be applied to a wiring board not having the core substrate 2. -17- 201221004 [Simplified description of the drawings] Fig. 1 is a view showing the wiring board of the configuration. Fig. 2 is also the wiring base of the embodiment: Top view of the board 0 Fig. 3 is cut along the I-Ι line Fig. 4 is an enlarged schematic view showing a part of a cross section when the wiring plates shown in Figs. 1 and 2 are cut along the line II-II. Fig. 5 is a schematic view showing the outline of a flat plate-shaped jig used in the embodiment. Fig. 6 is also a schematic view showing a schematic configuration of a flat plate-shaped jig used in the embodiment. Fig. 7 is a process diagram for explaining a method of manufacturing a wiring board in the embodiment. Fig. 8 is a view for explaining a manufacturing method in the embodiment. [Main and essential element symbol description] 1 Wiring board 8, 18 Solder resist 11 Solder bump 20 '30 Flat member 21, 31 Concave portion 22 Outer frame 32 Column portion 40 Support table 41 Setting part substrate base structure Simple structure c--18