201220379 - 六、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體裝置之晶片載體，特別係有關 於一種多對位標記之基板條構造及其封裝時的切割方 法。 【先前技術】 現今市場上的半導體裝置均是採用成批方式來製 作’利用格橋交錯之切割道預先於如印刷電路板之基板 _ 條之表面定義出複數個呈矩陣排列之基板單元，再經過 黏晶（die bond)、打線（wire bond)以及封裝（encapsulati〇n) 等製程。在封裝完成之後，大多需要先進行切割作業， 以將該些基板單元由該基板條分離，進而形成為個別的 半導體封裝構造，或者將多個半導體封裝構造堆疊並整 合成一層疊封裝（package on package，POP)，以供應予市 場之各種不同需求。雖然基板條之表面定義有若干個切 φ 割道’但通常在切割製程中仍必須依據位於對位標記作 為定位點基準’以對基板條進行切割動作。而對位標記 一般是位於基板條之周邊，或者是位於基板單元四個角 洛在切割道交會處。 如第1圖所示，一種習知銲罩層界定墊（SMD pad)之 基板條構造100’特別是應用於層疊封裝（POP)之基板 條，主要包含一基板條本體110與一銲罩層，該基板條 本體110係具有複數個呈矩陣排列之基板單元113，並 且在該基板條本體110之植球面上形成有複數個外接墊 [S ] 3 201220379 120與複數個電鍍線130。該些外接墊120係位於該些基 板單元113内，該些電鍍線130係交錯排列於該些基板 單元113之間與周邊。該銲罩層之複數個連接孔141係 局部顯露出該些外接墊120’也就是說該些連接孔ι41 係小於該些外接墊1 20而包覆該些外接墊丨2〇之周邊， 使得該些外接墊120為銲罩界定（solder mask defined， SMD)型態。此外，該銲罩層之複數個開孔1 42係顯露位 於該些基板單元113之間之該些電鍍線13〇。其中，該 些電鍍線130係呈十字交又於該些基板單元113之角 隅，在該些開孔142之顯露下，進而形成為複數個非銲 罩界定對位標記132在切割道之交會處，以作為切割時 的基準。如此，不需要將對位標記設計於該些基板單元 113内，又最接近該些基板單元113,符合高密度封裝之 精準對位切割道之需求。 如第2 A圖所示，以往該基板條構造i 〇〇在理想狀態 下，該銲罩層與該基板條本體11〇應為無偏移之情況， 原始基板條設計中該銲罩層之該些連接孔】4丨.應對準位 於該些外接墊120之中央部位，並且該些間孔142應完 整顯露該些非銲罩界定對位標記132。在對該基板條本 體no進行切割動作以分離該些基板單元113之後該 些外接墊120顯露於該些連接孔141之部位與該些基板 單το 11 3之邊緣可保持預定距離使得例如銲球等外接 端子ax置之後亦不會太靠近已切割封裝構造之邊緣。然 而’如第2B ®所示’事實上因為機台精度與銲罩層製m 4 201220379 造之製程公差’該銲罩層與該基板條本體110並不能如 上述理想狀態般呈現無偏移之情況，該銲罩層之偏移的 標準公差為+/- 50微米（#m)。當該銲罩層發生偏移時， 表示該銲罩層所有之該些連接孔141及該些開孔142皆 會產生偏移，即該些連接孔141之位置改變而無法對準 於該些外接墊120之中央部位，甚至偏移至該些外接墊 120之周邊’進而導致外接端子的偏移。然而，在切割 時仍以該些非銲罩界定對位標記132之中心作為基準， 將使得該些外接墊i 20顯露於該些連接孔1 4丨之部位與 該些基板單元113之邊緣的距離改變。因此，在設置外 接端子於該些外接墊120顯露於該些連接孔141之部位 後，會使得外接端子與切割後封裝構造之邊緣的距離過 於靠近，導致外接端子的分佈位置與原始設計的腳位位 置不同，進而造成後續表面接合時各種可能的問題。 【發明内容】 有鑒於此，本發明之主要目的係在於提供一種多對位 標記之基板條構造及其封裝時的切割方法，可提升封裝 構造於切割完成的精準度，以避免封裝後外接端子太靠 近已切割封裝構造之邊緣。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。本發明揭示一種多對位標記之基板條構 造’包含―基板條本體、複數個外接塾、複數個電鍵線 以及一輝罩層。該基板條本體係具有—模封面與一植球 面’該基板條本體内為複數個—體構成並呈矩陣排列之⑸ 5 201220379 基板單元與複數個位於該些基板單元之間與周邊的切割 道’其中該些切割道係包含至少一 X軸切割道與至少一 γ軸切割道。該些外接墊係設置於該植球面上並位於該 些基板單元内《該些電鍍線係設置於該植球面上且位於 該些切割道内，並於該X軸切割道與該γ軸切割道之交 會處形成有一金屬墊，以及於該基板條本體之周邊形成 有一第一非銲罩界定對位標記與一第二非銲罩界定對位 籲 標記’分別位於該X軸切割道與該γ軸切割道内《該銲 罩層係形成於該植球面上，該銲罩層係具有複數個顯露 該些外接墊之連接孔、一局部顯露該金屬墊之對位孔以 及複數個顯露該第一非銲罩界定對位標記與該第二非銲 罩界定對位標記之開孔，其中該些連接孔係小於該些外 接墊，以使該些外接墊為銲罩界定型態，並且該金屬墊 顯露於該對位孔之部位係形成為一銲罩界定對位標記， 其中該第一非銲罩界定對位標記與該第二非銲罩界定對 • 位標記係鄰近於該金屬墊，作為用以計算該銲罩界定對 位標記之位偏差值之基準點。本發明另揭示適用於上述 多對位標記之基板條構造封裝時的切割方法。 本發日㈣目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述之基板條構造中，該對位孔與該些非輝罩界定 對位標記係可為十字形。 1 在前述之基板條構造中，該銲罩層係可覆蓋該些電鍍 線在該金屬塾、該第一非銲罩界定對位標記與該第二：m 6 201220379 銲罩界定對位標記之外之部位。 在前述之基板條構造中，該些外接墊係可為周邊排 列0 在前述之基板條構造中，該些開孔係可為圓形，其孔 徑係不小於該銲罩界定對位標記之位偏差值的兩倍。 由以上技術方案可以看出，本發明之多對位標記之基 板條構造及其封裳時的切割方法，具有以下優點與功^ 參一、可藉由電鍍線形成在X軸與γ轴切割道之交會處的 金屬墊以及在X軸與Y軸切割道内之第一非銲罩界 定對位標記與第二非銲罩界定對位標記以及鲜罩層 之對位孔局部顯露出金屬墊之一部位而形成為銲罩 界定對位標記之特定組合關係作為其中之—技術手 段，即使銲罩界定對位標記因銲罩層之對位孔偏移 而改變位置’但第一非鋅罩界定對位標記與第二非 銲罩界定對位標記係不會因銲罩層之開孔偏移而改 _ 冑其原始位置，所以可作為用以計算銲罩界定對位 標記之位偏差的基準點’以利於切割動作之進行。 因此’可提升封裝構造於切割完成的精準度，以避 免封裝後外接端+ +告.A 1 太靠近已切割封裝構造之邊緣。 【實施方式】 以下將配合所附圖+ 4 4 Μ 立 叮W圖不咩細說明本發明之實施例，然應 注意的是，該些圖示均為簡化之示意圖，僅以示意方法 來說明本發明之基本架構或實施方法，故僅顯示與本案 有關之元件與組合關係，圖中所顯示之元件並非以實際m 7 201220379 實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例 與其他相關尺寸比例或已誇張或是簡化處硬，以提供更 清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計’詳細之元件佈局可能更為複雜。 依據本發明之一具體實施例’一種多對位標記之基板 條構造舉例說明於第3圖之上視示意圖、第4圖之局部 放大示意圖、第5圖依基板條本體之長邊平行方向剖切 基板單元之局部截面示意圖以及第6圖沿X軸切割道剖 切之局部截面示意圖。該多對位標記之基板條構造2〇〇 係包含一基板條本體210、複數個外接墊22〇、複數個電 鍍線230與一銲罩層240。 請參閱第3圖所示，並配合參酌第5圖，該基板條本 體210係具有一模封面211與一植球面212，該基板條 本體210内為複數個一體構成並呈矩陣排列之基板單元 與複數個位於該些基板單元213之間與周邊的切割 道214，其中該些切割道214係包含至少一 X軸切割道 214A與至少一 Y轴切割道214B。具體而言，該基板條 本體210之材質係可為雙馬來醯亞胺_三氮雜苯樹脂 (bismaleimide_triazine⑴⑷，簡稱bt樹脂並且該 模封面2U與該植球自212係為兩相背之表面如顯現 於第3圖中之表面係為該植球面212，該模封面2"係 位於該植球面212之背面’故該模封面2ιι無法標示於 第3圖中。更具體地，該模封面2ιι係作為提供予封膠 體形成之表面，而該植球面212係作為用以設置該些 8 201220379 接墊220與該些電鍍線23〇之表面，其中，該些基板單 元211在切割分離之後係可作為半導體封裝構造之晶片 載體。其中，所稱之「X軸切割道」係為平行於該基板 條構造200之較長邊的切割道，而所稱之「γ轴切割道」 則係為平行於該基板條構造2〇〇之較短邊的切割道。 請參閱第4圖所示，並配合參酌第6圖，該些外接墊 220係設置於該植球面212上並位於該些基板單元213 内，其中該些外接墊220係位於每一基板單元213内， 可供例如銲球等外接端子設置，以作為該些基板單元 213對外連接之通道。在本實施例中，該些外接墊22〇 係可為周邊排列，例如：可為單排或雙排排列於每一基 板單元213之周邊。或者，該些外接墊22〇亦可為矩陣 排列’或設置於該些基板單元2 1 3之中央部位或單一侧 邊’以因應各種不同產品之腳位配置型態。 請參閱第4圖所示’並配合參酌第6圖，該些電鍍線 籲 230係a又置於该植球面212上且位於該些切割道214 内’並於該X轴切割道214A與該Y軸切割道21 4B之交 會處形成有一金屬墊23 1，並且於該基板條本體21〇之 周邊形成有一第一非銲罩界定（non-solder mask defined， NSMD)對位標記232與一第二非銲罩界定（n〇n_s〇ider mask defined，NSMD)對位標記233，該第一非銲罩界定 對位標記232係位於該X軸切割道214A内，該第二非 鲜罩界定對位標記233係位於該γ轴切割道2 1 4B内。 詳細而言，該些電鍍線230係為用以電鍍該些外接墊22〇 9 201220379 之金屬線，通常該些電鍍線230之材質係可為銅。在本 實施例中，在該銲罩層240形成於該基板條本體210之 後，可藉由該些電鍍線230形成一電鍍層250披覆於該 些外接墊220、該金屬墊23 1、該第一非銲罩界定對位標 記232以及該第二非銲罩界定對位標記233之顯露頂 面，並且該電鍍層250之材質係可為鎳金或金，以具有 較佳的抗氧化能力。具體而言，該電鍍層250披覆於該 些外接墊220，可增加該些外接墊220與外接端子之結 合力’而該電鍵層250坡覆於該金屬整231與該些對位 標記232、233’能夠使該金屬墊231、該些非銲罩界定 對位標記232、233之顯露部位呈現為光亮表面，具有較 佳的辨識度。其中，該金屬墊231係恰位於該些電鍍線 23 0兩兩相交之處而可形成為十字形。或者，在一變化 例中，該金屬墊231之形狀亦可變更為圓形、正方形、 菱形等等。在一較佳型態中，該第—非銲罩界定對位標 s己232與該第二非銲罩界定對位標記233係可為十字 办’有助於辨識出該第一非辉罩界定對位標記232與該 第一非銲罩界定對位標記2 3 3之中心，但配置於該基板 條本體210之不同位置，可分別用以量測該銲罩界定對 位標記於Y轴與X轴之位偏差值。 請參閱第4圖所示，並配合參酌第6圖，該銲罩層 240係形成於該植球面212上，該銲罩層24〇係具有複 數個顯露該些外接墊220之連接孔241、一局部顯露該 金屬墊231之對位孔242以及複數個顯露該第一非銲罩 10 201220379 界定對位標記232與該第二非銲罩界定對位標記233之 開孔243。在本實施例中’該銲罩層240係可覆蓋該此 電鍍線23 0在該金屬墊23 1、該第一非銲罩界定對位標 記232與該第二非銲罩界定對位標記233之外之其它部 位。通常，該植球面212除了位於該銲罩層24〇之該此 連接孔241、該對位孔242與該些開孔243之部位係呈 現顯露狀態之外’該植球面212之其餘線路部位皆應被 該銲罩層240所覆蓋遮蔽。其中該些連接孔241係小於 _ 該些外接墊220,以使該些外接墊220為銲罩界定（s〇lder mask defined，SMD)型態，並且該金屬墊23丨顯露於該對 位孔242之部位係形成為一銲罩界定（s〇lder mask defined，SMD)對位標記，即覆蓋該金屬墊231之周邊’ 所以該銲罩界定對位標記之中心係由該對位孔242的形 狀尺寸來決定’而該對位孔242之位置偏移方向與偏移 量係與該銲罩層240之該些連接孔241之位置偏移方向 • 與偏移量為同步。在一較佳型態中，該對位孔242係可 為十字形’該金屬墊231顯露於該對位孔242之部位呈 現鍍金十字之型態，更有利於辨識其中心位置。此外， 該些開孔243係可為圓形，其孔徑係不小於該銲罩界定 對位標記之位偏差值的兩倍，如一般銲罩層偏移的標準 公差為+/- 50微米（# m) ’則該些開孔243之孔徑係可設 計為不小於100微米Qm)，以確保在該銲罩層24〇偏移 之後該些開孔243仍可顯露出該第一非銲罩界定對位標 記232與該第二非銲罩界定對位標記如的中心點。特⑸ 201220379 別的是’該第一非銲罩界定對位標記232與該第二非銲 罩界定對位標記233係鄰近於該金屬墊23 1，作為用以 計算該銲罩界定對位標記之位偏差值之基準點，並能界 定該X軸切割道214A與該Y軸切割道214B之原始位 置。其中，所稱之「鄰近」係指該第一非銲罩界定對位 標記232與該金屬墊231之距離以及該第二非銲罩界定 對位標記233與該金屬墊231之距離皆不大於該些基板 單元213同向邊長的二分之一。一般而言，該些非銲罩 界定對位標記232、233至該金屬墊231之距離係約為該 些基板单元213同向邊長的三分之一或四分之一。 綜上可知，本發明可藉由該些電鍍線23〇形成在該χ 轴切割道214Α與該Υ轴切割道214β之交會處的該金屬 墊23 1、在該χ轴切割道214Α與該γ軸切割道214β内 之該第一非銲罩界定對位標記232與該第二非銲罩界定 對位標記233以及該銲罩層240之該對位孔242局部顯 露出該金屬墊23 1之一部位而形成為該銲罩界定對位標 記之特定組合關係作為其中之一技術手段，即使該輝罩 界定對位標記因該銲.罩層240之該對位孔242偏移而改 變位置，但該第一非銲罩界定對位標記232與該第二非 銲罩界定對位標記233並不會因該銲罩層24〇之該些開 孔243偏移而改變其原始位置。所以，可利用該第^ [S] 銲罩界定對位標記232與該第二非銲罩界定對位標記 233計算出該銲罩界定對位標記之位偏差，進而調整切 割中心，以修正設置於該些外接塾22〇之外接端子至封 12 201220379 裝構造之邊緣的距離。因此’可提升封裝構造於切割完 成的精準度’以避免封裝後外接端子太靠近已切割封裝 構造之邊緣。 本發明還揭示上述多對位標記之基板條構造2〇〇封 裝時的切割方法舉例說明於帛7AJL 7Cffi，以彰顯本發 明之功效。 請參閱第7A圖所示，提供如前述之多對位標記之基 籲板條構造200。該多對位標記之基板條構造2〇〇係包含 該基板條本體210、該些外接墊220、該些電鍍線23〇 與該銲罩層240,由於在第7A圖中係顯示該基^條本體 2 1 0之該模封面2 u，所以位於該植球面2〗2之該些外接 墊220、該些電鍍線23〇與該銲罩層24〇無法標示於第 7A圖中’故請配合參酌第3、5與6圖所示。 π參閱第7B圖所示，將該基板條本體21〇之該模封 面211朝向上方，對該基板條構造2〇〇進行封裝動作， • 其係設置複數個晶片30於該些基板單元213上，並且電 性連接該些晶片30至該些基板單元213，例如：可藉由 打線方式形成之銲線或是覆晶結合之凸塊電性連接該些 晶片30與該些基板單元213。之後，再形成一封膠體4〇 於該基板條本體210之該模封面211，該封膠體4〇係毋 須全面覆蓋於該模封面211，但至少須完整覆蓋住所有 之該些基板單元213，以確保在分離成若干個半導體封 裝構造後該封膠體40能確實地包覆該些基板單元213， 進而提供完善的保護作用。在形成該封膠體40之後，可[s] 13 201220379 設置如銲球等外接端子於該些外接墊22g，以作為該些 基板單元213對外連接之焊接端點。 請參閱第7C圖所示，在完成上述步驟之後，在切判 之前’進行-切割道修正之步驟，先固定該基板條構： 2〇〇,並使該銲罩界定對位標記、該第一非銲罩界定對位 標記232以及該第二非鉾罩界定對位標記233朝向切割 機台内之定位偵測設備。抓取該銲罩界定對位標記與上 述具有第一非銲罩界定對位標記232之電鍍線23〇之間 的Y軸位偏差值，並取其兩者之間之一位置作為χ軸切 割道214Α之修正。所稱之r γ軸位偏差值」係指該銲罩 界定對位標記（即該對位孔242)之中心在γ軸方向的偏 移量，可由該銲罩界定對位標記（即該對位孔242)之中心 至在同一 X軸切割道内具有該第一非銲罩界定對位標記 232之該電鍍線230之最短距離計算而得。並可在該銲 罩界定對位標記之中心至具有該第一非銲罩界定對位標 記232之電鍍線230之最短距離之間取一適當位置，例 如：二分之一或三分之一處，以作為該X軸切割道214α 修正後之切割基準。如第7 C圖所示，當該銲罩界定對 位標記（即該對位孔242)之中心係沿著γ軸向上偏移， 則該X轴切割道2 14 Α的切割中心線應沿著γ轴向上修 正二分之一或三分之二的Y軸位偏差值。同時，抓取該 鲜罩界定對位標記與上述具有第二非鲜罩界定對位標記 233之電鍍線230之間的X軸位偏差值，並取其兩者之 間之 位置作為Y軸切割道214B之修正。所稱之「χ [ s] 14 201220379 軸位偏差值」係指該銲罩界定對位標記之中心在χ軸方 向的偏移量，可由該銲罩界定對位標記（即該對位孔242) 之中〜至在同一Υ軸切割道内具有該第二非銲罩界定對 位標記233之該電鍍線230之最短距離計算而得。並可 在該銲罩界定對位標記之中心至具有該第二非銲罩界定 對位標記233之電鍍線230之最短距離之間取一適當位 置，例如：二分之一或三分之一處，以作為γ軸切割道 φ 214Β修正後之切割基準。如第7C圖所示，當該銲罩界 定對位標記（即該對位孔242)之中心係沿著χ軸向左偏 移，則該Y軸切割道214B的切割中心線應沿著χ軸向 左修正二分之一或三分之二的χ軸位偏差值。較佳地， 經上述修正動作之後，可使得切割後封裝構造的腳位（即 外接端子的分佈位置）偏移公差縮減至+/_ 3〇微米（A m)，明顯小於該銲罩層240之偏移公差。 最後’依據修正後之X軸切割道2 1 4 A與Y軸切割道 _ 214B’切割該基板條本體210，以使每一基板單元213 分離成各自獨立之封裝構造。此外’由於修正後之χ轴 切割道214 A與Y轴切割道2丨4B較接近無偏移情況之原 始位置設計，在切割該些基板單元2 1 3以分離成若干個 半導體封裝構造之後’可防止設置於該些外接墊220之 外接端子過於靠近切割後半導體封裝構造之邊緣，進而 免除外接端子分佈不平均之情況。 請參閱第8A與8B圖所示，利用習知基板條構造與 本發明之多對位標記之基板條構造分別製成半導體封裝[y 15 201220379 構造之後緣示其外接端子與封裝構造邊緣之戴面示意 圖。如第8A圖所示，當習知設置一銲罩層14〇於該基 板單70 113時發生偏移之情況，該銲罩層丨4〇之該些連 接孔141無法對準該些外接墊12〇而形成有一位偏差值 D1。並且’該些外接端子2〇的位置是由該些連接孔ι4ι 來決定其分佈位置’所以該些外接端子2〇與該些外接墊 120中心之間亦形成有該位偏差值D1。因此，在形成封 _ 膠體10並切割成各自獨立之封裝構造之後，該些外接端 子20會太靠近封裝構造之邊緣^，因而造成表面接合 時種種不良影響。然而，在本發明中，如第80圖所示， 雖然利用相同製程能力，該銲罩層24〇也可能同樣發生 了如上述偏移之情況，即該些連接孔241與該些外接墊 220之間形成有一位偏差值D2 (D2等於m)，而使該銲 罩層240之該些連接孔241偏移而改變了該些外接端子 50之分佈位置，但由於本發明藉由該第一非銲罩界定對 Φ 位標5己232與該第二非銲罩界定對位標記233計算出該 銲罩界定對位標記之位偏差值（即D2)，進而修正為實際 切割道，所以在切割後能調整該些外接端子5〇與封裝構 造之邊緣4丨之間的距離，使得該些外接端子5〇不會因 該鲜罩層240之該些連接孔241偏移而太靠近已切割封 裝構造之邊緣41’故不會有嚴重的腳位偏移。在一較佳 實施例中，切割道修正的距離D3係可為該位偏差值的 的一分之一，或者修正為其它的適當距離，例如：三分 之二等等。 [S] 16 201220379 以上所述，僅是本發明的較佳實施例而已，並非對本 發月作任何形式上的限制，雖然本發明已以較佳實施例 揭露如上，然而並非用以限定本發明，任何熟悉本項技 術者’在不脫離本發明之技術範圍内，所作的任何簡單 修改、等效性變化與修飾，均仍屬於本發明的技術範圍 内。 【圖式簡單說明】 第圖.一種習知基板條構造之局部上視示意圖。 第3圖 第“A二2β圖：習知基板條構造之外接墊在銲罩層無偏 移與偏移時之顯露情況之上視示意圖。 第4圖 依據本發明之一具體實施例的一種多對位標記 之基板條構造之上視示意圖。 第5圖 依據本發明之一具體實施例的多對位標記之基 板條構造之局部放大示意圖。 第6圖 依據本發明之一具體實施例的多對位標記之基 板條構造依基板條本體之長邊平行方向剖切基 板單元之局部截面示意圖。 依據本發明之一具體實施例的多對位標記之基 板條構造沿X軸切割道剖切之局部截面示意 圖。 第7Α至7CH1 •分上占 • 據本發明之一具體實施例的多對位標 己之基板條構造封裝時的切割方法之元件示意 圖。 第8A與8只願· • 4用習知基板條構造與本發明之多對位[ 17 201220379 標記之基板條構造分別製成半導體封裝構造之 後繪示其外接端子與封裝構造邊緣之截面示意 圖。 【主要元件符號說明】 10封膠體 11封裝構造邊緣 3 0 晶片 41封裝構造邊緣 20外接端子 40封膠體 100基板條構造 110基板條本體 1 2 0 外接墊 1 3 0電鍍線 132非銲罩界定對位標記 141連接孔 142開孔 2〇〇多對位標記之基板條構造 210基板條本體 2 11模封面 2 1 4切割道 2 14A X軸切割道 220 外接塾 230電鍍線 232第一非銲罩界定對位標記 233第二非銲罩界定對位標記 240銲罩層 2 4 1 連接孔 圮丧札 242對位孔 1 3基板單元 2 1 2植球面 2 1 4B Y軸切割道 231金屬墊 5 0外接端子 213基板單元 2钧開孔 m 18 201220379 250電鍍層 D1、D2位偏差值 D3 切割道修正距離201220379 - VI. Description of the Invention: [Technical Field] The present invention relates to a wafer carrier for a semiconductor device, and more particularly to a substrate strip structure for a multi-alignment mark and a cutting method thereof when packaged. [Prior Art] Semiconductor devices on the market today use a batch method to fabricate a plurality of substrate units arranged in a matrix by using a grid-interleaved scribe line in advance on a surface of a substrate such as a printed circuit board. Processes such as die bond, wire bond, and encapsulation. After the package is completed, it is often necessary to perform a cutting operation to separate the substrate units from the substrate strip, thereby forming an individual semiconductor package structure, or stacking and integrating a plurality of semiconductor package structures into a package package. , POP), to supply the various needs of the market. Although the surface of the substrate strip defines a plurality of cut φ cuts, it is usually necessary to perform a cutting action on the substrate strip in accordance with the alignment mark as a positioning point reference during the cutting process. The alignment mark is generally located at the periphery of the substrate strip, or at the intersection of the four corners of the substrate unit at the intersection of the cutting path. As shown in FIG. 1 , a conventional substrate strip structure 100 ′ of a SMD pad is particularly applied to a substrate package of a package (POP), and mainly includes a substrate strip body 110 and a solder mask layer. The substrate strip body 110 has a plurality of substrate units 113 arranged in a matrix, and a plurality of external pads [S] 3 201220379 120 and a plurality of plating lines 130 are formed on the spherical surface of the substrate strip body 110. The external pads 120 are located in the substrate unit 113, and the plating lines 130 are staggered between the substrate units 113 and the periphery. The plurality of connection holes 141 of the solder mask layer partially expose the external pads 120 ′, that is, the connection holes ι 41 are smaller than the outer pads 1 20 and cover the periphery of the external pads 2 The external pads 120 are of a solder mask defined (SMD) type. In addition, a plurality of openings 1 42 of the solder mask layer are exposed to the plating lines 13A between the substrate units 113. Wherein, the electroplating lines 130 are crossed and at the corners of the substrate units 113. Under the exposure of the openings 142, a plurality of non-welding covers are defined to define the alignment marks 132 at the intersection of the cutting paths. Used as a benchmark for cutting. In this way, it is not necessary to design the alignment mark in the substrate unit 113, and the closest to the substrate unit 113, which meets the requirements of the precise alignment cutting channel of the high-density package. As shown in FIG. 2A, in the prior art, the substrate strip structure i 〇〇 should be in an ideal state, the solder mask layer and the substrate strip body 11 should be unbiased, and the solder mask layer in the original substrate strip design The connecting holes should be aligned at the central portions of the external pads 120, and the intermediate holes 142 should completely reveal the non-welding caps defining the alignment marks 132. After the substrate strip body no is cut to separate the substrate units 113, the portions of the external pads 120 exposed by the connection holes 141 may be kept at a predetermined distance from the edges of the substrate sheets το 11 3 so that, for example, solder balls After the external terminal ax is placed, it is not too close to the edge of the cut package structure. However, 'as shown in 2B ® 'in fact, because of the precision of the machine and the manufacturing tolerance of the welding layer m 4 201220379', the welding cap layer and the substrate strip body 110 are not as offset as described above. In the case, the standard tolerance of the offset of the solder mask layer is +/- 50 microns (#m). When the solder mask layer is offset, it indicates that all the connection holes 141 and the openings 142 of the solder mask layer are offset, that is, the positions of the connection holes 141 are changed and cannot be aligned. The central portion of the outer pad 120, even offset to the periphery of the outer pads 120, causes the offset of the external terminals. However, the center of the alignment mark 132 is defined by the non-welding masks as a reference during the cutting, so that the external pads i 20 are exposed at the edges of the connection holes and the edge of the substrate units 113. The distance changes. Therefore, after the external terminals are disposed on the portions of the external pads 120 exposed by the connecting holes 141, the distance between the external terminals and the edge of the packaged package structure is too close, resulting in the distribution position of the external terminals and the original design feet. The position of the bit is different, which in turn causes various possible problems in subsequent surface bonding. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a multi-alignment mark substrate strip structure and a cutting method thereof during packaging, which can improve the precision of the package structure in cutting completion, so as to avoid external terminals after packaging. Too close to the edge of the cut package construction. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a multi-paragraph substrate strip structure comprising a substrate strip body, a plurality of external turns, a plurality of bond wires, and a bump layer. The substrate strip system has a mold cover and a spherical surface. The substrate strip is composed of a plurality of bodies and arranged in a matrix. (5) 5 201220379 The substrate unit and a plurality of cutting paths between the substrate units and the periphery Where the scribe lines comprise at least one X-axis scribe line and at least one γ-axis scribe line. The external pads are disposed on the ball-forming surface and located in the substrate units. The plating wires are disposed on the ball-forming surface and located in the cutting channels, and the X-axis cutting channel and the γ-axis cutting channel Forming a metal pad at the intersection, and forming a first non-welding cover defining the alignment mark and a second non-welding cover defining the alignment mark on the periphery of the substrate strip body respectively located on the X-axis cutting channel and the γ In the shaft cutting track, the welding layer is formed on the surface of the ball, the welding layer has a plurality of connecting holes for exposing the external pads, a matching hole for partially exposing the metal pad, and a plurality of revealing the first The non-welding cover defines an alignment mark and the second non-welding cover defines an opening of the alignment mark, wherein the connection holes are smaller than the external pads, so that the external pads are defined by a solder mask, and the metal The portion of the pad exposed in the alignment hole is formed as a solder mask defining an alignment mark, wherein the first non-weld cover defining the alignment mark and the second non-weld cover defining a pair mark are adjacent to the metal pad, Used to calculate the welding mask boundary Bit deviation of the reference value of the mark point. The present invention further discloses a cutting method suitable for use in the substrate strip structure package of the above multi-alignment mark. The purpose of this issue (4) and the resolution of its technical problems can be further achieved by the following technical measures. In the foregoing substrate strip construction, the alignment aperture and the non-follower defining alignment marks may be cross-shaped. In the foregoing substrate strip construction, the solder mask layer may cover the plating lines at the metal crucible, the first non-weld mask defining the alignment mark and the second: m 6 201220379 solder mask defining the alignment mark The outer part. In the foregoing substrate strip structure, the external pads may be arranged in a peripheral manner. In the foregoing substrate strip structure, the openings may be circular, and the aperture is not less than the position of the solder mask defining the alignment mark. Two times the deviation value. It can be seen from the above technical solution that the multi-alignment mark substrate strip structure of the present invention and the cutting method thereof when sealing the skirt have the following advantages and advantages, and can be formed by cutting lines formed on the X-axis and the γ-axis by electroplating lines. The metal pad at the intersection of the track and the first non-welding cover in the X-axis and Y-axis cutting lane define the alignment mark and the second non-welding cover define the alignment mark and the alignment hole of the fresh cover layer partially exposes the metal pad A portion is formed as a specific combination relationship of the welding cap defining the alignment mark as a technical means thereof, even if the welding cap defines the alignment mark to change position due to the offset of the alignment hole of the welding cap layer, the first non-zinc cover is defined The alignment mark and the second non-weld cover define the alignment mark not to change its original position due to the opening deviation of the solder mask layer, so it can be used as a reference for calculating the deviation of the position mark of the welding cap defining the alignment mark. Point 'to facilitate the cutting action. Therefore, the accuracy of the package construction can be improved to avoid the external end of the package. The A.A1 is too close to the edge of the cut package structure. [Embodiment] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be noted that the drawings are simplified schematic diagrams, and only illustrated by way of illustration The basic architecture or implementation method of the present invention, so only the components and combinations related to the present case are shown. The components shown in the figure are not drawn in proportion to the number, shape and size of the actual m 7 201220379 implementation, and some size ratios are Other related size ratios are either exaggerated or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design. Detailed component layout may be more complicated. According to an embodiment of the present invention, a substrate strip structure of a multi-alignment mark is illustrated in a top view of FIG. 3, a partially enlarged view of FIG. 4, and a fifth view of a long side parallel direction of the substrate strip body. A partial cross-sectional view of a substrate unit and a partial cross-sectional view taken along line X of the X-axis. The multi-paragraph substrate strip structure 2 includes a substrate strip body 210, a plurality of external pads 22, a plurality of electroplated lines 230 and a solder mask layer 240. Referring to FIG. 3, and in conjunction with FIG. 5, the substrate strip body 210 has a mold cover 211 and a ball-fitting surface 212. The substrate strip body 210 is a plurality of substrate units integrally formed and arranged in a matrix. And a plurality of scribe lines 214 between the substrate unit 213 and the periphery, wherein the scribe lines 214 comprise at least one X-axis scribe line 214A and at least one Y-axis dicing street 214B. Specifically, the material of the substrate strip body 210 may be bismaleimide_triazine (1) (4), abbreviated as bt resin, and the cover 2U and the ball from the 212 are two-phase surface The surface shown in Fig. 3 is the spherical surface 212, and the mold cover 2" is located on the back side of the spherical surface 212. Therefore, the mold cover 2 ι can not be marked in Fig. 3. More specifically, the mold cover 2 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The wafer carrier can be used as a semiconductor package structure. The so-called "X-axis scribe line" is a scribe line parallel to the longer side of the substrate strip structure 200, and the so-called "γ-axis cutting lane" is Parallel to the substrate strip, the shorter side of the substrate is formed. Referring to FIG. 4, and in conjunction with FIG. 6, the external pads 220 are disposed on the ball-facing surface 212 and located on the substrate. Within unit 213, of which The pads 220 are disposed in each of the substrate units 213 and are provided by external terminals such as solder balls to serve as external passages for the substrate units 213. In this embodiment, the external pads 22 can be peripheral. The arrangement, for example, may be arranged in a single row or a double row at the periphery of each substrate unit 213. Alternatively, the external pads 22 may be arranged in a matrix or disposed at a central portion or a single portion of the substrate units 2 1 3 The side 'is configured according to the position of the various products. Please refer to Figure 4 and with reference to Figure 6, the electroplating line calls the 230 series a and is placed on the ball surface 212 and located in the A metal pad 23 1 is formed in the cutting path 214 and a first non-welding cover is formed at the intersection of the X-axis cutting path 214A and the Y-axis cutting path 21 4B. Non-solder mask defined, NSMD) alignment mark 232 and a second non-weld mask (NSMD) alignment mark 233, the first non-weld cover defining alignment mark 232 is located in the In the X-axis cutting lane 214A, the second non-fresh hood defines a pair The mark 233 is located in the γ-axis scribe line 2 1 4B. In detail, the plating lines 230 are metal wires for plating the external pads 22 〇 9 201220379, and the materials of the plating lines 230 are generally In the present embodiment, after the solder mask layer 240 is formed on the substrate strip body 210, a plating layer 250 may be formed on the external pads 220 and the metal pads 23 by the plating lines 230. 1. The first non-weld cover defines an alignment mark 232 and the second non-weld cover defines a exposed top surface of the alignment mark 233, and the material of the plating layer 250 may be nickel gold or gold to have a better Antioxidant capacity. Specifically, the plating layer 250 is coated on the external pads 220 to increase the bonding force between the external pads 220 and the external terminals. The electrical layer 250 is applied to the metal 231 and the alignment marks 232. 233 ′ can make the metal pad 231 , the non-welding cover defining the exposed portions of the alignment marks 232 , 233 appear as a bright surface, and has better recognition. Wherein, the metal pad 231 is formed in a cross shape just at the intersection of the two electroplating wires 230. Alternatively, in a variant, the shape of the metal pad 231 may be changed to a circle, a square, a diamond or the like. In a preferred form, the first non-weld cover defines the alignment mark 232 and the second non-weld cover defines the alignment mark 233, which can be a cross to help identify the first non-foam cover. Defining the alignment mark 232 and the first non-welding cover to define the center of the alignment mark 233, but disposed at different positions of the substrate strip body 210, respectively, for measuring the welding mask to define the alignment mark on the Y-axis The deviation from the position of the X axis. Referring to FIG. 4 , and in conjunction with FIG. 6 , the solder mask layer 240 is formed on the spherical surface 212 , and the solder mask layer 24 has a plurality of connecting holes 241 for exposing the external pads 220 , The alignment hole 242 of the metal pad 231 is partially exposed, and the plurality of openings 243 defining the alignment mark 232 and the second non-welding cover defining the alignment mark 233 are exposed. In the present embodiment, the solder mask layer 240 can cover the plating line 230 in the metal pad 23 1 , the first non-weld cover defining the alignment mark 232 and the second non-welding cover defining the alignment mark 233 Other parts than others. Generally, the ball-forming surface 212 is located in the exposed hole 241 of the solder mask layer 24, and the portion of the alignment hole 242 and the openings 243 is exposed. It should be covered by the solder mask layer 240. The connection holes 241 are smaller than the external pads 220, so that the external pads 220 are in the form of a solder mask defined (SMD), and the metal pads 23 are exposed in the alignment holes. The portion of 242 is formed as a splicing mark (SMD) alignment mark, that is, covering the periphery of the metal pad 231. Therefore, the center of the solder mask defining the alignment mark is defined by the alignment hole 242. The shape size determines 'the position offset direction and the offset amount of the alignment hole 242 are offset from the position of the connection holes 241 of the solder mask layer 240. · The offset amount is synchronized. In a preferred embodiment, the alignment hole 242 can be in the shape of a cross. The metal pad 231 is exposed to the alignment hole 242 to form a gold-plated cross shape, which is more advantageous for recognizing the center position. In addition, the openings 243 may be circular, and the aperture diameter is not less than twice the deviation value of the alignment mark defined by the solder mask, and the standard tolerance of the general solder mask offset is +/- 50 micrometers ( #m) 'The apertures of the openings 243 can be designed to be no less than 100 micrometers Qm) to ensure that the openings 243 can still reveal the first non-weld mask after the solder mask layer 24 is offset. A center point is defined between the alignment mark 232 and the second non-weld cover defining the alignment mark. (5) 201220379 In addition, the first non-weld cover defining alignment mark 232 and the second non-welding cover defining the alignment mark 233 are adjacent to the metal pad 23 1 as a calculation for defining the alignment mark of the welding cap The reference point of the deviation value and can define the original position of the X-axis cutting lane 214A and the Y-axis cutting lane 214B. The term "adjacent" as used herein means that the distance between the first non-welding cover defining the alignment mark 232 and the metal pad 231 and the distance between the second non-welding cover defining the alignment mark 233 and the metal pad 231 are not greater than The substrate units 213 are one-half the length of the same side. In general, the non-welding caps define the alignment marks 232, 233 to the metal pad 231 by a distance of about one-third or one-quarter of the same side length of the substrate units 213. In summary, the present invention can form the metal pad 23 1 at the intersection of the boring cutting path 214 Α and the boring cutting channel 214 β by the plating line 23 , at the 切割 切割 Α 214 Α and the γ The first non-welding cover defining alignment mark 232 and the second non-welding cover defining the alignment mark 233 in the shaft cutting path 214β and the alignment hole 242 of the welding cover layer 240 partially revealing the metal pad 23 1 A portion is formed as a technical means for defining a specific combination relationship of the alignment marks by the solder mask, even if the cladding defining the alignment mark changes position due to the offset of the alignment hole 242 of the solder mask layer 240, However, the first non-weld cover defining alignment mark 232 and the second non-welding cover defining the alignment mark 233 do not change their original positions due to the offset of the openings 243 of the solder mask layer 24 . Therefore, the second [S] solder mask defining alignment mark 232 and the second non-welding cover defining the alignment mark 233 can calculate the position deviation of the welding mask defining the alignment mark, thereby adjusting the cutting center to correct the setting. The distance from the external 塾22〇 to the edge of the seal 12 201220379 construction. Therefore, the accuracy of the package construction can be improved to avoid the external terminals of the package being too close to the edge of the cut package structure. The present invention also discloses a dicing method for the above-described multi-paragraph substrate strip structure 2 〇〇 encapsulation as exemplified in 帛7AJL 7Cffi to demonstrate the efficacy of the present invention. Referring to Figure 7A, a basic slat configuration 200 is provided which provides a plurality of alignment marks as previously described. The multi-paragraph substrate strip structure 2 includes the substrate strip body 210, the external pads 220, the plating lines 23A and the solder mask layer 240, which are shown in FIG. 7A. The cover 2 u of the strip body 2 1 0, so the external pads 220 located on the ball-forming surface 2 2, the plating lines 23 〇 and the solder mask layer 24 〇 cannot be marked in FIG. 7A. Coordinate with Figures 3, 5 and 6 as shown. Referring to FIG. 7B, the die strip cover 21 of the substrate strip body 21 faces upward, and the substrate strip structure 2 is packaged. The plurality of wafers 30 are disposed on the substrate units 213. And electrically connecting the wafers 30 to the substrate units 213, for example, the bonding wires formed by wire bonding or the bumps bonded together to electrically connect the wafers 30 and the substrate units 213. Then, a die 4 is formed on the die cover 211 of the substrate strip body 210, and the sealant 4 is not required to completely cover the die cover 211, but at least all of the substrate units 213 must be completely covered. In order to ensure that the encapsulant 40 can surely cover the substrate units 213 after being separated into a plurality of semiconductor package structures, thereby providing perfect protection. After the encapsulant 40 is formed, an external terminal such as a solder ball may be disposed on the external pads 22g as the soldering end points of the external connection of the substrate units 213. Referring to FIG. 7C, after the above steps are completed, the step of performing the cutting-cutting step is performed to fix the substrate strip structure: 2〇〇, and the welding mask defines the alignment mark, the first A non-weld cover defines the alignment mark 232 and the second non-shield defines the alignment mark 233 toward the position detecting device in the cutting machine. Grasping the weld hood defines a Y-axis deviation value between the alignment mark and the plating line 23 上述 having the first non-welding cover defining the alignment mark 232, and taking a position between the two as a 切割-axis cutting Correction of the road 214. The so-called r γ-axis misalignment value refers to the offset of the center of the weld mark defining the alignment mark (ie, the alignment hole 242) in the γ-axis direction, and the alignment mark can be defined by the welding hood (ie, the pair The center of the bit hole 242) is calculated by having the shortest distance of the plating line 230 of the first non-welding cover defining the alignment mark 232 in the same X-axis scribe line. And a suitable position may be taken between the center of the solder mask defining the alignment mark to the shortest distance of the plating line 230 having the first non-welding cover defining the alignment mark 232, for example: one-half or one-third At the same time, as the cutting reference of the corrected X-axis cutting path 214α. As shown in FIG. 7C, when the center of the solder mask defining the alignment mark (ie, the alignment hole 242) is offset along the γ axis, the cutting center line of the X-axis cutting path 2 14 应 should be along The y-axis deviation is corrected by one-half or two-thirds of the y-axis. At the same time, the X-axis deviation value between the alignment mark and the plating line 230 having the second non-fresh cover defining the alignment mark 233 is grasped, and the position between the two is taken as the Y-axis cutting. Amendment to Road 214B. The term "χ [ s] 14 201220379 Axial position deviation value" refers to the offset of the center of the welding mark defining the alignment mark in the direction of the x-axis, and the alignment mark can be defined by the welding cover (ie, the alignment hole 242) Among the to the shortest distances of the plating line 230 having the second non-welding cover defining the alignment mark 233 in the same crucible cutting lane. And a suitable position may be taken between the center of the solder mask defining the alignment mark to the shortest distance of the plating line 230 having the second non-welding cover defining the alignment mark 233, for example: one-half or one-third At the same time, as a γ-axis cutting path φ 214 Β corrected cutting reference. As shown in FIG. 7C, when the center of the weld cap defining the alignment mark (ie, the alignment hole 242) is shifted leftward along the χ axis, the cutting center line of the Y-axis scribe line 214B should follow the χ The axial left is corrected by one-half or two-thirds of the axial deviation value. Preferably, after the above-mentioned correcting action, the offset of the pin position of the packaged package structure (ie, the distribution position of the external terminal) can be reduced to +/_ 3 〇 micrometer (A m), which is significantly smaller than the solder mask layer 240. Offset tolerance. Finally, the substrate strip body 210 is cut according to the modified X-axis scribe line 2 1 4 A and the Y-axis scribe line _ 214B' to separate each substrate unit 213 into separate package configurations. In addition, 'because the modified y-axis traverse 214 A and the Y-axis scribe line 2 丨 4B are closer to the original position without offset, after cutting the substrate units 2 1 3 to be separated into several semiconductor package structures' The external terminals disposed on the external pads 220 can be prevented from being too close to the edge of the semiconductor package structure after cutting, thereby avoiding the uneven distribution of the terminals. Referring to FIGS. 8A and 8B, the substrate strip structure of the conventional substrate strip and the multi-alignment mark of the present invention are respectively fabricated into a semiconductor package [y 15 201220379. The rear edge of the structure shows the outer terminal and the edge of the package structure. Schematic diagram. As shown in FIG. 8A, when a solder mask layer 14 is disposed on the substrate unit 70 113, the connection holes 141 of the solder mask layer cannot be aligned with the external pads. 12〇 is formed with a deviation value D1. Further, the position of the external terminals 2 is determined by the connection holes ι4ι. Therefore, the position deviation value D1 is also formed between the external terminals 2 and the centers of the external pads 120. Therefore, after the encapsulant 10 is formed and cut into separate package configurations, the external terminals 20 are too close to the edge of the package structure, thereby causing various adverse effects on surface bonding. However, in the present invention, as shown in FIG. 80, although the same process capability is utilized, the solder mask layer 24 may also be subjected to the above-described offset, that is, the connection holes 241 and the external pads 220. A deviation value D2 is formed between D2 (D2 is equal to m), and the connection holes 241 of the solder mask layer 240 are offset to change the distribution position of the external terminals 50, but the present invention is The non-weld cover defines the alignment mark 233 for the Φ position mark 5.3 and the second non-weld cover, and calculates the position deviation value (ie, D2) of the weld mark defining the alignment mark, and then corrects the actual scribe line, so After cutting, the distance between the external terminals 5〇 and the edge 4丨 of the package structure can be adjusted, so that the external terminals 5〇 are not too close to the cut due to the offset of the connection holes 241 of the fresh cover layer 240. The edge 41' of the package construction does not have a severe foot offset. In a preferred embodiment, the trajectory corrected distance D3 can be one-half of the offset value of the bit, or modified to other suitable distances, such as two-thirds, and the like. [S] 16 201220379 The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made by those skilled in the art without departing from the technical scope of the present invention are still within the technical scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. is a partial top plan view showing a conventional substrate strip structure. Figure 3 "A 2 2β map: a schematic view of the outer surface of the conventional substrate strip structure when the solder mask layer is exposed without offset and offset. Figure 4 is a schematic view of a specific embodiment of the present invention. FIG. 5 is a partially enlarged schematic view showing the structure of a multi-paragraph substrate strip according to an embodiment of the present invention. FIG. 6 is a partially enlarged schematic view of a multi-paragraph substrate strip structure according to an embodiment of the present invention. The multi-paragraph substrate strip structure is a partial cross-sectional view of the substrate unit according to the long side parallel direction of the substrate strip body. The multi-paragraph substrate strip structure according to an embodiment of the present invention is cut along the X-axis cutting path A schematic view of a partial cross-section. Sections 7A to 7CH1 • Divisional components. A schematic diagram of a component of a method for cutting a multi-paragraph substrate strip according to an embodiment of the present invention. 8A and 8 The cross-sectional view of the external terminal and the package structure edge is shown after the conventional substrate strip structure and the multi-alignment of the present invention [ 17 201220379 labeled substrate strip structure respectively formed into a semiconductor package structure [Main component symbol description] 10 sealant 11 package structure edge 3 0 wafer 41 package structure edge 20 external terminal 40 sealant 100 substrate strip structure 110 substrate strip body 1 2 0 external pad 1 3 0 plating line 132 non-weld cover defined pair Position mark 141 connection hole 142 opening 2 〇〇 multi-alignment mark substrate strip structure 210 substrate strip body 2 11 mold cover 2 1 4 cutting lane 2 14A X-axis cutting lane 220 external 塾 230 plating line 232 first non-welding hood Defining the alignment mark 233, the second non-welding cover defining the alignment mark 240, the welding cover layer 2 4 1 connecting hole, the funeral 242, the alignment hole 1 3 the substrate unit 2 1 2 the spherical surface 2 1 4B Y-axis cutting path 231 metal pad 5 0 external terminal 213 substrate unit 2 钧 opening m 18 201220379 250 plating layer D1, D2 position deviation value D3 cutting track correction distance