TW201218384A - Thin film transistor and method for manufacturing the same - Google Patents

Abstract

The subject of this invention provides a thin film transistor having excellent confidence and reliability, high yield rate and excellent productivity, and a method for manufacturing the same. The solution of this invention provides the method for manufacturing the thin film transistor, which has: a step of forming a gate electrode on a substrate; a step of obtaining a laminate comprising a first insulating film, an oxide semiconductor film and a second insulating film by means of forming the first insulating film that covers the gate electrode on a substrate, the oxide semiconductor film on the first insulating film, and a second insulating film on the oxide semiconductor film; a step of forming a gate insulating layer, an active layer and a channel protection layer respectively by means of patterning the first insulating film, the oxide semiconductor film and the second insulating film of the laminate; and a step of forming a source electrode and a drain electrode. The first insulating film, the oxide semiconductor film and the second insulating film are not exposed to the atmosphere and are formed continuously.

Description

201218384 VI. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly to a film which is excellent in reliability and reproducibility, and which has high yield and excellent productivity. A transistor and a method of manufacturing the same. [Prior Art] At present, a ruthenium film transistor, particularly an electric field effect type transistor, is widely used as a semiconductor memory integrated circuit, a high frequency signal amplification element, and the like. Moreover, as a switch of a flat panel display device (FpD) such as a liquid crystal display device (LCD) or an electroluminescence display device (EL) '% Em Em 〇 Display (FED) 兀Among the electric and chemical-type transistors, a thin film transistor (hereinafter also a private TFT) can be used. The TFT used in the flat thin image display device (hereinafter also referred to as FPD) forms an amorphous f-short film or a polycrystalline silicon film as an active layer on a glass substrate. It is necessary to use a relatively high-temperature thermal step in the living layer using the above amorphous amorphous film or polycrystalline silicon film. Therefore, although a glass substrate ' can be used, it is difficult to use a substrate made of a resin having low heat resistance. Further, the FPD ′ is required to be further reduced in thickness, weight, and breakage resistance. A substrate made of a lightweight and flexible resin is also used instead of the glass substrate. Therefore, the development of a TFT having an amorphous oxide semiconductor film of a low-temperature film formation, such as an In_Ga_Zn_〇-based amorphous oxide, is actively carried out (see, for example, Patent Documents 1 and 2). In the case of Patent Document 1, a device comprising an amorphous oxygen oxide insulator of at least one element of the i-th insulating layer is provided with a conductor film which constitutes an active layer in this order. The oxygen hole density at least one of the interface with the first insulator at the interface with the first insulator is lower than the portion other than the first interface layer. Further, Patent Document 1 discloses that the oxygen pore density is higher than that of the bulk layer. In Patent Document 1, the second insulating layer and the oxide semiconductor oxide are formed on the first insulating body. The semiconductor film constitutes an active layer. In addition to the film formation step of the first insulating conductor film, at least the interface layer between the first and second layers of the oxide semiconductor film and the second interface layer The first and second layers of the guest semiconductor film have a low oxygen pore density. Further, in Patent Document 1, a thin gate metal film, a thin film device as a first insulating material (thin film edge body, an oxide semiconductor film containing at least Zn, Ga, and an indium compound, a buildup layer structure, and a thin oxide layer) In the literature, the first interfacial layer, that is, the first interfacial layer, and the second interfacial layer, the oxygen interfacial density first interface layer of the main layer of the oxide semiconductor film The second interface layer has a low pore density. A method for producing a thin film device including a conductor film and a second insulator by a step of forming a semiconductor film and a step on an oxygen substrate is disclosed. The specific body, the second insulator, and the oxide are half-oxidized, so that the oxygen hole density of the portion of the interface between the second insulator at the interface of the first insulator is higher than that of the oxygen interface layer. The other part, that is, the laminated structure of the main body device, is formed by a gate insulating film, an oxide half 201218384 conductive film, a source, a drain metal film, and a protective edge film as a second insulator. When the layer structure of the thin film device is formed, it is formed after the gate insulating film is formed, and the oxidative treatment and the formation of the oxide semiconductor film are performed in order without being exposed to the atmosphere. Document 2 discloses an electric field effect type transistor which is an electric effect type transistor having a channel layer of an amorphous oxide film containing In or Zn, wherein the amorphous oxide film system contains 1 〇 16 / cm 3 to氢2G/cm3 or less of a hydrogen atom or a ruthenium atom. The electric field effect type electro-optic system can be formed, for example, by the steps of forming a gate electrode to form a gate electrode. The step of forming an insulating layer forms a source electrode and a drain electrode. a step of forming an electrode; and a step of forming a channel layer composed of an amorphous oxide while introducing a hydrogen atom-containing body (except for 'water vapor) and oxygen into a film-forming package with a predetermined partial pressure. [Previous Technical Literature [Patent Document 1] JP-A-2008-42088 [Patent Document 2] JP-A-2007-103918 [Non-Patent Document] [Non-Patent Document 1] APPLIED PHYSICS LETTERS (Applied Literature) 90 , 1 921 01 20 [Non-Patent Document 2] APPLIED PHYSICS LETTERS 92, 072104 2008 [Invention] [Problems to be Solved by the Invention] Patent Document 1 'After forming a film of an oxide semiconductor film of an active layer 'The system is patterned after the atmosphere is opened to become the required shape. On the field, it is treated as a gas. 201218384 At this time, the channel behind the active layer is exposed to the atmosphere, and is exposed when patterned. Etching liquid, etc. Therefore, the back channel has a problem of adsorbing moisture, adsorbing oxygen, or mixing impurities such as impurities. When oxygen, moisture, or the like is adsorbed on the surface of the back channel, it is known that the characteristics of the crystal crystal change (see Non-Patent Documents 1 and 2). Therefore, Patent Document 1 has a problem of poor reliability and reproducibility. Further, Patent Document 2 is an amorphous oxide film having a hydrogen atom or a ruthenium atom of 10 〇 16 /cm 3 or more and i 〇 2 0 / cm 3 or less, thereby reducing hysteresis. However, in Patent Document 2, in order to add hydrogen to the amorphous oxide film (channel layer), it is necessary to introduce a hydrogen atom-containing gas (except water vapor) and oxygen into the film forming apparatus at a predetermined partial pressure. The steps are troublesome' while adding the number of steps. In order to eliminate the problems based on the foregoing prior art, the object of the present invention is to provide a thin film transistor which is excellent in reliability and reproducibility, and which has high yield and excellent productivity, and a method for producing the same. [Means for Solving the Problems] The above aspect of the present invention provides a method of manufacturing a thin film transistor, in which at least a pad electrode, a ruthenium, a ruthenium layer, and a channel layer are provided on a substrate. Functional activity

The channel region of the active layer, the J-channel retention layer, the source electrode, and the drain-pole, is characterized by having a w M m ^ . The step of forming the gate electrode on a different substrate, Forming a first insulating film on the substrate by covering the closed electrode, and forming an oxide semiconductor film on the front surface of the first I and the germanium film, and then escaping the oxide half Guide w the aforementioned! The insulating film and the front insulating film 2 are obtained, and the first layer of the laminated body is obtained by the step of forming the laminated body #+. # ^ of the oxide semiconductor film and the second insulating layer 201218384. The oxide semiconductor film and the second insulating film are patterned to form the inter-electrode insulating layer, the active layer and the channel protective layer, and the step of forming the source electrode and the drain electrode; The second insulating film, the oxide semiconductor film, and the second insulating film are continuously formed without being exposed to the atmosphere. In the present invention, the step of forming the channel protective layer, the active layer and the front/polar insulating layer preferably includes the step of patterning the front insulating film of the laminated body to form the channel protective layer; 1. The step of patterning the insulating film to form the closed-electrode insulating layer. The step of patterning the oxide semiconductor film to form the active layer and forming the source electrode and the front drain electrode are provided. Forming a conductive film on the substrate and electrically, tf and using the channel protective layer as an etch stop layer (step etrg pper), using the acid surname to engrave the conductive film (4), and the aforementioned "邑 膜 film The second insulating film of the above-described oxidation is preferably formed by a bismuth ore method. Preferably, the first insulating film and the second insulating film of the oxide described above are preferably a back pressure of the film and a front side of the film, and the second insulating film is preferably oxygen and It is formed under conditions of 0.1% or more and less than 10%. The sub-combination ratio is and is preferably a step in which the second insulating film is composed of G and the channel protective layer is formed to form a half of the oxide film of the above Ga 201218384: a step of forming a photoresist on the oxide film of the above-mentioned ?, a portion of at least the channel region of the photoresist film: a portion which becomes a pattern portion and a portion other than a non-pattern portion; and: a test solution for use The step of removing the non-pattern portion by the arrow, +, 1 to form a pattern; in the first 4 diagrams, the shape of the non-pattern portion is removed, and when the non-pattern portion is removed, the arrow below the non-pattern buffer The + oxide film of the Ga is divided into the channel protective layer by the alkali solution. The second aspect of the 'X month is to provide at least a gate inter-electrode insulation on the substrate, 彳 4 a The active layer of the function of the channel protective layer, the patch covering the active layer of the layer, the protective layer of the bitter cover layer, the channel protective layer of the domain, the source electrode and the drain electrode of the front layer are formed on the active layer. The aforementioned channel protection sound,

(1) The channel protective layer and the above-mentioned active I protection sounds toward Shanger, +, J虱, and the degree of 攸 攸 攸 通道 通道 通道 通道 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓 蔓1 The thickness of the hydrogen concentration in the vicinity of the interface between the protective layer and the front surface has a very small value: in the channel protective layer and the active layer value and the differential value of the hydrogen concentration profile, the negative value changes from negative to positive, and simultaneously The difference in the aforementioned differential values near the face is lxl()'h. '22 is the aforesaid ... hydrogen "is again" preferably in the above-mentioned living s & layer of the channel protective layer interposed between the formation of the source electrode and the drain electrode. "Yu Cheng, and ' compare Preferably, the active layer is mainly composed of a non-daily solar semiconductor, and in this case, it is preferable that the active layer is composed of an amorphous oxide semiconductor containing ruthenium. And zn 201218384 [Effect of the invention] In the method for producing a thin film transistor of the present invention, the first insulating film as the gate insulating layer, the oxide semiconductor film as the active layer, and the second insulating film as the channel protective layer are continuously exposed without being exposed to the atmosphere. The formation of the ground can suppress the entry of impurities into the interface between the active layer and the channel protective layer, and can suppress the displacement of moisture, oxygen, impurities, and the like in the active layer, thereby suppressing the displacement of the threshold value of the ** threshold. A thin dielectric transistor having good characteristics is produced with good reproducibility and high yield. 薄膜 According to the thin film transistor of the present invention, the channel protective layer and the hydrogen/density in the active layer are oriented from the channel protective layer. The layer is reduced, and the hydrogen concentration profile near the interface between the channel protective layer and the active layer has a minimum value and a maximum value, and the micro-knife value of the hydrogen concentration shift is negatively changed to the vicinity of the interface between the channel protective layer and the active layer. At the same time, the difference in the differential value in the vicinity of the interface is 1 X 1 〇 2G or more, and it is possible to exhibit good TFT characteristics and improve long-term reliability. [Embodiment] [A form for implementing the invention] The thin film transistor of the present invention and the method for producing the same are described in detail with reference to the preferred embodiments shown in the drawings. Fig. 1 is a schematic cross-sectional view showing a thin film transistor according to the first embodiment of the present invention. The thin film transistor (hereinafter also referred to simply as a transistor) is a type of 〇-type electric field effect type transistor having a substrate 丨2; a gate electrode 14 · 'gate insulating layer 16; function as a channel layer Active layer ¢: -10- 201218384 18 'Channel protective layer 20; source electrode 22; drain electrode 24 and planarization layer 2 6 ° The transistor i 施加 is applied to the gate electrode 14 to control the activity Layer 1 8 The current flowing in the track region c has an active element for performing a function of switching the current between the source electrode 22 and the drain electrode 24. The transistor system shown in Fig. 1 is generally referred to as a lower gate. A bottom gate top contact constructor. The gate electrode 14 is formed on the surface 1 2 a of the substrate 12 in the transistor 10', and is on the surface 1 2 of the substrate 12 in such a manner as to cover the gate electrode 14. a forming a gate insulating layer 16. The active layer 18 is formed on the surface 16 6 a of the gate insulating layer 16. A channel protection covering the channel region C of the active layer 18 is provided on the surface 18 8 of the active layer 18. Layer 20. A source electrode 2 2 and a drain electrode 24 are formed on the surface 18 8 of the active layer 18 with the channel protective layer 20 interposed therebetween. The source electrode 22 is formed on the surface 16a of the gate insulating film 16 so as to cover the surface 18a of the active layer 18 and a part of the surface 20a of the channel protective layer 20. Further, the gate electrode 24 which is paired with the source electrode 22 is provided on the surface 16a of the gate insulating film 16 so as to cover the surface 18a of the active layer 18 and a part of the surface 20a of the channel protective layer 20. It is formed to face the source electrode 22. That is, the source electrode 22 and the electrodeless electrode 24 are formed above the surface 2A of the open channel protective layer 20 so as to cover a portion of the surface 18a of the active layer 18 and the surface 20a of the channel protective layer 20. The planarization layer 26 is formed to cover the source electrode 22, the channel protective layer 20, and the drain electrode 24. The transistor 10' substrate 12 is not particularly limited. For the substrate 12, an inorganic -11 - 201218384 material χ ' substrate such as glass or Y S Z (oxidized indium arsenide) can be used! 2 It is also possible to use polypyridyl acid (4), second brewed polycalyte diacetate, etc.), polythene, polyethyl carbonate (pES), polyaromatic brewing, dilute propylene A liquid crystal organic material such as a synthetic resin such as an alcoholic acid, a polyruthenium (ρι), a polycycloolefin, a reduced-chain, or a poly(fluorene trifluoroethylene). When the glass is used for the substrate 12, in order to reduce the elution of ions from the glass, it is preferable to use the non-glass. When X' is used for the substrate 12' to use a limestone, it is preferable to use a barrier coating which is subjected to dioxotomy or the like. Further, when an organic material is used for the substrate 12, it is preferably excellent in heat resistance and dimensional stability, such as solvent resistance, electrical insulating properties, workability, low air permeability, and low moisture absorption. As the substrate 12, a flexible substrate can also be used. The flexible substrate preferably has a thickness of from 50/zm to 500 //m. This is because when the thickness of the flexible substrate is less than 50 # m, it is difficult for the substrate itself to maintain sufficient flatness. When the thickness of the flexible substrate exceeds 500//rn, the pullability of the Maxtor is reduced. , making the substrate itself difficult to free; Here, in the present invention, the flexible substrate refers to an organic substrate and a metal substrate which are materials and structures as described below. As the organic substrate constituting the flexible substrate, for example, a saturated polyester (PET) resin substrate or a polyethylene naphthalate (pen) resin substrate can be used for conjugated anti-butyric acid-acetic acid resin substrate, and polycarbonate. Vinegar (pc) resin substrate, polyether (PES) resin substrate, poly; ε wind (psF, PSU) resin substrate, polyarylate (PAR) resin substrate, cyclic polyolefin (c〇p, COC) - 12- 201218384 Resin substrate, cellulose resin substrate, polyimine (PI) resin substrate, polyamidoximine (P AI) resin substrate, maleimide-olefin tree ruthenium substrate A guanamine (PA) resin substrate, an acrylic resin substrate, a gas resin substrate, an epoxy resin substrate, a polyoxyn resin film substrate, a polybenzazole resin substrate, or an episulfide compound A substrate, a liquid crystal polymer (LCP) substrate, a cyanic acid-based resin substrate, and an aromatic resin substrate. Further, the organic substrate also includes a plastic substrate of the composite material shown below. As the plastic substrate of the composite material, for example, a composite material with cerium oxide particles; a composite material with metal nanoparticles, inorganic oxide nanoparticles, inorganic nitride nanoparticles, or the like; Composite of nanofibers and microfibers; composite with carbon fiber and carbon nanotubes; composite with glass shards, glass fibers, glass beads; composite with particles with clay mineral or mica derived crystalline structure And a composite material in which the thin glass and the organic material constituting the resin substrate exemplified as the organic substrate are one less than one joint. In the case of a metal substrate which is a flexible substrate, it is possible to use a metal substrate which is a stainless steel substrate or a metal layer which is formed by laminating different metals. Further, as the metal system, an aluminum substrate can be used, or an insulating sheet which is raised on the surface by a soiling treatment, for example, an anodic emulsification treatment. When the aluminum base of the π-deposited film is insufficient, the insulating property is formed when the substrate 12 is made of a plastic film or the like. -13- 201218384 When a flexible substrate is used for the substrate 1 2 ', a hard coat layer, an undercoat layer, or the like may be further provided as necessary. Further, it is also possible to provide a moisture-proof layer (gas barrier layer) on the front or back surface thereof for preventing the passage of water vapor and oxygen. As the material of the moisture-proof layer (gas barrier layer), an inorganic substance such as Nitrogen Oxide Oxide or Oxide can be suitably used. Further, a structure in which an organic film such as an acrylic tree or a oxy-resin is laminated may be used. The anti-transmission wide layer (gas barrier layer) can be formed using, for example, a high-frequency sputtering method. The interpole electrode 14 can be, for example, Al, Mo, Cr,,,,,,, - v i a , i l

Metal such as Au or Ag or alloys thereof, alloys such as AiNd or ApC, tin oxide, oxidized, indium oxide, indium tin oxide (ITO), indium zinc oxide (yttrium oxide), etc. $ aniline, poly. It is formed by an organic conductive compound such as phenophene or polypyrrole or a mixture thereof. As the gate electrode 4', it is preferable to use Mo, Mo alloy or Cr from the viewpoint of reliability of TFT characteristics. The thickness of the gate electrode 14 is, for example, Mnm to 1000 nm. The thickness of the gate electrode 14 is preferably 2 〇 nm to 5 〇〇 nm, and more preferably 40 nm to 1 〇〇 nm. The method of forming the gate electrode 14 and the method of forming the gate electrode 14 are not particularly limited. For the gate electrode = i, a wet method such as a printing method or a coating method, a vacuum ruthenium plating method, a sputtering method, an ion 喑〃 卞 卞 卞 mining method, or the like; a chemical method such as CVD or plasma CVD; And dry Wan style # to form. These can be selected in consideration of the suitability of the picker α constituting the gate electrode 14. For example, using Mo or Mo to form a + + formation of a pet electrode to form a gate electrode 1 4 拄 DC sputtering can be used. Further, in the case where the J-bit wrap 14 is an organic compound, a wet film forming method can be used. Conductive Conductor -14- 201218384 At least two or more of the inter-electrode insulating layers 16 can be used. An insulator such as Si〇2, SiNx, SiON, Al2〇3, Ys〇3, Ta2〇5, or the like or a compound thereof. Further, a polymer insulator such as polyimide may be used in the gate insulating layer 16. The thickness of the pole insulating layer 16 is preferably 10 nm to 1 〇//m. In order to reduce the leakage current, it is necessary to increase the voltage resistance, and it is necessary to increase the film thickness to some extent. However, when the film thickness of the gate insulating layer 6 is increased, the driving voltage of the transistor 10 rises. Therefore, in the case of the inorganic insulator, the thickness of the gate insulating layer 16 is preferably a polymer insulator of MnmqOOk, and more preferably "m~5" m. Also, because of the high dielectric like Hf〇2 When the constant insulator is used in the gate insulating layer 16, the pad insulating layer 16 can be driven at a low voltage even if the film thickness is increased, and the gate insulating layer 16 is used to use the high dielectric constant source electrode 22 and the drain electrode. For the electrode 24, for example, a metal such as Mo, Cr, Ta, Ti, Au, or Ag or an alloy thereof, an alloy such as Ab or Nd, APC, or the like, tin oxide, zinc oxide, or indium oxide 'indium tin oxide can be used. Ιτο), the formation of a metal oxide conductive material such as indium yttrium (IZ〇). Also, regarding ΙΤο # ότ w, you can either 疋 amorphous or crystallization IT 〇 as the source electrode 22 And the drain electrode 24 is preferably an M 〇 or M 〇 alloy from the viewpoint of the dependence of the TFT characteristics. Further, the source: 22 and the thickness of the electrodeless electrode 24 are, for example, i 〇 nm 〜1 〇〇〇 nm. The source electrode 22 and the drain electrode 24 can be formed by forming an upper composition=conductive film and using lithography* The wire element is formed by etching the conductive film with an etching solution using an acid. -15- 201218384 Further, a method of forming the conductive film having the above-described composition of the source electrode 22 and the drain electrode 24 is not particularly limited. The conductive film of the above composition may be a wet type such as a printing method or a coating method, a physical method such as a vacuum ruthenium plating method, a sputtering method, or an ion plating method, or a chemical such as a CVd or an electropolymerization CVD method. For example, when the source electrode 22 and the drain electrode 24 are formed using Mo < Mo alloy or amorphous IT, for example, a ruthenium film or a ruthenium film or an amorphous ruthenium film can be formed. m Then, lithography is used. A photoresist pattern is formed on the M 〇 film or the M 〇 alloy film or the amorphous ITO film, and the film is etched using an acid etchant.

The Mo alloy film or the amorphous IT film is etched to form the source electrode 22 and the drain electrode 24. When a Mo film or a Mo alloy film is used for the source electrode 22 and the gate electrode 24, a mixed aqueous solution called phosphorus phosphatidyl phosphate, nitric acid, and acetic acid can be used as the etching liquid. The phosphorus-nitrocetic acid water system is generally known as a PAN (Phosphoric-Acetic-Nitric-acid), and the ratio of each component of the phosphorus-nitroacetic acid water is arbitrary, depending on the composition of the various applications. Further, as the phosphorus nitroacetic acid water, for example, a mixed acid A1 etching solution manufactured by Kanto Chemical Co., Ltd. or a Mo etchant Ts1 manufactured by Azusa Pure Chemical Industries Co., Ltd. can be used. Further, when amorphous ITO is used as the source electrode 22 and the gate electrode 24, oxalic acid can be used as the residual liquid. As the oxalic acid, for example, IT〇_〇6N manufactured by Kanto Chemical Co., Ltd. can be used. The active layer 18 is a function of the channel layer and can be formed using a germanide semiconductor. As an oxide semiconductor constituting the active layer 18, for example -16 - 201218384

If you can use ln203, ZnO 'Sn02, CdO

Indium-Zinc-Oxide (Indium-Zinc-Oxygen; IZO), Indium-Tin-Oxide (Indium-Tin-Oxygen; ITO), Gallium-Zinc-Oxide (Gallium-D-Oxygen; GZO), Indium-Gallium-Oxide (indium-gallium-oxygen; IGO),

Indium-Gallium-Zinc-Oxide (indium-gallium-zinc-oxygen; IGZO). The active layer 18 is preferably an amorphous semiconductor as a main component. Further, among the active layer 18'' oxide semiconductors, it is preferable to use an amorphous oxide semiconductor which can be formed of a plastic film having low heat resistance. As described above, the amorphous oxide semiconductor which is excellent in low temperature production is an amorphous oxide semiconductor containing at least In and Zn. The amorphous oxide semiconductor used in the active layer 18 is composed of In-Ga-Zn-Ο and is composed in a crystalline state.

An amorphous oxide semiconductor represented by InGa〇3(ZnO)m (m is a natural number less than 6) is preferable, and an amorphous oxide semiconductor represented by InGaZn〇4 is more preferable. The characteristics of the amorphous oxide semiconductor having such a composition are such that the electron mobility increases as the conductivity increases, and the control conductivity can be controlled by the oxygen partial pressure during film formation. Further, the thickness of the active layer 18 is preferably from 1 nm to 1 nm, more preferably from 2.5 nm to 50 nm. Further, the oxide film is also simply referred to as an IGZO film of In_Ga_Zn_〇-based amorphous material constituting the active layer 18. The fruit production diagram (4) is a graph in which the vertical axis uses hydrogen concentration and the horizontal axis uses ice to show the gate insulating layer, the active layer, and the channel protective layer cloth. (b) shows the importance of Fig. 2 (4) Part: Chart, and (4) shows the differential value of the curve in Figure 2 (4) in Figure -17-201218384. The depth of the horizontal axis of Figs. 2(a) to (c) is such that the surface of the channel protective layer 20 is set to zero. Further, in the case of the Di-based channel protective layer 20 shown in Figs. 2(a) to 2(c), the D2 shown in Figs. 2(a) to 2(c) corresponds to the active layer 18, and Fig. 2 The D3 shown in (a) to (c) corresponds to the gate insulating layer 16. The curve A shown in Fig. 2 (a) and (b) shows an example of the hydrogen concentration profile of the transistor 10 of the present embodiment, and shows the measurement results of the transistor of the first embodiment described later. Further, the curve E shown in Fig. 2(c) shows an example of the differential value of the transistor 10 of the present embodiment, and shows the measurement results of the transistor of the first embodiment to be described later. Further, the hydrogen concentration was determined by SIMS (Secondary Ion Mass Spectrometry). In the transistor 10 of the present embodiment, the hydrogen concentration in the channel protective layer 20 (region D) and the active layer 18 (region D2) is shown by the curve A shown in Figs. 2(a) and 2(b). It is reduced from the channel protective layer 20 toward the active layer 18. As shown by the curve A in Fig. 2(b), the hydrogen concentration profile near the interface a of the channel protective layer 20 and the active layer 18, that is, near the surface 18 8 of the active layer 18 has a minimum value / 3 1 And the maximum value / 3 2 . Further, as shown in the graph (B) of Figs. 2(a) and 2(b), an example of the hydrogen concentration of the prior transistor is shown, and the hydrogen concentration of the transistor of Comparative Example 1 to be described later is displayed. In the prior transistor, although the hydrogen concentration in the region (channel protective layer) and the region D2 (active layer) decreased from the region D (the channel protective layer) toward the region D2 (active layer), there was no extreme value. Further, in the transistor 10 of the present embodiment, as shown by the curve E of Fig. 2(c), in the vicinity of the interface α of the channel protective layer 20 and the active layer 18, the differential of the milk concentration profile of -18-201218384 The value system changes from negative to positive, and the difference in the differential value near the interface ^ is 1χ1〇2. the above. That is, the difference between the minimum value r i and the maximum value ^ 2 of the differential value in the vicinity of the interface α of the oil line 第 in Fig. 2 (4) is ΙχΙΟ20 or more. For example, the curve ε of Fig. 2 (4) has a difference of 2.85 χΐ〇 20 in the vicinity of the interface α. Further, the curve F of Fig. 2(c) shows an example of the differential value of the previous transistor and shows the differential value of the transistor which compares you later. The previous electro-crystal system is represented by, for example, the curve F of Fig. 2 (4), although the differential value of the hydrogen concentration profile near the interface α changes from negative to positive, but the difference in differential value near the interface α & 8 59χ1〇19 The difference in differential values is small. Also, the difference between the differential values is the displacement of 2 临 threshold. When the difference is "lxl" or more, it is possible to suppress the hydrogen concentration in the active layer 18 of the transistor 10 of the present embodiment as shown in the second region (4) and (9) of Fig. 2 (4) and (9) being 1 〇 2 lat 〇 / cm 3 or more and The concentration of hydrogen in the active layer 18 can be 1 〇 2 丨 atoms/cm 3 or more by the production described in detail later. Here, the carrier concentration of the amorphous oxide constituting the active layer 18 can be sufficiently obtained by various means. It is adjusted to the required value. The carrier concentration of the amorphous oxide is not particularly limited, and it is preferably 古5 gripper 3 or more. It is preferably 1×10 〇 b/cm 3 〜 lxl 〇 21/cm 3 . The carrier concentration of the amorphous oxide can be adjusted by the adjustment means using oxygen defects, the adjustment means using the composition ratio, the adjustment means of the pure substance, and the adjustment means using the oxide semiconductor material, which will be described in detail below. Means to adjust. Moreover, regarding the adjustment of the second degree of amorphous oxidation, various adjustment means can be used alone, or appropriate: various adjustment means. -19- 201218384 First, in the use of oxygen defect adjustment means, a conductor has been produced Active when oxygen is deficient The concentration of the carrier of the layer is increased so that: = = the amount of oxygen-deficient defects can be controlled, and the carrier degree of the oxide half-body can be controlled. The oxygen partial pressure in the film which is the amount of oxygen deficiency control, and the concentration after the film formation; :, there are ^ ^ milk 'morning and processing time, etc.. Here's the so-called post-processing, specifically #1〇吖 or more, oxygen electric treatment, UV odor, oxygen at the king. Among these methods, From the viewpoint of productivity, it is preferable to control the partial pressure of oxygen in the film formation. By adjusting the oxygen content in the film formation, it is possible to "enrich the carrier of the oxide semiconductor" and adjust the composition ratio. It is known that the carrier concentration changes by changing the metal composition ratio of the compound semiconductor. For example,

InGaZni-xMgx〇4, when the ratio of Mg is increased, the carrier concentration is small. Further, in the oxide system of (Ιη203) mouth (Ζη0)χ, when the Zn/in ratio is above, the carrier concentration becomes smaller as the Zn ratio increases. As a specific method of changing the composition ratios, for example, in the film formation method by sputtering, a target having a different composition ratio is used. Further, by using a multi-component target, co-sputtering and individually adjusting the sputtering rate, the composition ratio of the film can be reorganized. Further, in the adjustment means using impurities, the carrier concentration can be reduced by using an element such as an oxide semiconductor Li, Na' Mn, Ni, Pd, Cu, Cd, C, N, or P as an impurity. The method of adding an impurity is carried out by co-sputtering an oxide semiconductor and an impurity element, and by an ion doping method of ion-doping an impurity element in an oxide semiconductor which has been formed. 201218384 The above-mentioned means for adjusting the concentration of the carrier is a method for adjusting the concentration of the carrier in the system. However, the same-oxide semiconductor material can change the carrier concentration. The s 吏 半 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在Thus, the carrier concentration can be adjusted by changing the 半 oxide semiconducting. The primary bovine conductor material, the active layer 丨8 composed of an amorphous oxide, and the polycrystalline sintered body of the ruthenium compound semiconductor can be formed by using an oxygen film method as the I target system. Among the vapor phase film formation methods, sputtering 2 and vapor phase formation (PLD method) are suitable for forming an active layer and/or pulsed laser deposition, and are preferable from the viewpoint of generosity. The active layer 丨8 system ώ: S, +曰,, ^ is formed by a controllable degree of vacuum and oxygen, for example, using RF magnetics. Also / the more the flow rate, the conductivity of the active layer 18 can be changed. The smaller the channel protective layer 20, the function is to protect the active layer 18, especially the channel region c, when the source electrode 22 and the electrodeless electrode 24 are formed, without being etched by the surname. The channel protective layer 20 is disposed to cover at least the channel region C of the active layer 18. The channel protective layer 20 is formed using an oxide of Ga.

The oxide of Ga is, for example, Ga203. Further, the thickness of the channel protective layer 20 is preferably from 1 nm to 1 nm, more preferably from 5 nm to 1 Οητη. The planarizing layer 26 is formed for the purpose of protecting the channel protective layer 20, the source electrode 22, and the drain electrode 24 from deterioration by the atmosphere and for insulating the electronic component fabricated on the transistor. -21 - 201218384 The flattening layer 26 of the present embodiment is formed by subjecting a photosensitive acrylic resin to heat hardening treatment in a nitrogen atmosphere. For the photosensitive acrylic resin, for example, PC405G manufactured by JSR Corporation can be used. The planarizing layer 26 may be a metal oxide such as MgO, SiO, Si 2 , A1203, GeO, NiO, CaO, BaO, Fe203, Y203' or TiO 2 in addition to the above-mentioned photosensitive acrylic resin; SiNx, Metal nitrides such as SiNxOy; metal fluorides such as MgF2, LiF, A1F3, or CaF2; polyethylene; polypropylene; polymethyl methacrylate, polydioxane, ethylene, trifluoroethylene, dichloroethylene a copolymer of ethylene; a copolymer obtained by mixing a monomer containing tetrafluoroethylene and at least one comonomer; and a fluorine-containing copolymer having a cyclic structure in a copolymerization main chain, having a water absorption ratio of 1% or more A water-absorbent substance; a moisture-proof substance having a water absorption ratio of 0.1% or less. The method of forming the planarization layer 26 is not particularly limited. The planarization layer 26 is sufficient for applications such as vacuum plating, sputtering, reactive sputtering, MBE (molecular ray epitaxy), cluster ion beam i〇n, ion plating, plasma Polymerization method (high-frequency excitation ion plating method), electropolymerization CVD method, laser CVD method, thermal CVD method, gas source CVD method, coating method, printing method, or transfer method. In the transistor 1 of the present embodiment, as indicated by the curve of Fig. 2 (4), the differential value of the vicinity of the interface at the interface between the channel protective layer 2Q and the living (4) 18 is negative 辔. _ yue yue Ma Zheng, at the same time the difference in the differential value near the interface α is lxl 〇 2 〇 w U 'the threshold will not shift to a negative value' and can show good TFT Μ B ^ Λ c 1 will In addition, the long-term reliability of the transistor 10 is improved. -22-201218384 The method for manufacturing the transistor 10 of the present embodiment will be described based on Fig. 3 (a) to (g). For example, an alkali-free glass plate is prepared. Next, for example, pure water is used for 15 minutes in this order, and acetone is used for 15 minutes: the base 12 is ultrasonically washed using a pure 7jc 15" clock. It is introduced into the surface i 2a of the substrate 12. Using D (: magnetron sputtering method to form a molybdenum film (not shown) having a thickness of 4 〇 nm. Further, the DC magnetron sputtering method uses, for example, Ar gas as a sputtering gas, and introduces helium gas. The pressure at the time is 0.2 P a. Secondly, a photoresist film (not shown) is formed on the molybdenum film, and is used. The photolithography method is exposed to the desired jg! and is subjected to the enamel pattern, and the photoresist pattern is formed by development. Next, as the etching of the acid, the molybdenum film is etched, for example, using phosphorus nitrate water. 35, the photoresist is peeled off. Thus, as shown in Fig. 3 (4), a gate electrode made of molybdenum can be formed on the surface i2a of the substrate 12, and second, as shown in Fig. 3 (b), to cover the gate electrode. The method of 14 is to form a film (the working insulating film) 15 which is a gate insulating layer at a thickness of 200 nm on the entire surface 12a of the substrate 12, for example, the RF 贱 key method is used, for example, 2 is (4) and Ar gas and helium 2 gas are used as a sputtering gas. In this case, for example, the flow rate of A 4 〇 Sccm and the flow rate of 〇 2 gas is 4 5 seem, & The pressure is 〇16 Pa. ” Secondly, no atmospheric release, that is, no vacuum is broken, and a ruthenium film as the active layer 18 is formed on the surface 15a of the film 15 (for example, at a thickness of 5 〇 nm). The semiconductor film "7. The composition of the IGZO film 17 is, for example, InGaZn〇4. -23- 201218384 In the bonding method, a polycrystalline sintered body having a composition of InGaZn〇4 is used as a target, and Ar gas and A gas are used as a sputtering gas. At this time, the flow rate of Ar gas is 97 Sccm, and the flow rate of 〇2 gas is 4 "The pressure at which the claw, Ar gas, and helium gas are introduced is 〇37 Pa. Secondly, the atmosphere is not released, that is, the vacuum is not broken, and the surface 17a' of the igz diaphragm 17 is used, for example, at a thickness of 40 nm using the rf sputtering method. A Ga oxide film (second insulating film) 丨9 serving as the channel protective layer 20 is formed. Further, RF sputtering is performed using gallium oxide (Ga2〇3) as a target', and Ar gas and helium gas are used as a gas plating gas. For example, the flow rate of αγ gas is 97seem, the flow rate of 〇2 gas is 5.0seem, and the pressure at the time of introduction of Ar gas and 〇2 gas is 〇.4Pa. Thus, without releasing the atmosphere, that is, without breaking the vacuum, the 〇2 film 15, the IGZ0 film 17, and the Ga oxide film 19 are continuously formed on the substrate 2 U in accordance with the order thereof, as shown in Fig. 3(b). A laminate 23 composed of a yam film 1 5 IGZ yttrium film 17 and a Ga oxide film 19 was obtained. Next, as shown in Fig. 3(c), a photoresist film 40 is formed on the surface 19a of the Ga oxide film 19, for example. Then, by using the lithography method, at least a part of the channel region c (refer to the two first drawings) covering the IGZO film 17 in the photoresist film 40' becomes the pattern portion 42, and the other portion becomes the non-pattern portion 44. The photoresist film 40 is exposed to form the pattern portion 42 and the non-pattern portion 44. Next, the non-pattern portion 44 of the photoresist film 40 after the exposure is removed in the developing solution by using, for example, an aqueous solution of tetraammonium hydroxide as an alkaline solution, for example, Τ μ Α can be used. η 2.3 8 % (trade name, manufactured by Tama Chemical Industry Co., Ltd.). -24 - 201218384 In the present embodiment, when the non-pattern portion 44 is removed, since the Ga oxide film 19 can be dissolved in the alkaline solution, the pattern portion 42 is used as the mask instead of the pattern in the Ga oxide film 19. The oxide film IX under the portion and the non-pattern portion 44 are simultaneously removed by the alkaline solution, whereby the pattern portion 42 and the 〇3 oxide film under the pattern portion 42 remain. Subsequently, the pattern portion 42 is peeled off. Thereby, the channel protective layer 2A as shown in Fig. 3(d) can be formed. Thus, the development step of the pattern portion 42 for forming the photoresist film 4 and the etching step of the Ga oxide film 19 can be simultaneously performed in the same step. Further, the resist film may be formed into a pattern portion 'in a portion corresponding to the channel region C (see the second drawing) of the active layer 18 of the IGZ yttrium film 17, either positive or negative. In the case of a person, a photoresist film (not shown) is formed on the surface m of the IGZO film 17 and a photoresist pattern is formed using a lithography method, for example, the acid water is used to etch the IGZO film 17. Subsequently, the photoresist film was peeled off. Thereby, the active layer 18 as shown in Fig. 3(e) can be formed. g

Si. : The method of covering the surface of the channel protective layer 20 and the active I 18 forms a photoresist film (not shown) in the method of forming a photoresist pattern 15a, and uses lithography:: _ then, for example, using buffered hydrogen fluoride The acid (bUffered hydrofluoncacnd) will be etched with a 〇2 film 15 to expose the contact holes. Subsequently, the photoresist 4* electrode is taken as a film "forming contact:,: enough: into the insulating film 16. ^成... Figure (4) shows the gate as extremely shown in Figure 3 (f), covering the channel with the can wind in the active layer 1 8 0 I £ 1 V, θ 0 surface 18a and gate insulation The surface of i6-25-201218384 16a, for example, uses 0 (: magnetron sputtering method to "paw film 21" as a conductive film. X forms molybdenum, and DC magnetron sputtering is used, for example, to use dirty force. .2Pa is carried out. "After the age of the gas, and secondly, a photoresist film is formed on the surface 2la of the molybdenum film 21 (the lithography method is not used, for example, the Φ pole 22 which can be obtained by the first θ and the β cadence is obtained. And the pattern of the drain electrode 24 is exposed ': resist pattern. From the ride, to form the light second, for example, using phosphoric acid water as the acid etching solution, and the resist pattern is used as a mask to etch the molybdenum film 2 At the time, because of the use of Ga oxidized jinjin into the channel protective layer 20, Chuanfeitang, 诉 非 非 难以 难以 难以 难以 难以 难以 难以 难以 难以 难以 难以 难以 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其It is possible to prevent etching of a portion corresponding to the pass region C of the tunnel F 梡 4 in the active layer 2, and because The pole insulating layer H is formed by the field C · a , and is also formed using the S 〇 2 film, so that it is not etched. Thereby, as shown in FIG. 3 (G), it can be on the surface of the active layer 18 18a, the source channel 22 and the drain electrode 24 are formed by sandwiching the channel only. The electrode is coated, and after pre-baking, the acrylic resin film is formed by using a micro-shirt method. For example, it is post-baked and baked for 1 hour at a temperature of 1. Thus, the planarization layer 26 can be formed. As described above, the operation of the ^_τ is sufficient to form the transistor 10 shown in Fig. 1. Secondly, Covering the channel protective layer 2〇, the source electrode 22 and the drain electrode. J soil 'τ 偶 偶 1 . j 1 PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC PC ω ω ω ω ω ω ω ω ω ω ω ω ω ω The method 'for example, using a spin coater to the thickness of the claws JSR / 彐 ^ ^ -26-201218384 As described above, after the formation of the oxide semiconductor film constituting the active layer, the patterning becomes necessary after the atmospheric release Shape. At this time, because the active layer is exposed to the atmosphere, or is patterned It is exposed to an etching solution or the like. However, in the present embodiment, the Si〇2 film 15, the IGZ0 film 17 and the Ga emulsion film 19 are arranged on the substrate in accordance with the order without releasing the atmosphere, that is, without breaking the vacuum. The formation of 1 2 is continuous, and it is possible to manufacture the interface of the active layer 18 and the channel protective layer 20 without being exposed to the atmosphere. It is possible to suppress entry of moisture, oxygen, impurities, and the like into the active layer 18 and the channel protective layer 20. The interface can suppress the influence of moisture, oxygen, impurities, and the like in the active layer 18, and can suppress the displacement of the threshold. Thereby, the thin film transistor 10 having good characteristics can be formed with good reproducibility and high yield. Thus, the transistor 10 having excellent reliability can be obtained. Further, according to the manufacturing method of the transistor 10 of the present embodiment, as shown by the curve A shown in Figs. 2(a) and 2(b), the channel protective layer 20 (region and active layer 18 (hydrogen concentration in the region DO) , reducing the hydrogen concentration profile near the surface 1 8 a of the active layer 18 from the channel protective layer 2 〇 toward the active layer 18 and decreasing 'the vicinity of the interface α of the channel protective layer 20 and the active layer 18 ′ A hydrogen concentration profile having a minimum value of 1 and a maximum value of 2 is obtained. Further, the manufacturing method of the transistor 1 according to the present embodiment is as shown by the curve E of Fig. 2(c), in the channel protective layer 2 The differential value of the 'hydrogen concentration profile' near the interface α with the active layer 18 changes from negative to positive, and the difference in the differential value near the interface α is 1 χ 102 〇 or more. That is, 'in the second figure (c) The minimum value of the differential value near the interface α of the curve 77*, and the difference from the maximum value r 2 is lxl〇2〇 or more. -27- 201218384 Further, the manufacturing method of the transistor 1 according to the present embodiment, although There is no special step for adding hydrogen, and the hydrogen concentration in the active layer 18 can also be made 1 〇21 atoms/cm3 or more. Thus, in the present embodiment, the number of steps can be reduced, and the steps can be simplified. Thereby, the manufacturing cost of the transistor 1 can be reduced, and the transistor 10 can be inexpensive. Further, in the method of manufacturing the transistor 10 of the present embodiment, by using the channel protective layer 20 as a Ga oxide and removing the non-pattern portion of the photoresist film, it is possible to use an imaging solution of an alkaline solution. The Ga oxide film 19 other than the channel protective layer 20 is removed. Therefore, the step of removing the Ga oxide film 19 is not required. Thus, the number of steps can be further reduced, and the steps can be further simplified, and the manufacturing cost can be further reduced. Moreover, it is necessary to use hydrofluoric acid (hydrum flu〇ric acid) when using a SIN film or a Si〇2 film as a channel protective layer and attempting a wet type, but in this embodiment, since it is not necessary to use hydrofluoric acid, It is possible to form the channel protection layer 20 more safely. Eight, Shiben Shi---Post·...~Yi Yun Nai Ling,

(5) 2 films (i-th insulating film (1) (9) such as film (oxide semiconductor film) 17 with oxide film (second insulating film) 19, back pressure at film formation W = lower: water content at the time of film formation is reduced" For the active layer, the back pressure at the time of film formation is preferably 10x10-4 Pa or less. Moreover, the 'Ga oxide film (the second insulating film) makes the mixing ratio of argon gas 〇] 〇 / μ. From the squatting, it is better to use the milk wind in the present ~ ο·1. The above conditions are less than 10%. In the manufacturing method of the transistor 10 in the form of the A, the ugly occupation of the photoresist pattern is夂From the opening of the 2 large i-resist film, the formation of various films, and the flatness

In any case, the temperature is 2 a J I. In this way, since each step of -28-201218384 is performed at a temperature of 200 ° C or lower, for example, PET, PEN, PI, LCP, PES or the like can be used as the substrate. Since PEN, PI, LCP, and PES are flexible, a transistor can be obtained. Next, a second embodiment of the present invention will be described. Fig. 4 is a schematic cross-sectional view showing a second embodiment of the present invention. Further, in the present embodiment, the same configuration as that of the transistor 1 第 of the first embodiment is omitted, and detailed description thereof will be omitted. Compared with the transistor 1 表示 shown in Fig. 1, the fourth transistor 1 〇a is formed by the channel protective layer 28 and the active layer 18, and the channel region C is wider than the first one. The transistor 1 is represented by the same structure. The first transistor l〇a forms a source on the surface 16 a of the gate insulating layer 16 in such a manner as to cover the surface of the channel protective layer 28, because the channel protective layer 28 is in addition to the shape, and the channel protection of the state The layer 20 is the same 'so that the transistor 10a of the present embodiment is omitted, and the curve a shown by the first field, as shown in the second figure (a) and (b), the channel is in the region D1. And the active layer 18 (corresponding to the region D2) is reduced from the channel protective layer 28 toward the active layer 18, and the interface α between the sheath 28 and the active layer 18 is near, that is, the living surface is 18 a The nearby hydrogen concentration profile has a minimum value of 1 and further, in the transistor 1 〇a of the present embodiment, as shown by the curve E, the channel protective layer 28 and the active layer have low heat, and the PET, The structure of the flexible film transistor 1 is shown in the same figure as the same symbol, and the structure of the structure 4 shows a portion of the i-electrode 22 of 28 a. Description of the first embodiment *. The morphology of the same layer & layer 28 (the argon concentration of the phase, while the surface of the channel is 4, the maximum value of the surface of the layer 2 is cold 2. The interface of 18 of Figure 2 (c) is attached -29-201218384 near, hydrogen concentration profile The differential value is changed from negative to positive, and the difference in the differential value near the interface is 1×1 〇 2G or more. Moreover, the hydrogen concentration in the active layer 18 is l〇21 atoms/cm 3 or more. Since the transistor 10a has only the shape of the channel protective layer 28, the same effect as that of the transistor 10 of the first embodiment can be obtained. Therefore, the threshold of the transistor 10a of the present embodiment is limited. In the meantime, it is not necessary to shift to a negative value, and it has a good TFT characteristic and has high long-term reliability. Next, a manufacturing method of the first embodiment 〇a will be described. Fig. 5 (a) to (f) are displayed in the order of steps. A schematic cross-sectional view showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention. Further, in the method of manufacturing the transistor 10a, the first embodiment shown in Figs. 3(a) to 3(g) The manufacturing method of the transistor 10 of the form is the same, and the detailed description thereof is omitted. The manufacturing method of the transistor 1 〇a of the present embodiment is the same as that of the transistor 10 of the first embodiment except that the step of forming the channel protective layer 28 is different from that of the transistor 10 of the first embodiment. The manufacturing method is basically the same manufacturing method. In the present embodiment, the steps shown in Figs. 5(a) and 5(b) are based on the third embodiment (a) and (b) of the first embodiment. The steps shown in the same manner are the same, and the detailed description thereof will be omitted. Therefore, the procedure of Fig. 5(c) will be described. As shown in Fig. 5(c), the surface 19a of the Ga oxide film 19 is formed, for example. The photoresist film 40a. Then, using the lithography method, a protective layer 28 of substantially the same size as the active layer 18 is formed on the IGZO film 17, and is matched with the -30-201218384 active layer 18 &" Part 44:: square: the pattern portion is formed, and the other portion is ψ ^ 42a m , and the photoresist film 4〇a is exposed to form the pattern tea W Wa and the non-pattern portion 4 etch. 4Ga non-pattern _, in addition to the imaging winter H Schein oxidized tetramethylammonium solution as an alkaline solution

The base can be used, for example, TMAH 2.38% (trade name, manufactured by Tama Chemical Industry Co., Ltd.). (H the amine amine 1 Q form removes the non-pattern portion 44a because of Ga oxidation

Therefore, it is sufficient to dissolve in the alkaline solution. Therefore, in the Ga oxide film 19, FIG. A and °P42a are used as masks instead of the G a oxide limb 1 n / 4 under the pattern portion 44a, and the pattern is non-patterned. The portion 44a is simultaneously removed by the alkaline solution. The pattern portion 42a and the carrier film 19 are left under the pattern portion "a." The photoresist film can be either positive or negative as in the first embodiment. |J- 丨

The pattern portion 42a is not peeled off, and for example, the IGZO film 17 is etched using oxalic acid. After you •, the photoresist film 4〇a is peeled off. Thereby, the active layer 丨8 represented by the fifth = () is formed. Then, in the same manner as in the first embodiment, the contact and the hole are formed in the SiO 2 film 15, and the gate insulating film 16 as shown in Fig. 4 (4) is formed. Then, in the same manner as in the first embodiment, as shown in Fig. 5 (the hook surface is formed to cover the channel protective layer 28, the pin 21 is formed on the = surface 16a of the gate insulating layer 16 and then, as shown in Fig. (1) It is shown that the source electrode 22 and the drain electrode 4 are formed between the pass-through layer 12 and the drain electrode 4 is formed in the same manner as in the first embodiment to form a flattening layer or more. The transistor 1 〇a shown in Fig. 4. -31 - 201218384 The method of manufacturing the transistor 1 〇a of the present embodiment is different from the method of manufacturing the transistor 10 of the first embodiment. In the case of forming the size of the protective layer 28 and the formation of the active layer, the difference in the formation of the photoresist pattern is omitted, and the same effect as the method of manufacturing the transistor 10 of the first embodiment can be obtained. Therefore, in the present embodiment, the SiO2 film 15, the IGZ0 film 17, and the Ga oxide film 19 are continuously formed on the substrate 12 in accordance with the order without releasing the vacuum, that is, without breaking the vacuum, and moisture can be formed. &#市虱气, impurity, etc. into the active layer 18 The channel protective layer 2 8 == surface can suppress the moisture, oxygen, impurities, and the like in the active layer 丨8, and can suppress the displacement of the threshold value. Thereby, the reproducibility is good and the formation is high yield. Thin film transistor with good characteristics 1〇a. This kind of 1' can obtain a transistor with excellent reliability, 1 Oa. In the present embodiment, the concentration of hydrogen in the channel protective layer 28 and the active layer is It is also reduced from the channel protective layer 28 toward the active layer 丨8; in the vicinity of the interface between the channel protective layer 28 and the active layer 丨8, the hydrogen concentration profile of the vicinity of the surface l8a of the [Life® 1 main H] is also The second brother - ^ \ 〇) Similarly, the curve A has the same hydrogen concentration profile with a minimum value of 1 and a large value of 々2. . Further, in the present embodiment, similarly to the curve & shown in Fig. 2(c), the differential value of the hydrogen/length profile is negative near the interface between the channel protective layer 28 and the active layer 18. It becomes positive, and the difference in micro knife value near the interface is 丨x丨〇2〇 or more. That is, the difference between the differential value 7 1 and the maximum value 7 2 of the differential value near the interface is i χ J 〇 2 〇 or more. Further, according to the method for producing the transistor 丨〇a of the present embodiment, although the special step of adding hydrogen is not carried out at -32 to 201218384, the hydrogen 'length of the active layer can be 1 〇 21 atoms/cm 3 or more. . Thus, in this embodiment, the number of steps can be reduced, and the steps can be simplified. Thereby, the manufacturing cost of the transistor 10a can be reduced, and the transistor 1a can also be inexpensive. Further, in the method of manufacturing the transistor 丨〇a of the present embodiment, the channel protective layer 28 and the active layer 18 have the same shape, and the channel protective layer 28 and the layer 18 can be formed by the photoresist pattern formed by the gate mask. . Thereby, it is possible to reduce the number of masks necessary for forming the photoresist pattern, thereby reducing the cost and simplifying the steps. This also increases production efficiency. Further, in the present embodiment, as in the case of the i-th embodiment, the number of steps can be further reduced, and the number of steps can be further reduced, and the steps can be further reduced. manufacturing cost. Further, in the same manner as in the first embodiment of the present embodiment, it is necessary to use a hydrofluoric acid in the case of using a SIN film or Si〇2骐 as a protective layer and attempting wet etching. However, this embodiment also does not use Hydrofluoric acid can form the channel protective layer 28 more safely. Further, in the manufacturing step of the transistor 1a, any of the formation of the resist pattern of the photoresist film, the formation of various films, and the formation of the planarization layer 26 are also at a temperature of 2 〇〇 <> get on. In this manner, since the steps are all performed at a temperature of 200 ° C or lower, a substrate 12 having low heat resistance such as ρ Ετ can be used. Thereby, a flexible electric cover can be obtained. Next, a third embodiment of the present invention will be described. The shape in 1 8 can also be priced, and the amount of phase activity t can be used to remove. Because of the -, it is also compatible with the Daobao fluoric acid, light, and each step of the PEN k body. -33-201218384 The thin film transistor of the embodiment is denoted by the same reference numerals and the detailed description is omitted. Fig. 6 is a view showing the first mode of the present invention. Further, in the present embodiment, the same components as those of the transistor 10 of the first embodiment will be described in detail. The transistor 1〇b shown in Fig. 6 is generally referred to as a top gate top contact constructor. The transistor i〇b is in addition to the position 2 of the gate electrode 14 and the channel protective layer 20 and the active layer 18, and the source electrode, as compared to the transistor ίο of FIG. The position of the electrodeless electrode 24 is different from the upper and lower sides, and the other structures are the same as those of the transistor 10 shown in Fig. 1. The transistor i〇b as shown in Fig. 6 forms the active layer 18 on the surface 12a of the substrate 12. A channel protective layer 20 is formed on the surface i8a of the active layer 18. The source electrode 2 2 is formed on the surface i2a of the substrate 12 so as to cover the surface 18a of the active layer 18 and a portion of the surface 20a of the channel protective layer 20. Further, the drain electrode 24 which is paired with the source electrode 22 is disposed on the surface 12a of the substrate 12 and the source electrode 22 so as to cover a surface 18a of the active layer 18 and a portion of the surface 20a of the channel protective layer 2A. Formed in opposite directions. The insulating film 30 is formed on the substrate I so as to cover the channel protective layer 2A and the active layer 18, the source electrode 22, and the drain electrode 24. A gate electrode 14 is formed on the surface 3A of the insulating film 30. A planarization layer 26 is formed on the surface 30a of the insulating film 3A so as to cover the gate electrode 14. Further, the insulating film 30 is used to insulate the channel protective layer 2 and the active layer 18 and the source electrode 22 and the drain electrode 24 from the gate electrode 14. In the case of -34-201218384, the insulating film 30 is the same as the gate insulating layer 16 of the transistor 10 shown in Fig. 1, and detailed description thereof will be omitted. Similarly to the first embodiment, the transistor 1 Ob has the channel protection layer 20 (corresponding to the region D!) and the active layer 18 (corresponding to the curve A shown in Figs. 2(a) and 2(b). The concentration of hydrogen in the region D2) decreases from the channel protective layer 20 toward the active layer 18, while the vicinity of the interface between the channel protective layer 20 and the active layer 18, that is, near the surface 18 8 of the active layer 18. The hydrogen concentration profile has a minimum value of /5 1 and a maximum value of /3 2 . Further, in the transistor 1 Ob of the present embodiment, as shown by the curve E of Fig. 2(c), the differential value of the hydrogen concentration profile changes from negative to near the interface between the channel protective layer 20 and the active layer 18. Positive, the difference in differential values near the interface is 1 X 1 02 G or more. Further, the hydrogen concentration in the active layer 18 is 10 ato 21 atoms/cm 3 or more. Further, in the transistor 1 Ob of the present embodiment, the difference in the hydrogen concentration and the differential value in the vicinity of the interface is the same as that of the transistor 1 in the first embodiment, because of the structure of the active layer 18 and the channel protective layer 20. The same effects as those of the transistor 10 of the first embodiment can be obtained. Therefore, in the transistor 10b of the present embodiment, the threshold value is not shifted to a negative value, and the TFT characteristics are excellent and the long-term reliability is high. Next, a fourth embodiment will be described. Fig. 7 is a schematic cross-sectional view showing a thin film transistor of a fourth embodiment of the present invention. In the present embodiment, the same components as those of the transistor 1 〇b of the third embodiment shown in Fig. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. -35- 201218384 The transistor 1 〇c shown in Fig. 7 is different from the transistor 10b shown in Fig. 6, because the channel protection layer 28 and the active layer 18 are different in shape, and other structures are different. The same structure as the transistor 1 〇b shown in Fig. 6 is omitted, and detailed description thereof will be omitted. Further, the channel protective layer 28 is the same as the channel protective layer 20 of the third embodiment except for the shape. The transistor 10c of the present embodiment differs from the third embodiment only in the size of the channel protective layer 28. Therefore, in the present embodiment 10c, as in the third embodiment, as in the first embodiment, the channel protection layer 28 (corresponding to the curve A shown in Figs. 2(a) and 2(b) can be obtained. The concentration of hydrogen in the region D,) and the active layer 18 (corresponding to the region D2) decreases from the channel protective layer 28 toward the active layer 18, while the interface between the channel protective layer 28 and the active layer 18 is That is, the hydrogen concentration profile near the surface 18 8 of the active layer 18 has a minimum value of /5 1 and a maximum value of 2. Further, in the transistor 10c of the present embodiment, as shown by the curve E of Fig. 2(c), the differential value of the hydrogen concentration profile changes from negative to near the interface between the channel protective layer 28 and the active layer 18. Positive, the difference in differential values near the interface is 1 X 1 02G or more. Further, the hydrogen concentration in the active layer 18 is 10 ato 21 atoms/cm 3 or more. In the transistor 10c of the present embodiment, since the size of the channel protective layer 28 is different from that of the third embodiment, the same effects as those of the transistor 10 of the first embodiment can be obtained. Therefore, in the transistor 1 〇c of the present embodiment, the threshold value is not shifted to a negative value, and the TFT characteristics are excellent and the long-term reliability is high. Further, the transistor 10, 10a to 10C of any of the above embodiments can be used as a display device using a liquid crystal or an EL element, in particular, as a switching element or a driving element of an FPD. Further, the image display device using the transistor 10, 1 Oa to 1 Oc according to any of the above embodiments can be applied to a mobile phone display, a personal digital assistant (PDA: Personal Digital Assistant), a computer display, a car information display, TV monitors or a wide range of areas of general illumination. Further, the substrate of the transistors 10, 10a to 10c of any of the above embodiments can be applied to a 1C card or an ID tag or the like as a flexible substrate such as a plastic film. The invention is essentially as described above. Although the thin film transistor of the present invention and the method for producing the same are described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. [Example 1] Hereinafter, examples of the film transistor of the present invention will be specifically described. In the present embodiment, the electromorph according to Example 1 shown below and the transistor of Comparative Example 1 were produced, and the evaluation of the transistor of each Example 1 and the transistor of Comparative Example 1 with time was performed. The transistor of the first embodiment has the same structure as the transistor 10 of the first embodiment shown in Fig. 1, and the transistor of the first embodiment shown in Figs. 3(a) to 3(g) is used. The manufacturer of the 10 0 manufacturing method. The transistor of Comparative Example 1 has the same structure as that of the transistor 100 shown in Fig. 8(g), and is produced by the manufacturing method -37-201218384 shown in Figs. 8(a) to 8(g). Also, + knot. Door _ The transistor 100 shown in Fig. 8(g) and the Thunder mail/, shown in Fig. i. In the same configuration as in the manufacturing method, the electric Japanese and Japanese sisters 10 are made of an alkali-free glass on the substrate i 2 . As shown in Fig. 3(a), the gate electrode 14 is formed on the substrate 12 as follows. First, 'by dc magnetron sputtering method, the two emulsions are made of money, and the flow rate of Ar gas is (5) coffee, ^:, the pressure at the time of entering is 2 Pa, and the thickness is formed on the substrate 12. 1 molybdenum film. Then, the molybdenum film was formed into a photoresist 2 by a lithography method, and a molybdenum film was etched to form a gate using a etchant TSL (manufactured by Lin Chun Pharmaceutical Co., Ltd.) with a liquid helium of 25 C. The electrode is 丨4. The Si〇2 film 15 as the gate insulating layer 丨6 shown in FIG. 3(b) is formed by covering the gate electrode 丨4 with a thickness of 2〇〇ηΠ1 by rf sputtering. The surface 12a of the substrate 12 is comprehensive. In addition, the RF sputtering method uses Sl2 as a target, and the flow rate of the & gas is 4 (seven) ccm, the flow of the helium gas is set to 45 sccm, and the pressure at which the gas and the helium gas are introduced is 〇. 16Pa is carried out. The IGZO film 17 of the field active layer 18 shown in Fig. 3) is formed by DC sputtering on the surface 15a of the 81〇2 film 15 at a thickness of 5 〇 nm without the release of the atmosphere. Further, in the DC sputtering, a polycrystalline sintered body having a composition of I_nGaZn〇4 is used as a standard, and a flow rate of the helium gas is 97 SCCm, a flow rate of the A gas is 4 2 sccm, and Ar gas and helium gas are introduced. The pressure at the time was 0.37 Pa. Next, the surface of the lGz ruthenium film 17 is not subjected to RF sputtering at a thickness of 4 〇 nm using a thickness of 4 〇 nm to form a Ga-oxidation of the channel protective layer 20 as shown in Fig. 3(b). Film 19. Further, the rf splash bond uses gallium oxide (Ga2〇3) as the target 'and the flow rate of the Ar gas is 97seem, the flow rate of the helium gas is 5.0 sccm, and the pressure at which the Ar gas and the 02 gas are introduced is 0.4. Pa is carried out. In this manner, the layered body 23 shown in Fig. 3(b) is formed without releasing the atmosphere. Next, as shown in Fig. 3(c), a photoresist film 40 is formed on the surface 19a of the Ga oxide film 19. Then, exposure is performed so as to form the pattern portion 42 and the non-pattern portion 44 by the lithography method. Then, the non-pattern portion 44 of the exposed photoresist film 40 is removed by using TMAH 2.3 8% (trade name, manufactured by Tama Chemical Co., Ltd.), and then the pattern portion 42 is removed to form the third image (d). The channel protection layer 20 is shown. Next, a photoresist pattern is formed on the surface 17a of the IGZO film 17 by lithography. Then, IGZO film 17 was etched at a liquid temperature of 35 ° C using oxalic acid water (IT〇_〇6N (manufactured by Kanto Chemical Co., Ltd.) to form active layer 18 shown in Fig. 3(e). Next, a photoresist film (not shown) is formed on the surface 15a of the Si〇2 film 15 so as to cover the channel protective layer 20 and the active layer 18, and a photoresist pattern is formed by photolithography. Then, the HF concentration obtained by diluting buffered hydrofluoric acid with water was 6 mass%, and the liquid temperature was 25. (: The Si〇2 film 15 is etched to form a contact hole for gate electrode extraction. Thus, the gate insulating film 丨6 shown in Fig. 3(e) is formed. Next, 'the way to cover the channel protective layer 20 On the surface 18a of the active layer 18 and the surface 16a of the gate insulating layer 16, a molybdenum film represented by Fig. 3 (1) is formed by a DC magnetron sputtering method at a thickness of 100 nm, and a 39-201218384 DC magnetron is used. The sputtering method is such that ^ # Λ 15sc is a sputtering gas, and the Ar gas is captured by 15 sccm, and Ar gas is introduced into the crucible from the mine A, and the pressure at the time of entering is 0.2 Pa. A pattern of 2 p p is blocked on the surface of the key film 21. Light is formed using lithography

It is a human, using the rhyme of acid (M sauce w, system, V 〇 using the surname TSL (Lin Chun Pharmaceutical Industry Co., Ltd.)), with a liquid temperature of 25 〇Γ base such as flute 3... The pin film 21 is etched to form the source electrode 22 and the electrodeless electrode shown in Fig. 3(g). Next, the channel protective layer 2, the source electrode 22, and the drain electrode 24 are used. Rotating the coating. The coated state was coated with PC-405G manufactured by JSR Co., Ltd. at a thickness of 1.5/zm, and was cooled and pre-baked. Then, the acrylic film was patterned using lithography U. The film was aged for 18 hours and then baked for 1 hour to form a planarization layer 26 (see Fig. i). The transistor of Example 1 was formed as described above. With respect to the transistor of Example 1, when the hydrogen concentration was measured by SIMS, 旎The result of obtaining the curve A and the curve E shown in the above FIGS. 2(a) to 2(c) is compared with the method of manufacturing the transistor of the above-described embodiment, and the method for producing the transistor of the comparative example 1 is formed. 8 Figure 0) shows the gate electrode 14 and forms a Si〇2 film 5 as a gate insulating layer ,6, and then, to no violence The step of forming the IGZ ruthenium film 17 as the active layer 18 continuously in the atmosphere is the same as that of the transistor of the embodiment i, and detailed description thereof will be omitted. The transistor of Comparative Example 1 is used. The manufacturing method is followed by forming a photoresist pattern by using a lithography method on the surface of the IGz film ί 7 , and then using a HF concentration of the buffered hydrofluoric acid diluted with water to 6 mass % - 40-201218384 'The gate electrode insulating film 16 as shown in Fig. 8(b) is formed by etching the S i Ο 2 film 1 5 I at a liquid temperature of 2 5 ° C. Next, 'the surface 17a of the IGZO film 17 'The photoresist pattern was formed by the lithography method. Then, the IGZO film 17 1 was inscribed at a liquid temperature of 35 ° C using oxalic acid water (ITO-06N (manufactured by Kanto Chemical Co., Ltd.)) to form an image (8). The active layer 18 is shown. Next, as shown in Fig. 8(c), the surface 16a of the gate insulating film 16 is formed as a channel at a thickness of 40 nm by RF sputtering in such a manner as to cover the active layer 18. The protective layer 2 is a Ga oxide film 19. The RF deposition method uses gallium oxide (Ga2〇3) as a target, and the flow rate of the Ar gas is 97 sc. The pressure of 〇2 gas is 5.0 sccm, and the pressure at the time of introduction of Ar gas and 〇2 gas is 〇4 Pa. Next, 'Ga is oxidized by the same method as the method for producing a transistor of Example 1. The film 19 is processed to form the active layer 20 as shown in Fig. 8(d). Next, 'the molybdenum film 21 shown in Fig. 8(e) is formed in the same manner as the method for producing the transistor of the first embodiment. Then, the source electrode 22 and the drain electrode 24 shown in Fig. 8 are formed.

Then, in the same manner as in the method of producing a transistor of the first embodiment, the planarization layer 26 shown in Fig. 8(g) is formed. Thus, the transistor of Comparative Example 1 was obtained. With respect to the transistor of Comparative Example 1, when the hydrogen concentration was measured by SIMS, the results of the curve B and the curve F shown in Figs. 2(a) to 2(c) above were obtained. For the transistor of Example 1 and the transistor of Comparative Example 1, the initial value (initial Vth) at the initial stage of measurement was measured. Subsequently, the transistors of the transistor-41 - 201218384 of the first embodiment and the transistor of the comparative example 1 were each stored in a desiccator (2rc, relative humidity of 60%), and the threshold value and "solid moon" after 2 weeks were each measured. The subsequent limit value. The measurement results of the above-mentioned thresholds are shown in the following table and the initial threshold (initial grain) indicated in Table 1 below is 9 points in 100 mm □, and Vg is made. (gate voltage) is the average of -1〇v~ values.

Vds (source-drain voltage) is 1〇v - 15V and is obtained by scanning. The threshold after 2 weeks and the threshold after 1 month are also shown in Table 1 below. For 9 points in 1〇〇mm□, Vds (source no-electrode) is 1〇v and Vg (question voltage) is -ι〇ν~1 5 V and is scanned. The average of the values. [Table 1]

-1.3V -4.3V __ After 2 weeks 1 month later, as shown in Table 1 above,

-1.3V -5.lv The electro-crystalline system of Example 1 has a small change in the threshold value after 1 month of jade and has high long-term reliability. On the other hand, the change in the threshold value of the electro-crystalline system of the comparative example is large, and the time passes through the same period, and the threshold value is shifted to the negative side, and the long-term reliability is low. This is considered to be because the electromorphic system of the comparative example is different from the crystal of the first embodiment in that it does not continuously form an IGZO film as an active layer and a GA oxide ruthenium as a channel protective layer without breaking the vacuum, resulting in contamination. The impurities are mixed into the surface of the active layer. '42-201218384 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a thin film transistor according to a first embodiment of the present invention. Fig. 2(a) is a graph showing the distribution of hydrogen concentration in the gate insulating layer, the active layer, and the channel protective layer by using the hydrogen concentration on the vertical axis and the depth on the horizontal axis, and (b) showing the second figure. (a) is an enlarged chart of important parts, and (c) is a graph showing the differential value of the curve in Fig. 2(b). Fig. 3 (a) to (g) are schematic cross-sectional views showing a method of manufacturing a thin film transistor according to a first embodiment of the present invention in order of steps. Fig. 4 is a schematic cross-sectional view showing a thin film transistor of a second embodiment of the present invention. Fig. 5 (a) to (f) are schematic cross-sectional views showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention in order of steps. Fig. 6 is a schematic cross-sectional view showing a thin film transistor of a third embodiment of the present invention. Fig. 7 is a schematic cross-sectional view showing a thin film transistor of a fourth embodiment of the present invention. Fig. 8 (a) to (g) are schematic cross-sectional views showing a method of manufacturing the thin film transistor of Comparative Example 1 of the present invention in order of steps. [Major component symbol description] 10, 10a, 10b, 10c, 100 Thin film transistor (transistor) 12 Substrate 12a Substrate surface 14 Gate electrode 15 Si02 film-43- 201218384 15a Surface of Si02 film 16 Gate insulating film 16a Surface of gate insulating film 17 IZGO film 17a Surface of IZGO film 18 Active layer 18a Surface of active layer 19 Ga oxide film 19a Surface 20 of Ga oxide film 20 Channel protective layer 20a' 28a Surface 22 of channel protective layer Source Electrode electrode 23 Laminated body 24 Bipolar electrode 26 Flattening layer 30 Insulating film 30a Surface of insulating film 40 Photoresist film 40a Surface 42 of resist film Pattern portion 42a Surface portion of pattern portion Non-pattern portion 44 a Surface of non-pattern portion C channel area -44-

Claims (1)

201218384 VII. Patent application scope: 1 · A method for manufacturing a special film transistor, which is provided with at least a gate on the substrate, a pole, a gate insulating layer, and an active layer functioning as a channel layer, 1) Ijjt Λ /L « ^ * I · Channel protective layer, source electrode and immersed in the channel region of the green layer;) 3⁄4 & A, U pole, characterized by: forming the gate electrode on the substrate a step of forming a first insulating film on the substrate and forming an oxide semiconductor film on the insulating film and forming a second insulating layer on the insulating film a step of forming a laminate comprising the first insulating film and the oxide semiconductor film; the conductor film and the second insulating film and the second insulating film of the laminate; The steps of patterning and semi-insulating the insulating layer and the channel protective layer: the front electrode forms the source electrode and the front electrode, and the steps of meaning, +. lean τ and the electrode The first insulation film, the aforementioned oxidation township, The insulating film is formed by forming the channel protective layer, the active layer and the pre-T method without exposing the atmosphere to the atmosphere (4) and the second < 4 film transistor, and the step of the layer is: The first insulating layer of the thermal insulating m_layer is patterned to form the channel protective layer. The insulating film is patterned to form the gate. The first insulating semiconductor film is patterned to form i and 曰. And the steps of the above-mentioned 3_ as described in the scope of the patent application " 'The film-seeking transistor; the raw + t forming the source electrode and the front enamel method, the step of attacking the electrode, the device -45-201218384 Preparation: forming a conductive film on the aforementioned substrate and A step of forming a photoresist pattern on the conductive film and using the channel protective layer as an etching stopper, and etching the conductive surface using an etching solution of an acid. 4. The method of producing a thin film transistor according to the first aspect of the invention, wherein the first insulating film, the oxide semiconductor film, and the second insulating film are formed by a sputtering method. 5. The method of producing a thin film transistor according to the fourth aspect of the invention, wherein the first insulating film, the oxide semiconductor film, and the second insulating film are formed at a back pressure of 1 〇 x 1 〇 4 p a or less. The method for producing a thin film transistor according to the fourth aspect of the invention, wherein the second insulating film is formed under a condition that a mixing ratio of xenon to argon is 〇 1% or more and less than 10%. The method for producing a thin film transistor according to any one of claims 2 to 6, wherein the second insulating film is composed of an oxide film of Ga, and the step of forming the channel protective layer is a step of forming an oxide film of the above & a step of forming a photoresist f on the oxide film of Ga; and causing at least one of the channels in the channel region of the photoresist film to become a pattern and making other portions non- a step of patterning; and a step of removing the non-pattern portion by using the test solution to form a pattern; A, when the non-pattern portion is removed in the pattern forming step, as described below, the non-pattern portion The oxide film system of Ga is described as being removed by the alkali cold liquid to form the channel protective layer. -46- 201218384 8 _ - A thin film transistor which is provided with at least a positive electrode on the substrate, a gate insulating layer 'active layer of the function of the channel protective layer, and channel protection covering the channel region of the active layer a layer, a source, a pole and a cathode: an electrode, wherein the channel protective layer is formed on the active layer, and the channel protection and the first aspect of the active layer β are from the channel protective layer toward the active layer. Decrease, and the pin, +.4 ^ 'the hydrogen channel concentration of the channel protection layer and the aforementioned active layer near the interface has a minimum value and a maximum value' at the boundary between the channel protection layer and the aforementioned active layer _ ^ ^ In the vicinity of the surface, the differential value of the hydrogen concentration profile changes from negative to positive, and the difference of the differential value in the vicinity of the interface is more than 1Χ1〇Μ. 9_The thin film transistor of claim 8 is Wherein the aforementioned hydrogen concentration in the active layer is 1 〇 21 atoms/cm 3 or more. 1 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The protective layer is interposed to form the S electrode and the drain electrode. A thin film transistor is used as a main component. The active layer is an amorphous semiconductor such as the first layer of the patent application range containing In, Ga and The eleventh thin film transistor is composed of the above-mentioned active and amorphous oxide semiconductor of Zn.