201217802 六、發明說明： 【發明所屬气技術部域】 技術領域 本發明係有關於—種燒機裝置、燒機系統、燒機裝置 之控制方法及燒機系统之控制方法。 L· ^ 背景技術 可進订使電子零件等半導體裝置之早期瑕疲明顯並進 料期故障品之去除之―測試之-種之燒機(B·刚 又之#置已知有燒機裝置。上述燒機裝置係半導體測試 裝置之-種’可將裝&有複數受測元件(Deviee Under 丁⑻) 之半導體裝置（諸如NAND型快閃記憶體）之預燒板收置於 燒機裝置内’並對元件施加電壓而賦與電應力，且加 熱怪溫槽内部之空氣而賦與預定溫度之熱應力，藉此而使 早期瑕㈣顯。又’上述燒機測試中，係對受測元件供給 預定之測賴號’而進行㈣元件之動作職，並進行測 試受測兀件是否正常動作之功❹彳試。魏賴包含複數 測試。 上述燒機裝置中’將進行數小時至數十小時之長時間 之燒機測試’故為提昇測試效率’―般係將複數受測元件 裝設於丨U燒板上，錄她之上述賴板純收置於燒 機裝置内，而進行燒_試（參照諸如專利文獻i :特開 2005-265665號公報）。 進行燒機測試之功能測試時所需之測試型樣資料係由 201217802 ，機裝置所生成，再送至預燒板上㈣設之受測元件。其 ά t基於上述測試^樣資料而使受測元件進行動作，並由 …為裝置自預燒板讀取其動作結果之來自受測元件之輸出 ^k機I置則將比較讀取之輸出訊號與理論值，而判 疋又測讀疋否正常動作。判定結果將顯示諸如受測元件 過功n以未通過，上述狀結果將依序作為測試 。果而儲存於燒機裝置内之記憶體。上述判定結果將顯示 ;諸士叹於燒機裝置之顯示器作為測試結果。 為降低成本，燒機裝置與預燒板之間之訊號線數量有 限因此’無法對搭載於1片預燒板上之全部受測元件同時 進仃功故而’將丨片預燒板上搭載之複數受測元件 依預疋數之㈣it件加以⑽構成複數群組，並依 群組單位依序對受測元件供給測試型樣資料，並由燒機農 ，讀取來自受測it件之輸出訊號而進行動作判定並儲存判 疋、’、口果。亦即’依序切換各群組而讀取來自受測元件之輸 出訊號以進行功能測試。 具體而言’燒機裝置係朝預燒板供給元件選擇訊號並 藉元件選擇訊Μ擇將㈣進行魏測試之狀數之受測 元件而構成上料^其次，燒齡㈣自ALPG(演算法 型樣產生器）等朝選出之複數受測元件供給同—測試型樣 資料’而同時進行功能測試。 另’燒機裝置可能諸如先進行接觸測試作為早期測 武’再進行功能測試。功能測試為提昇測試精度，而構成 對在功能測試所包含之某測試中暫定為有瑕疵之受測元件 201217802 重複至少1次以上相同之測試至判定為無瑕疵為止。其次，201217802 VI. Description of the Invention: [Technical Field of the Invention] Technical Field The present invention relates to a burning apparatus, a burning system, a control method of a burning apparatus, and a control method of a burning system. L· ^ Background Art It is possible to order a "burning machine" for the early detection of a semiconductor device such as an electronic component and the removal of a defective product during the feeding period (B. The above-mentioned burning device is a type of semiconductor testing device that can be used to mount a pre-burning plate of a semiconductor device (such as a NAND type flash memory) having a plurality of devices under test (Deviee Under D (8)) in a burning device. Internally' applies a voltage to the component to impart electrical stress, and heats the air inside the strange temperature bath to impart a thermal stress at a predetermined temperature, thereby making the early 瑕 (4) visible. The measuring component supplies the predetermined measuring number 'and performs the action of the component (4), and performs the test of whether the tested component is in normal operation. Wei Lai includes the plural test. The above burning device will be carried out for several hours to The tens of hours of burning machine test 'so it is to improve the test efficiency' - the general test unit is installed on the 丨U burning board, recording her above-mentioned Lai board purely placed in the burning machine, and Perform a burning test (refer to, for example, patent document i : JP-A-2005-265665. The test pattern data required for the functional test of the burn-in test is generated by the device of 201217802 and sent to the device under test on the pre-burning plate (4). Based on the above test data, the device under test is operated, and the output from the device under test is read by the device from the pre-burning plate, and the output signal and theory are compared. The value is judged and the test is performed normally. The result of the judgment will show that the measured component is not passed, and the above result will be used as a test. The memory stored in the burning device is the above. The judgment result will be displayed; Zhu Shi sighs the display of the burning machine as the test result. In order to reduce the cost, the number of signal lines between the burning device and the pre-burning plate is limited, so it is impossible to mount all of the pre-burning plates. At the same time, the device under test is subjected to the test and the plurality of devices under test on the enamel pre-burning plate are formed into a plurality of groups according to the number of pre-numbers (4), and the test components are sequentially supplied to the device under test according to the group unit. Sample information, By burning the machine, reading the output signal from the tested piece to determine the action and storing the judgment, ', the fruit. That is, 'switching the groups sequentially and reading the output signal from the device under test to perform Functional test. Specifically, the 'burning machine device' supplies the component selection signal to the pre-burning plate and selects the component to be tested by the component selection signal (4) to form the material to be tested. Secondly, the burning age (4) from the ALPG (Algorithm model generator), etc., to supply the same test-type data to the selected plurality of tested components while performing functional tests. Another 'burning device may be used for first contact test as early measurement' and then functional test The functional test is to improve the test accuracy, and constitutes the test of the test element 201217802 which is tentatively determined to be flawed in the test included in the functional test, and repeats the test at least one time until it is determined to be innocent. Secondly,
相同測試中重複判定為有瑕疵之受測元件’則就上述測試 最終加以判定為有瑕疵。 K 在此’接觸測試結果為有瑕疵之受測元件在次一功能 測試亦判定為有瑕疵之可能性極高。接觸測試中被判定有 瑕疵之受測元件於功能測試中亦被判定為有瑕疵時，將對 該受測元件如上述般重複進行相同測試，故功能蜊試將需 時較長。因此，可謂宜將上述受測元件排除於測試對 外，以整體縮短燒機測試時間。 之 然而，習知之燒機裝置係自iSALPG朝複數受測_ 供給同—測試型樣資料，故無法藉控制測試型樣資料&件 任意之受測元件排除於測試對象之外，而成問題。將 【先行技術文獻】 【專利文獻】 【專利文獻1】特開2005-265665號公報 【發明内容】 發明概要 發明欲解決之課題 本發明可提供一種可藉簡單之構造將任意之受 排除於測試對象之外之燒機裝置、燒機系統、燒機牛 控制方法及燒機系統之控制方法。 用以欲解決課題之手段 為解決上述問題，本發明之燒機裝置可供裝設有 受測元件之職板插人，並對前述複數受測細進行徒機 201217802 1八乙3有.元件選擇訊號輸出電路，可對前述預燒 ^輪出用於自前述複數受測元件中選出將進行功能測試之 =測几件之元件選擇訊號；及，測試型樣輸出電路，可對 =預燒板輸出用於對將進行前述功㈣m之受測元件供 ”。之測式型樣資料；前述元件選擇訊號輸出電路包含儲存 有屏蔽設定資料之屏蔽設定記《，而可屏蔽前述元件選 擇訊號1使前述屏蔽設定資料所蚊之受測元件不被選 為將進行前述功能測試之受測元件。 一又，本發明亦可進而包含：接觸測試執行電路，可在 前述功能測試之前，對前述預燒板輸出接觸測試用訊號， 而對已裝設於前述職板上之前述魏受測元件執行用於 確認其電性連接之接觸職；料電路，可讀取來自已接 收前述接觸職用訊號之前述各受測元件之輸出訊號，而 判定所讀取之輸出訊號是讀理論值_致並輸出接觸測試 判定結果；賴結果記_，可記錄料接_試判定結 果作為接_m結果；&，屏蔽設定電路，可狀前述屏 蔽設定資料以自前述複數受測元件中特定前述接觸測試結 果為有瑕疵者。 又，亦可使前述判定電路讀取來自已接收前述測試型 樣資料之前述各受測元件之輸㈣號，而狀所讀取之輸 出訊號是否與理論值-致並輸◎彳定結果，前述 測試結果記錄㈣靖前述魏㈣料縣作為功能測 試結果，歧«設;t電路贱定前述懸設定資料以自 前述複較取㈣狀料魏辑料翁瑕疲者。 201217802 又，本發明亦可進而包含：判定電路，可讀取來自已 接收前述測試型樣資料之前述各受測元件之輸出訊號，而 判定所讀取之輸出訊號是否與理論值一致並輸出功能測試 判定結果；測試結果記錄部，可記錄前述功能測試判定結 果作為功能測試結果；及，屏蔽設定電路，可設定前述屏 蔽設定資料以自前述複數受測元件中特定前述功能測試結 果為有瑕疵者。 又，前述功能測試亦可包含複數測試，本裝置亦可進 而包含測試順序控制電路，其可控制前述元件選擇訊號輸 出電路、前述測試型樣輸出電路及前述判定電路，而將前 述預燒板上所裝設之前述複數受測元件依預定數之受測元 件加以個別區分，藉此構成複數群組，並按群組單位依序 對前述受測元件進行前述功能測試所包含之預定測試， 且，對於前述預定測試中判定為有瑕疵之前述受測元件重 複相同之測試至少1次以上至判定為無瑕疵為止。 又，亦可使前述受測元件係NAND型快閃記憶體，前 述元件選擇訊號所選出之將進行前述功能測試之受測元件 則允許寫入，前述測試型樣資料則寫入已允許寫入之前述 受測元件。 本發明之燒機裝置之控制方法中，燒機裝置可供裝設 有複數受測元件之預燒板插入，並對前述複數受測元件進 行燒機測試，本方法則包含以下步驟：對前述預燒板輸出 用於自前述複數受測元件中選出將進行功能測試之受測元 件之元件選擇訊號；及，對前述預燒板輸出用於對將進行 201217802 前述功能測試之受測元件供給之測試型樣資料且，屏1 前述元件選擇，以使屏蔽狀賴㈣定之受測元二 不被選為將進行前述功能測試之受測元件。 本發明之燒機系統包含有：預燒板，可裝設複數受測 元件；及，燒機裝置，可供前述職板插人，而對前述複 數受測元件進行燒機測試；前述燒機裝置則包含：元件選 擇訊號輸tb電路’可對前述聽板輸㈣於自前述複數= 測7L件中選出將進行功能測試之受測元件之元件選擇訊 號；及，測試型樣輸出電路，可對前述職板輸出用於對 將進行前述功能測試之受測元件供給之測試型樣資料； 而，前述元件選擇訊號輸出電路包含儲存有屏蔽設定資料 之屏蔽設定記憶體，而可屏蔽前述元件選擇訊號，以使前 述屏蔽設定資料所特定之受測元件不被選為將進行前述功 能測試之受測元件。 本發明之燒機系統之控制方法中，燒機系統包含有： 預燒板，可裝設複數受測元件；及，燒機裝置，可供前述 預燒板插入，而對前述複數受測元件進行燒機測試；本方 法則包含以下步驟：對前述預燒板輸出用於自前述複數受 測元件中選出將進行功能測試之受測元件之元件選擇訊 號；及，對前述預燒板輸出用於對將進行前述功能測試之 受測元件供給之測試型樣資料；且，屏蔽前述元件選擇訊 號，以使屏蔽設定資料所特定之受測元件不被選為將進行 前述功能測試之受測元件。 圖式簡單說明 201217802 第1圖係本發明一實施例之燒機系統之燒機裝置之整 體正面圖。 第2圖係顯示第1圖之燒機裝置中收置有預燒板之狀態 下之内部構造之一例之正面配置圖。 第3圖係顯不第1圖之燒機裝置中，用於在燒機裝置與 受測元件之間交換控制訊號及輸出訊號之内部構造之一例 之功此區圖。 第4圖係本發明一實施例之預燒板之平面配置圖。 第5圖係顯示本發明一實施例之測試控制裝置之内部 構造之一例之功能區圖。 第6圖係顯示本發明一實施例之元件選擇訊號輸出電 路之内部構造之一例之功能區圖。 第7圖係說明本發明一實施例之燒機系統所執行之燒 機測試之動作之流程圖。 第8圖係說明本發明一實施例之變形例之燒機系統所 執行之燒機測試之功能測試動作之流程圖。 【實施*方式】 用以實施發明之形態 以下，參照圖示說明本發明之實施例。另，以下所說 明之實施例並非用以限定本發明之技術範圍者。 第1圖係本發明一實施例之燒機裝置10之整體正面 圖，顯示了門板20已關閉之狀態。第2圖係說明燒機裝置1〇 之内部構造之要部之正面配置圖，顯示了對燒機裝置1〇插 入預燒板BIB後之狀態。該等第丨及第2圖所示之燒機裝置i 〇 201217802 係半導體測試裝置之一種，而由燒機裝置10與預燒板BIB 構成本實施例之燒機系統。 如該等第1及第2圖所示，本實施例之燒機裝置10内部 藉隔熱板30所區隔之空間而形成有空室40。該空室40内部 可收置1或複數片之預燒板BIB。 本實施例中，並如第2圖所示，就各載架CR於空室40 内收置預燒板BIB。即，各載架CR形成有用以支持預燒板 BIB之凹槽50 ’在預燒板bIB已插入上述凹槽50之狀態下， 可對空室40收置載架CR。本實施例中，構成可對1載架CR 插入15片預燒板BIB。 又，本實施例中，構成可於空室40内收置4台載架CR。 因此，藉將4台載架CR收置於空室40内，即可將總計60片 之預燒板BIB收置於空室40内。但，該空室40内可收置之載 架CR之台數及配置、載架CR内之預燒板BIB之片數及配置 可任意加以變更。 進而，亦可不使用載架CR，而直接將預燒板BIB收置 於空室40内。此時，將於空室40内形成凹槽50，而對上述 凹槽50直接插入預燒板BIB。 如第1圖所示，上述燒機裝置10設有2片門板20，藉使 門板20呈開啓狀態，則可對空室40進行載架CR之置入取 出。又，上述門板20亦裝設有隔熱材，使門板20呈關閉狀 態’即構成與周圍隔熱之空間之空室40。 進而，如第2圖所示，本實施例之燒機裝置1〇設有加熱 器60與冷卻單元70。又，空室40内設有延伸於其左側、上 10 201217802 側、右側之空氣循環管道DT，藉設於該空氣循環管道DT 之風扇80即可使空氣循環管道DT内之空氣循環，而構成可 循環、攪拌空氣以使空室内之溫度均一。 冷卻單元70係由2台之冷卻壓縮機72與2台之熱交換器 74所構成。本實施例中，上述冷卻單元70係採用使用冷媒 之冷卻方式。冷卻壓縮機72係可使冷媒循環之壓縮機，熱 交換器74係可與空室40内部之空氣交換冷媒之冷熱之交換 器。2台熱交換器74均設於空氣循環管道DT内。因此，藉 風扇80使空氣循環，即可使循環之空氣藉熱交換器74而冷 卻，並降低空室40内部之溫度。 又，加熱器60係由諸如電熱加熱器所構成，而構成對 加熱器60供電即可發熱。在加熱器60已發熱之狀態下，使 空氣循環管道DT内之空氣循環，即可提高空室40内之空氣 溫度。 另，燒機裝置10之右側設有控制部CL。該控制部CL將 依循預設之設定及順序而控制上述燒機裝置10，並進行燒 機測試。本實施例中，尤其在燒機測試時將控制加熱器60 及冷卻單元70,而使預燒板BIB周圍之溫度形成使用者等所 設定之目標溫度。 第3圖係顯示用於在燒機裝置10與受測元件之間交換 必要之控制訊號及輸出訊號之内部構造之一例之功能區 圖。如該第3圖所示，燒機裝置10設有測試控制裝置100、 緩衝板110、驅動板120、延伸板130。該等測試控制裝置 100、緩衝板110係諸如設於控制部CL内部，驅動板120與延 201217802 伸板130則設於空室40内。 測試控制裝置1〇〇可進行上述燒機裝置10所進行之燒 機測試之整體控制。依循該測試控制裝置1〇〇之控制，而執 行燒機測試。燒機測試之執行所需之控制訊號則經作為輸 出緩衝區之緩衝板11〇而輸出至複數之驅動板120。 驅動板120與延伸板13〇則於空室40内對應各凹槽50而 配設。即，本實施例中，對應1片預燒板BIB設有^组之驅動 板120與延伸板13〇。因此，第1及第2圖所示之燒機裝置1〇 中’設有60組之驅動板120與延伸板130。供入驅動板120之 控制訊號則經延伸板13〇而最終送入預燒板BIB。 反之’預燒板BIB所輸出之測試結果之相關資料等之輸 出訊號則經延伸板13〇、驅動板120及緩衝板11〇而輸入測試 控制裝置100。藉此，測試控制裝置100即可取得各種測試 結果之相關資料。 第4圖係顯示本實施例之預燒板bIB之平面配置之一例 者。如該第4圖所示，預燒板BIB之插入方向端部設有插入 緣H0。該第4圖之例中，於3處配置有插入緣14〇。 一旦將預燒板BIB收置於空室40内’則對設於延伸板 130之連接器插入上述插入緣140。插入緣140則形成有複數 之訊號墊，且，延伸板13〇侧之連接器亦形成有複數之訊號 腳。該等訊號腳與訊號墊則分別對應而配置，訊號腳與訊 號墊並可電性連接。藉此，即可對延伸板130電性連接預燒 板BIB，並進行燒機裝置1〇與預燒板BIB之間之訊號交換。 其次’燒機測試結束後，將朝拔出方向拔出上述預燒板 12 201217802 BIB，而分離預燒板BIB側之插入緣140與延伸板130側之連 接器。 預燒板BIB上設有256個插座SK。上述第4圖之例中’ 插座SK係按插拔方向上16個（A列至P列）、寬度方向上16個 (第1行至第16行）之配置而排列。受測元件DUT可裝設於上 述插座SK上。即，總計16個xl6個=256個之受測元件DUT 可裝設於1片之預燒板BIB上。但，插座SK之數量不限於上 述之數量，而可為任意數量。 本實施例中，受測元件DUT係說明為NAND型快閃記 憶體。又，設定1受測元件DUT係於封裝内積層4片半導體 晶片（NAND型快閃記憶體晶片）而構成者。 對預燒板BIB則經形成於插入緣140之訊號墊輸入燒機 裝置10所生成之元件選擇訊號DSEL0〜DSEL79、測試型樣 資料、位址及電源等。 其中，元件選擇訊號DSEL0-DSEL63將供入分別對應 之受測元件DUT之晶片賦能端子/CE1〜4。該等晶片賦能端 子/ C E1〜4係用於設定是否使受測元件D U T内之對應之半導 體晶片進行動作之端子。上述第4圖之例中，即就A列之16 個受測元件DUT朝其等之晶片賦能端子/CE1共通地供給元 件選擇訊號DSEL0，並對其等之晶片賦能端子/CE2共通地 供給元件選擇訊號DSEL1，且對其等之晶片賦能端子/CE3 共通地供給元件選擇訊號DSEL2，並對其等之晶片賦能端 子/CE4共通地供給元件選擇訊號DSEL3。對B列〜P列之受測 元件DUT亦同樣供給元件選擇訊號DSEL4〜DSEL62。 13 201217802 又’元件選擇訊號DSEL64〜DSEL79將供入對應之受測 元件DUT之寫入致能端子/WE。寫入致能端子/WE係用於設 定是否允許對受測元件DUT之寫入之端子。上述第4圖之例 中’即就第1行之16個受測元件DUT對其等之寫入致能端子 /WE共通地供給元件選擇訊號DSEL79。對第2行〜第16行之 受測元件DUT亦同樣供給元件選擇訊號DSEL64〜DSEL78 之任一。但’元件選擇訊號之訊號數不限於上述訊號數， 而可為任意之訊號數。又’將供入元件選擇訊號之受測元 件DUT之端子亦不受限於上述之例。 測試型樣資料、位址及電源等亦將供入各受測元件 DUT之端子，但省略圖示及詳細說明。 依據上述構造’設定元件選擇訊號DSEL0〜DSEL79， 即可允許對任意之受測元件DUT之任意之半導體晶片之寫 入。藉此，而可進行對任意之受測元件DUT之任意之半導 體曰曰片之寫入測試。舉例言之，賦能元件選擇訊號DSEL2、 DSEL74後可將第6行A列之受測元件dut選為將進行功能 測"式之文測70件’而對該受測元件DUT内之第2個半導體晶 片進行寫入測試。In the same test, the test element which is repeatedly determined to be defective is judged to be defective in the above test. K In this case, the contact test result is that the tested component is highly likely to be defective in the next functional test. When the device under test that has been determined to be defective in the contact test is also judged to be defective in the function test, the same test will be repeated for the device under test as described above, so the function test will take a long time. Therefore, it can be said that the above-mentioned components to be tested should be excluded from the test to reduce the test time of the burner as a whole. However, the conventional burning device is supplied from the iSALPG to the plural _ supply of the same-test type data, so it is impossible to exclude the test object from the test object by the control test type data & . [Provisional Technical Documents] [Patent Document 1] [Patent Document 1] JP-A-2005-265665 SUMMARY OF INVENTION Technical Problem The present invention can provide an object that can be excluded from testing by a simple configuration. The burning device, the burning system, the burning machine control method and the control method of the burning machine system other than the object. Means for Solving the Problem In order to solve the above problems, the burning device of the present invention can be inserted into a job board equipped with a component to be tested, and the above-mentioned plurality of measured fines are subjected to the machine 201217802 1 八乙3. Selecting a signal output circuit, wherein the pre-burning wheel is used to select a component selection signal for testing a plurality of components from the plurality of components to be tested; and the test pattern output circuit can be pre-fired The board output is used for measuring the type of the device to be tested (4)m. The component selection signal output circuit includes a mask setting record for storing the mask setting data, and the component selection signal 1 can be shielded. The test component of the mosquito shielding device is not selected as the component to be tested for performing the foregoing functional test. Further, the present invention may further comprise: a contact test execution circuit, which may be used before the aforementioned functional test The burnt board outputs a contact test signal, and the contact device for confirming the electrical connection is performed on the aforementioned Wei test component mounted on the above-mentioned job board; the material circuit can be read Receiving the output signals of the aforementioned tested components of the contact service signal, and determining that the read output signal is the read theoretical value _ and outputting the contact test determination result; the result _, the recordable material connection _ test determination As a result, the masking setting circuit can shape the mask setting data to be specific to the specific contact test result from the plurality of the tested components. Further, the foregoing determining circuit can also read the Receiving the above-mentioned test type data, the input (four) number of each of the above-mentioned test elements, and whether the output signal read by the shape and the theoretical value are combined with the result of the determination, the foregoing test result record (4) Jing Wei (four) material county as The result of the functional test, the circuit is determined by the t-circuit, and the above-mentioned suspension setting data is taken from the foregoing (four)-like material, and the invention is further included: 201217802 Further, the present invention may further comprise: a determination circuit, which can be read from Receiving the output signals of the foregoing tested components of the foregoing test pattern data, and determining whether the read output signal is consistent with the theoretical value and outputting the function test determination result; The test result recording unit may record the function test result as a function test result; and the mask setting circuit may set the mask setting data to be specific to the specific function test result from the plurality of test elements. The functional test may also include a plurality of tests, and the device may further include a test sequence control circuit that controls the component selection signal output circuit, the test pattern output circuit, and the determination circuit, and installs the pre-burning plate The plurality of test elements are individually distinguished according to a predetermined number of test elements, thereby forming a plurality of groups, and performing predetermined tests included in the foregoing functional test on the test elements in sequence according to the group unit, and The device under test determined to be defective in the predetermined test repeats the same test at least one time until it is determined to be flawless. Alternatively, the device under test may be a NAND flash memory, and the component selection signal is selected. The device under test that will perform the aforementioned functional test allows writing, the aforementioned test pattern Allowing the material of the write of the writing has been tested element. In the control method of the burning device of the present invention, the burning device can be inserted into a pre-burning plate in which a plurality of components to be tested are mounted, and the plurality of devices to be tested are subjected to a burning test. The method comprises the following steps: The pre-burning board output is used for selecting a component selection signal of the device under test to be functionally tested from the plurality of components to be tested; and outputting the pre-burning plate for supplying the device under test to perform the aforementioned functional test of 201217802 Test type data, and the above components are selected in the screen 1 so that the shielded element (4) is not selected as the tested component to perform the aforementioned functional test. The burning machine system of the present invention comprises: a pre-burning plate, which can be equipped with a plurality of components to be tested; and a burning device for inserting the above-mentioned job board, and performing a burning test on the plurality of components to be tested; The device comprises: a component selection signal transceiving tb circuit 'can input the above-mentioned listening board (4), selecting a component selecting signal of the tested component to be functionally tested from the foregoing complex number = 7L; and, the test pattern output circuit can The foregoing board outputs test type data for supplying the device under test to perform the foregoing functional test; and the component selection signal output circuit includes a mask setting memory storing the mask setting data, and the component selection can be shielded. The signal is such that the device under test specified by the aforementioned mask setting data is not selected as the device under test to perform the aforementioned functional test. In the control method of the burning machine system of the present invention, the burning machine system comprises: a pre-burning plate, which can be provided with a plurality of components to be tested; and a burning device for inserting the pre-burning plate, and the plurality of components to be tested are Performing a burn-in test; the method includes the steps of: outputting, by the pre-burning plate, a component selection signal for selecting a test component to be functionally tested from the plurality of tested components; and, for outputting the pre-burning plate The test pattern data supplied to the device under test to be subjected to the foregoing functional test; and the component selection signal is shielded so that the device under test specified by the mask setting data is not selected as the device under test to perform the aforementioned functional test. . BRIEF DESCRIPTION OF THE DRAWINGS 201217802 FIG. 1 is a front elevational view of a burner apparatus of a firing machine system in accordance with an embodiment of the present invention. Fig. 2 is a front view showing an example of an internal structure in a state in which a burn-in board is housed in the burner unit of Fig. 1. Fig. 3 is a view showing an example of an internal structure for exchanging control signals and output signals between a burning device and a device under test in the burning device of Fig. 1. Fig. 4 is a plan view showing the layout of a burn-in board according to an embodiment of the present invention. Fig. 5 is a functional block diagram showing an example of the internal structure of the test control device according to an embodiment of the present invention. Fig. 6 is a functional block diagram showing an example of the internal structure of the component selection signal output circuit of an embodiment of the present invention. Fig. 7 is a flow chart showing the operation of the burner test performed by the burning system of an embodiment of the present invention. Fig. 8 is a flow chart showing the functional test operation of the burn-in test performed by the burner system according to the modification of the embodiment of the present invention. [Embodiment *] Mode for Carrying Out the Invention Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, the embodiments described below are not intended to limit the technical scope of the present invention. Fig. 1 is a front elevational view showing the burner unit 10 of an embodiment of the present invention, showing a state in which the door panel 20 is closed. Fig. 2 is a front elevational view showing the main part of the internal structure of the burner unit 1A, showing the state in which the burner unit 1 is inserted into the burn-in board BIB. The burner device i 〇 201217802 shown in the above figures and Fig. 2 is one type of semiconductor test device, and the burner device 10 and the burn-in plate BIB constitute the burner system of the present embodiment. As shown in the first and second figures, the inside of the burning apparatus 10 of the present embodiment is formed with a space 40 by the space partitioned by the heat insulating panel 30. One or a plurality of pre-burning plates BIB can be housed inside the empty chamber 40. In the present embodiment, as shown in Fig. 2, the pre-burning plate BIB is housed in the empty chamber 40 for each of the carriers CR. That is, each of the carriers CR forms a recess 50' for supporting the pre-burning plate BIB. The carrier CR can be housed in the empty chamber 40 in a state where the pre-burning plate bIB has been inserted into the recess 50. In this embodiment, it is possible to insert 15 pieces of pre-burning plates BIB into one carrier CR. Further, in the present embodiment, the configuration can accommodate four carriers CR in the empty chamber 40. Therefore, by accommodating the four carriers CR in the empty chamber 40, a total of 60 sheets of pre-burning sheets BIB can be placed in the empty chamber 40. However, the number and arrangement of the racks CR that can be accommodated in the empty chamber 40, and the number and arrangement of the burn-in boards BIB in the rack CR can be arbitrarily changed. Further, the pre-burning plate BIB may be directly housed in the empty chamber 40 without using the carrier CR. At this time, the groove 50 is formed in the empty chamber 40, and the pre-burning plate BIB is directly inserted into the above-mentioned groove 50. As shown in Fig. 1, the above-described burning device 10 is provided with two door panels 20, and when the door panel 20 is opened, the carrier CR can be placed and removed in the empty chamber 40. Further, the door panel 20 is also provided with a heat insulating material, so that the door panel 20 is in a closed state, that is, an empty chamber 40 constituting a space for heat insulation with the surroundings. Further, as shown in Fig. 2, the burner unit 1 of the present embodiment is provided with a heater 60 and a cooling unit 70. Further, the empty chamber 40 is provided with an air circulation duct DT extending on the left side and the upper side 10 201217802 side and the right side, and the air in the air circulation duct DT can be circulated by the fan 80 provided in the air circulation duct DT. The air can be circulated and stirred to make the temperature in the empty chamber uniform. The cooling unit 70 is composed of two cooling compressors 72 and two heat exchangers 74. In the present embodiment, the cooling unit 70 is a cooling method using a refrigerant. The cooling compressor 72 is a compressor that can circulate a refrigerant, and the heat exchanger 74 is an exchanger that can exchange cold and heat of the refrigerant with the air inside the empty chamber 40. Two heat exchangers 74 are provided in the air circulation duct DT. Therefore, by circulating the air by the fan 80, the circulating air is cooled by the heat exchanger 74, and the temperature inside the empty chamber 40 is lowered. Further, the heater 60 is constituted by, for example, an electrothermal heater, and constitutes heating of the heater 60 to generate heat. When the heater 60 is heated, the air in the air circulation duct DT is circulated, so that the temperature of the air in the empty chamber 40 can be increased. Further, a control unit CL is provided on the right side of the burning device 10. The control unit CL controls the burning device 10 in accordance with the preset setting and order, and performs a burn test. In the present embodiment, the heater 60 and the cooling unit 70 are controlled particularly during the burn-in test, and the temperature around the burn-in board BIB is set to a target temperature set by the user or the like. Fig. 3 is a functional block diagram showing an example of an internal structure for exchanging necessary control signals and output signals between the burning device 10 and the device under test. As shown in FIG. 3, the burning device 10 is provided with a test control device 100, a buffer plate 110, a drive plate 120, and an extension plate 130. The test control device 100 and the buffer plate 110 are disposed inside the control unit CL, for example, and the drive plate 120 and the extension plate 17130802 are provided in the empty chamber 40. The test control device 1 can perform overall control of the burn test performed by the above-described burner device 10. The burn-in test is performed following the control of the test control device. The control signals required for the execution of the burn-in test are output to the plurality of drive boards 120 via the buffer board 11 of the output buffer. The driving plate 120 and the extension plate 13 are disposed in the empty chamber 40 corresponding to the respective grooves 50. That is, in the present embodiment, the driving plate 120 and the extending plate 13A of the group are provided corresponding to one piece of the pre-burning plate BIB. Therefore, 60 sets of the drive plate 120 and the extension plate 130 are provided in the burner unit 1A shown in Figs. 1 and 2 . The control signal supplied to the driving board 120 is finally sent to the pre-burning board BIB via the extension board 13A. On the other hand, the output signal of the test data outputted by the pre-burning board BIB is input to the test control device 100 via the extension plate 13A, the drive plate 120, and the buffer plate 11〇. Thereby, the test control device 100 can obtain information on various test results. Fig. 4 is a view showing an example of the planar configuration of the burn-in board bIB of this embodiment. As shown in Fig. 4, the insertion end edge H0 is provided at the end portion of the burn-in board BIB in the insertion direction. In the example of Fig. 4, the insertion edge 14 is disposed at three places. Once the burn-in board BIB is placed in the empty chamber 40, the above-described insertion edge 140 is inserted into the connector provided on the extension board 130. The insertion edge 140 is formed with a plurality of signal pads, and the connector on the side of the extension plate 13 is also formed with a plurality of signal pins. The signal pins are respectively arranged corresponding to the signal pads, and the signal pins and the signal pads are electrically connected. Thereby, the extension plate 130 can be electrically connected to the pre-burning plate BIB, and the signal exchange between the burning device 1〇 and the pre-burning plate BIB can be performed. Next, after the end of the burn-in test, the pre-burning plate 12 201217802 BIB is pulled out in the pulling-out direction, and the connector of the insertion edge 140 and the extension plate 130 side of the pre-burning plate BIB side is separated. The burn-in board BIB has 256 sockets SK. In the example of Fig. 4, the socket SK is arranged in the arrangement of 16 (column A to column P) and 16 in the width direction (first row to 16th row). The device under test DUT can be mounted on the above socket SK. That is, a total of 16 x 16 words = 256 DUTs to be tested can be mounted on one of the pre-burning plates BIB. However, the number of sockets SK is not limited to the above, but may be any number. In this embodiment, the DUT under test is described as a NAND type flash memory. Further, the one to be tested DUT is configured to be formed by stacking four semiconductor wafers (NAND type flash memory chips) in a package. The burn-in board BIB is input to the component selection signals DSEL0 to DSEL79, test pattern data, address and power source generated by the signal pad formed on the insertion edge 140. The component selection signals DSEL0-DSEL63 are supplied to the respective wafer enable terminals / CE1 to 4 of the corresponding test element DUT. The wafer enabling terminals / C E1 to 4 are for setting terminals for operating the corresponding semiconductor wafer in the device under test D U T . In the example of FIG. 4, the 16 DUTs of the A column are commonly supplied with the component selection signal DSEL0 toward the wafer enable terminals /CE1 of the same row, and the wafer enable terminals /CE2 are commonly used. The component selection signal DSEL1 is supplied, and the wafer enable terminal /CE3 is supplied to the component selection signal DSEL2 in common, and the wafer selection terminal /CE4 is supplied to the component selection signal DSEL3 in common. The component selection signals DSEL4 to DSEL62 are also supplied to the DUTs of the B to P columns. 13 201217802 Further, the component selection signals DSEL64 to DSEL79 are supplied to the write enable terminal /WE of the corresponding device DUT under test. The write enable terminal /WE is used to set whether or not to allow writing to the DUT of the device under test. In the example of Fig. 4 described above, the component selection signal DSEL79 is commonly supplied to the write enable terminals /WE of the 16 test elements DUT of the first row. The device under test DUT of the second row to the 16th row is also supplied to any of the component selection signals DSEL64 to DSEL78. However, the number of signals of the component selection signal is not limited to the above number of signals, but may be any number of signals. Further, the terminal of the DUT to which the component selection signal is supplied is also not limited to the above example. The test pattern data, address and power supply will also be supplied to the terminals of each DUT under test, but the illustration and detailed description are omitted. The writing of the component selection signals DSEL0 to DSEL79 in accordance with the above configuration allows the writing of any semiconductor wafer of any of the DUTs under test. Thereby, the writing test of any of the semiconductor thin films of any of the DUTs under test can be performed. For example, after the component selection signals DSEL2 and DSEL74 are enabled, the device under test in row 6A can be selected as the function of the function test, and the number of the device in the DUT is Two semiconductor wafers were subjected to a write test.
而可將1片之預燒板BIB上裝設之複數之受測元件 DUT依預讀之受㈣元件加了分別予以區分而構成複數群 、’且並扣群組單位依序對受測元件DUT供給測試型樣訊 '進行寫入測試。舉例言之，本實關巾，係以8個受 ’則凡件DUT為1組而將256個受測元件DUT分為32群組進行 寫入測°式°亦即’首先就A列之第1群組之8個受測元件DlJT 201217802 進行寫入測試（第1次掃瞄），接著就A列之第2群組之其餘8 個受測元件DUT進行寫入測試（第2次掃瞄），以下亦同，最 後則就P列之第32群組之8個受測元件DUT進行寫入測試 (第32次掃瞄）。 又，對受測元件DUT之預定端子供給預定訊號，則可 按群組單位依序使燒機裝置10讀取來自受測元件DUT之輸 出訊號，而進行動作判定並儲存判定結果作為測試結果。 第5圖係顯示本發明之一實施例之測試控制裝置10 0之 内部構造之一例之功能區圖。如第5圖所示，測試控制裝置 100包含測試順序控制電路200、測試型樣輸出電路 (ALPG)210、元件選擇訊號輸出電路220、判定電路230、測 試結果記錄部240、屏蔽設定電路250、接觸測試執行電路 260。元件選擇訊號輸出電路220係對應各預燒板BIB而設 置。即’本實施例中，元件選擇訊號輸出電路220與預燒板 BIB之片數相同設有60個。 測試順序控制電路2 00在本實施例中係諸如由設於上 述控制部CL之個人電腦等獨立電腦所構成。測試順序控制 電路200可依循程式而藉測試順序控制訊號控制測試型樣 輸出電路210、元件選擇訊號輸出電路22〇、判定電路23〇、 測試結果記錄部240、屏蔽設定電路25〇及接觸測試執行電 路260之動作狀態。上述程式係諸如儲存於上述個人電腦之 記憶裝置内。 測試型樣輸出電路210可經緩衝板11()等而朝預燒板 BIB輸出用於對將進行功能測試之受測元件DUT供給之測 15 201217802 試型樣資料。測試型樣資料係由型樣程式所設定。型樣程 式係諸如儲存於設於上述控制部CL之個人電腦之記憶裝置 内。本實施例中，設有1個測試型樣輸出電路21〇。 各元件選擇訊號輸出電路220可經緩衝板110等而朝對 應之預燒板BIB輸出用於自複數之受測元件duT中選出將 進行功能測試之受測元件DUT之元件選擇訊號 DSEL0〜DSEL79。本實施例中，設定元件選擇訊號為賦能 (諸如高位準）時選出受測元件DUT，而元件選擇訊號為失效 (諸如低位準）時則不選出受測元件DUT。元件選擇訊號所選 出之將進行功能測試之受測元件DUT將允許寫入。上述之 測試型樣資料則將寫入已允許寫入之受測元件DUT。未被 選為將進行功能測試之受測元件之受測元件Dut則不允許 寫入。 元件選擇訊號輸出電路220包含儲存有屏蔽設定資料 之屏蔽设疋s己憶體’對於屏蔽設定資料所特定之受測元件 DUT則使元件選擇訊號DSEL0〜DSEL79失效。即，各元件 選擇訊號輸出電路220將屏蔽元件選擇訊號 DSEL0-DSEL79，而不選擇屏蔽設定資料所特定之受測元 件DUT作為將進行功能測試之受測元件dut。 屏蔽設定資料係已特定諸如就各次掃瞄（各群纪）進行 屏蔽之元件選擇訊號之資料。 接觸測試執行電路260可在功能測試之前，經緩衝板 110等而朝各預燒板BIB輸出接觸測試用訊號，而對預择板 BIB上裝設之複數受測元件D U T執行用於確認其電性^接 16 201217802 之接觸測試。即’接觸測試中，將測試受測元件DUT與播 座SK之對應之端子彼此是否已電性連接。 判定電路230則於接觸測試時，經緩衝板110等而讀取 來自已供入接觸測試用訊號之各受測元件之輸出訊號，並 判疋所δ貝取之輸出机號疋否與理論值一致而輸出接觸測試 判定結果。 又，判定電路230並可於功能測試時，經緩衝板丨1〇等 而讀取來自已供入測試型樣資料之各受測元件之輸出訊 號，並判定所讀取之輸出訊號是否與理論值一致而輸出功 能測試判定結果。 測5式結果記錄部240則記錄判定電路23〇之接觸測試判 定結果作為接觸測試結果，並記錄功能測試判定結果作為 功能測試結果。 屏蔽設定電路250則基於測試結果記錄部24〇所記錄 接觸測試結果與功能測試結果’對各元件選擇訊號輪出 ;電 路22〇設定屏蔽設定資料’以由複數之受測元件dut中特定 接觸測試結果為有瑕疵者及功能測試結果為有瑕疵者 其中一種。 一 工，丨…，、·1 a上你栩出電路 210、兀件選擇訊號輸出電路咖 '判定電路23〇 ,以就 板BIB上所裝設之複數受測元件DUT依預定數之受剛—义 丽分別加以區分而構錢數群組，並按群組單位依=件 受測元件ixmt行減測奴就_ 4 對 上述預定測試中判定為有料之受測元件DUT重複卜 17 201217802 上相同之測試至判定為無瑕疵為止。 第6圖係顯示本發明一實施例之元件選擇訊號輸出電 路220之内部構造之一例之功能區圖。如第6圖所示，元件 選擇訊號輸出電路220包含元件選擇訊號設定功能電路 300、屏蔽設定記憶體310、邏輯電路320。邏輯電路320係 對應各元件選擇訊號DSEL0〜DSEL79而設置。即，本實施 例中設有80個邏輯電路320。各邏輯電路320則包含AND電 路(邏輯積電路)330、OR電路(邏輯和電路)340、選擇器350。 元件選擇訊號設定功能電路300係用於設定將進行功 能測試之受測元件DUT者，可朝80個邏輯電路320中之預定 電路輸出高位準訊號。舉例言之，元件選擇訊號設定功能 電路300將對邏輯電路320之何者依何時序輸出高位準訊 號，可依循程式而受控制。本實施例中，元件選擇訊號設 定功能電路300係同時對8個邏輯電路320輸出高位準訊 號，並對其餘之邏輯電路320輸出低位準訊號。 屏蔽設定記憶體310儲存有屏蔽設定資料。屏蔽設定資 料係用於特定將屏蔽元件選擇訊號DSEL之受測元件DUT 之資料。屏蔽設定記憶體310可對80個邏輯電路32〇中對應 將不進行功能測試之受測元件DUT之邏輯電路32〇輸出高 位準訊號。 其次’詳細說明上述邏輯電路320之構造。在此，將就 可輸出元件選擇訊號DSEL0之邏輯電路320加以說明。 AND電路330可自一方之輸入端子輪入來自元件選擇 訊號設定功能電路300之訊號，並自他方之輸入端子（逆轉 18 201217802 換輸入端子）輸入來自屏蔽設定記憶體31〇之訊號。藉此， 而可僅在來自元件選擇訊號設定功能電路300之訊號為高 位準，而來自屏蔽設定記憶體310之訊號為低位準時’使 AND電路330輸出高位準訊號。 OR電路340則可由一方之輸入端子輸入PG_CMD訊 號，並由他方之輸入端子輸入AND電路330之輸出訊號。 PG_CMD訊號係欲將全部元件選擇訊號DSEL0-DSEL79設 為賦能時設成高位準之訊號。 選擇器350則由一方之輸入端子「1」輸入賦能訊號 Enable，並由他方之輸入端子「0」輸入失效訊號Disable， 並由選擇端子「S」輸入OR電路340之輸出訊號。選擇器350 將在自選擇端子「S」輸入高位準訊號後，將元件選擇訊號 DSEL0設為賦能，並於對選擇端子「S」輸入低位準訊號後， 將元件選擇訊號DSEL0設為失效。 可輸出元件選擇訊號DSEL1〜DSEL79之各邏輯電路 320亦為相同之構造，故省略其說明。 如此，如前所述，各元件選擇訊號輸出電路220可朝對 應之預燒板BIB輸出用於自複數之受測元件DUT中選出將 進行功能測試之受測元件DUT之元件選擇訊號 DSEL0〜DSEL79。但，各元件選擇訊號輸出電路220可屏蔽 元件選擇訊號DSEL0〜DSEL79，以避免屏蔽設定資料所特 定之受測元件DUT被選為將進行功能測試之受測元件。 其次，參照第7圖，說明燒機系統之燒機測試之動作之 一例。第7圖係說明本發明一實施例之燒機系統之燒機測試 19 201217802 之動作之流程圖。 首先藉接觸測試執行電路260對各預燒板BIB上之各受 測元件DUT輸出接觸測試用訊號，而執行接觸測試（步驟The DUTs of the plurality of devices to be tested mounted on the BIB of the pre-burning plate can be distinguished according to the pre-reading (four) components to form a complex group, and the group of the components is sequentially connected to the device under test. The DUT is supplied with a test type message to perform a write test. For example, in this case, the 8 pairs of DUTs are divided into 32 groups and the DUTs are divided into 32 groups for writing into the measurement type, that is, 'first on the A column. The 8 test elements D1JT 201217802 of the first group perform the write test (the first scan), and then the write test is performed on the remaining 8 DUTs of the second group of the second column (the second scan) The same applies to the following. Finally, the write test (32nd scan) is performed on the 8 DUTs of the 32th component of the P column. Further, when a predetermined signal is supplied to a predetermined terminal of the device under test DUT, the burning device 10 can be sequentially read by the group unit to read the output signal from the DUT under test, and the operation result is judged and the result of the determination is stored as a test result. Fig. 5 is a functional block diagram showing an example of the internal structure of the test control device 100 of one embodiment of the present invention. As shown in FIG. 5, the test control device 100 includes a test sequence control circuit 200, a test pattern output circuit (ALPG) 210, a component selection signal output circuit 220, a determination circuit 230, a test result recording portion 240, a mask setting circuit 250, Contact test execution circuit 260. The component selection signal output circuit 220 is provided corresponding to each of the burn-in plates BIB. That is, in the present embodiment, the component selection signal output circuit 220 has the same number of chips as the burn-in board BIB. In the present embodiment, the test sequence control circuit 200 is constituted by a separate computer such as a personal computer provided in the above-described control unit CL. The test sequence control circuit 200 can follow the test sequence control signal control test pattern output circuit 210, component selection signal output circuit 22, decision circuit 23, test result recording unit 240, mask setting circuit 25, and contact test execution. The operational state of circuit 260. The above program is stored in a memory device of the above personal computer. The test pattern output circuit 210 can output a test pattern for supplying the DUT to be tested for functional testing to the burn-in board BIB via the buffer plate 11() or the like. The test pattern data is set by the type program. The pattern program is stored, for example, in a memory device of a personal computer provided in the control unit CL. In this embodiment, one test pattern output circuit 21 is provided. Each of the component selection signal outputting circuits 220 can output component selection signals DSEL0 to DSEL79 for selecting the device under test DUT to be functionally tested from the plurality of devices under test duT to the corresponding burn-in board BIB via the buffer board 110 or the like. In this embodiment, when the component selection signal is set to enable (such as a high level), the device under test DUT is selected, and when the component selection signal is disabled (such as a low level), the device under test DUT is not selected. The DUT selected by the component selection signal that will perform the functional test will allow writing. The above test pattern data will be written to the DUT of the device under test that has been allowed to be written. The device under test, Dut, which is not selected as the device under test to be functionally tested, is not allowed to be written. The component selection signal output circuit 220 includes a mask device that stores the mask setting data. The DUT that is specific to the mask setting data invalidates the component selection signals DSEL0 to DSEL79. That is, each component selection signal output circuit 220 selects the shield component selection signals DSEL0-DSEL79 without selecting the device under test DUT specified by the mask setting data as the device under test dut to be functionally tested. The mask setting data is specific to the component selection signals that are masked for each scan (group). The contact test execution circuit 260 may output a contact test signal to each of the burn-in boards BIB via the buffer board 110 or the like before the function test, and perform a check for the plurality of test elements DUT mounted on the pre-selection board BIB for confirming the power thereof. Contact test of 201217802. That is, in the 'contact test, whether the terminals corresponding to the test device DUT and the broadcast SK are electrically connected to each other. The determining circuit 230 reads the output signal from each of the tested components that have been supplied with the contact test signal via the buffer board 110 or the like during the contact test, and determines whether the output number of the δB is the same as the theoretical value. The output contact test determines the result. Moreover, the determining circuit 230 can read the output signals from the tested components that have been supplied with the test pattern data through the buffer board 〇1〇, etc. during the function test, and determine whether the read output signal is theoretical or not. The values are consistent and the function test results are output. The measurement result recording unit 240 records the result of the contact test determination by the determination circuit 23 as the contact test result, and records the result of the function test as the function test result. The mask setting circuit 250 selects the signal selection for each component based on the recorded contact test result and the function test result by the test result recording unit 24; the circuit 22 sets the mask setting data to be tested by the specific contact in the plurality of tested components dut The result is one of the flawed and functional test results. One work, 丨...,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, - Yili separately distinguishes and constructs the group of money, and according to the group unit, the ixmt line of the measured component is reduced. _ 4 Repeat the test component DUT which is determined as the material in the above predetermined test 17 201217802 The same test until the judgment is innocent. Fig. 6 is a functional block diagram showing an example of the internal configuration of the component selection signal output circuit 220 according to an embodiment of the present invention. As shown in Fig. 6, the component selection signal output circuit 220 includes a component selection signal setting function circuit 300, a mask setting memory 310, and a logic circuit 320. The logic circuit 320 is provided corresponding to each of the component selection signals DSEL0 to DSEL79. That is, 80 logic circuits 320 are provided in this embodiment. Each logic circuit 320 includes an AND circuit (logical product circuit) 330, an OR circuit (logic and circuit) 340, and a selector 350. The component selection signal setting function circuit 300 is for setting the DUT of the device under test to perform the function test, and can output a high level signal to a predetermined circuit among the 80 logic circuits 320. For example, the component selection signal setting function circuit 300 will output a high level signal to the logic circuit 320 according to the sequence, and can be controlled according to the program. In this embodiment, the component selection signal setting function circuit 300 outputs a high level signal to the eight logic circuits 320 at the same time, and outputs a low level signal to the remaining logic circuit 320. The mask setting memory 310 stores the mask setting data. The mask setting data is used to specify the material of the DUT to be tested for the shield component selection signal DSEL. The mask setting memory 310 can output a high level signal to the logic circuit 32 of the 80 logic circuits 32 that corresponds to the DUT of the device under test which is not functionally tested. Next, the construction of the above logic circuit 320 will be described in detail. Here, the logic circuit 320 for outputting the component selection signal DSEL0 will be described. The AND circuit 330 can input a signal from the component selection signal setting function circuit 300 from one of the input terminals, and input a signal from the mask setting memory 31 from the other input terminal (reverse 18 201217802 switching input terminal). Therefore, the AND circuit 330 can output the high level signal only when the signal from the component selection signal setting function circuit 300 is at a high level and the signal from the mask setting memory 310 is a low level. The OR circuit 340 can input the PG_CMD signal from one of the input terminals, and input the output signal of the AND circuit 330 from the other input terminal. The PG_CMD signal is intended to set all component selection signals DSEL0-DSEL79 to a high level signal when energized. The selector 350 inputs the enable signal Enable from one of the input terminals "1", and inputs the disable signal Disable from the other input terminal "0", and inputs the output signal of the OR circuit 340 from the selection terminal "S". The selector 350 will set the component selection signal DSEL0 to enable after inputting the high level signal from the selection terminal "S", and disable the component selection signal DSEL0 after inputting the low level signal to the selection terminal "S". The respective logic circuits 320 of the output element selection signals DSEL1 to DSEL79 have the same configuration, and the description thereof will be omitted. In this way, as described above, each component selection signal output circuit 220 can output component selection signals DSEL0 to DSEL79 for selecting the device under test DUT to be functionally tested from the plurality of DDUs to be tested. . However, each component selection signal output circuit 220 can shield the component selection signals DSEL0 to DSEL79 to prevent the device under test DUT specified by the mask setting data from being selected as the component to be tested for functional testing. Next, an example of the operation of the burn-in test of the burning system will be described with reference to Fig. 7. Figure 7 is a flow chart showing the operation of the burn-in test 19 201217802 of the burner system according to an embodiment of the present invention. First, the contact test execution circuit 260 outputs a contact test signal to each of the DUTs on each of the burn-in boards BIB, and performs a contact test (step).
S10)。本實施例中，將對60片x256個= 15360個受測元件DUT 執行接觸測試。此時，則藉判定電路230讀取來自上述各受 測元件DUT之輸出訊號，並判定所讀取之輸出訊號是否與 理論值一致，而判定各受測元件DUT之電性連接是否正 常。其次，藉測試結果記錄部24〇預先記錄接觸測試判定結 果作為接觸測試結果。 接著，藉屏蔽設定電路250自測試結果記錄部240讀取 接觸測試結果（步驟SU)。本實施例中，係讀取與各受測元 件DUT對應之15360個接觸測試結果。 然後，藉屏蔽設定電路250對應所讀取之接觸測試結果 而就屏蔽設定資料進行屏蔽設定（步驟S12)。舉例言之，當 第1片之預燒板BIB中第6行a列之受測元件DUT之接觸測 試結果為有瑕疵時，即就屏蔽設定資料進行屏蔽設定，以 於A列之功能測試時將元件選擇訊號DSEL設為失效。上述 屏蔽設定可諸如利用程式而自動進行。但，亦可手動進行 屏蔽設定。 其次，藉屏蔽設定電路250更新屏蔽設定記憶體310(步 驟SU)。上述例中，係藉在步驟S12中業經屏蔽設定之屏蔽 設定資料更新對應第1>}預燒板BIB之元件選擇訊號輸出電 路220之屏蔽設定記憶體31〇。 然後’進行功能測試(步驟S14)。在此，將就進行寫入 20 201217802 測試作為功能測試之一例加以說明。功能測試係藉測試型 樣輸出電路21〇產生測試型樣資料，並將該測試蛰樣資料寫 入由元件選擇訊號DSEL0〜DSEL79中選出之受測元件DUT 而進行。 舉例言之，首先就60片之預燒板BIB個別由元件選擇訊 號設定功能電路300依循程式而輸出訊號，以對A列之第2 行、第4行、第6行、第8行、第10行、第12行、第14行及第 16行之8個受測元件DUT之第一個半導體晶片進行功能測 試。藉此，元件選擇訊號輸出電路220可將元件選擇訊號 DSEL0、DSEL64、DSEL66、DSEL68、DSEL70、DSEL72、 DSEL74、DSEL76、DSEL78設為賦能。 然而，上例中，已基於屏蔽設定資料而將第1片預燒板 BIB之相關之元件選擇訊號DSEL74強制設為失效’故無法 對第1片預燒板BIB之第6行A列之受測元件DUT進行寫 入。即，無法對該受測元件DUT進行功能測試。 上述之例中，該第6行A列之受測元件DUT因接觸測試 結果為有瑕疲，故進行功能測試時為有瑕疵*之可此性極 高。本實施例之燒機裝置10為提昇測試精度而如前述般’ 構成對在功能測試所包含之預定測試中一旦判定為有瑕疵1 之受測元件DUT，將重複1次以上相同之測試至判定為無瑕 '疵為止。其次，在相同之測試中重複判定為有叔疮之受測 元件DUT即就該測試最終判定為有瑕疵。 然而，本實施例中，則設定不對接觸測試結果為有瑕 疵之受測元件DUT進行功能測試，故可避免重複進行判為 21 201217802 有瑕疵之測試之時間浪費。 進而，該第6行A列之受測元件DUT之全部端子極可能 並未正常進行訊號或電源之供給。上述狀態下一旦對寫入 致能端子/WE供給訊號，則該受測元件DUT可能諸如流通 大於一般之異常電流。此時，可能因用以朝複數之受測元 件DUT供電之燒機裝置10内之電源裝置之電流供給能力不 足’而無法對接觸測试結果為無瑕.疵之其它受測元件dut 供給充分電流。因此’可能對原本應判定為無瑕疵之受測 元件DUT之功能測試造成不良影響，而誤判為有瑕疵。 然而’本貫施例中’上述接觸測試結果為有瑕疵之第6 行A列之受測元件DUT並未自寫入致能端子/we供入訊 號，故未流通異常電流。 如上所述，依據本實施例，由於構成可屏蔽元件選擇 訊號，以避免屏蔽設定記憶體310之屏蔽設定資料所特定之 受測元件DUT被選為將進行功能測試之受測元件dut，故 可將任意之受測元件DUT排除於測試對象以外。因此，設 定屏蔽設定資料以特定接觸測試結果為有瑕疵之受測元件 DUT，即可將該種受測元件DUT排除在隨後之功能測試之 測試對象以外。藉此，即可不對接觸測試結果為有瑕疵之 受測元件DUT重複執行功能測試，故可縮短功能測試之測 試時間。 又，本實施例之燒機裝置1〇若構成對習知之燒機裝置 追加屏蔽設定s己憶體31〇 ’並對應接觸測試結果進行屏蔽設 定，即可實現。因此，可藉較少硬體之追加，而以簡單之 22 201217802 構造實現本發明。 (變形例） 其次，參照第8圖說明燒機系統之功能測試之動作之另 一例。第8圖係說明本發明一實施例之變形例之燒機系統所 執行之燒機測試之功能測試之動作之流程圖。 以下各步驟亦可作為諸如第7圖之流程圖中步驟S14之 〇 功能測試而執行。此時，屏蔽設定將反映接觸測試結果與 功能測試結果。 或，亦可不於屏蔽設定反映接觸測試結果，並與第7圖 之流程圖分別獨立而執行以下各步驟。此時，屏蔽設定則 反映功能測試結果。 首先，藉測試型樣輸出電路210開始測試型樣資料之輸 出（步驟S20)。 接著，測試元件選擇訊號DSEL0〜DSEL79所選出之受 測元件DUT(步驟S21)。 以下則就該步驟S21之測試加以詳細說明。 舉例言之，首先就6 0片之預燒板BIB個別由元件選擇訊 號輸出電路220輸出元件選擇訊號DSEL0〜DSEL79(第一次 掃瞄），以選出A列之第2行、第4行、第6行、第8行、第10 行、第12行、第14行及第16行之8個受測元件DUT之第一個 半導體晶片。 藉此，而對上述各受測元件DUT之第1個半導體晶片之 各記憶單元寫入測試型樣資料。 其次，藉判定電路230自上述8個受測元件DUT之第1個 23 201217802 半導體晶片讀取輪出訊號(即，已寫入之資料），並判定所讀 取之輸出訊號是否與理論值（即，測試型樣資料）一致。然 後，藉測試結果記錄部240將判定電路230之功能測試判定 結果預先記錄為功能測試結果。在此，舉例言之，亦可將 文測7L件DUT中瑕疵記憶單元數在預定數以上之區段定義 為壞塊，而就各受測元件DUT記錄壞塊數作為功能測試結果。 接著’自第2個半導體晶片重複上述測試至第4個半導 體晶片為止。 隨後’就60片之預燒板BIB個別選出A列之第1行、第3 行、第5行、第7行、第9行、第11行 '第13行及第15行之8 個受測元件DUT之第一個半導體晶片（第二次掃瞄）。 然後’依程式所預設之順序進行相同之測試，並藉32 次掃瞄’結束對各預燒板BIB之256個受測元件DUT之測試。 其次’藉測試型樣輸出電路21〇結束測試型樣資料之輸 出（步驟S22)。 接著，藉屏蔽設定電路250自測試結果記錄部240讀取 功能測試結果（步驟S23)。 然後，藉測試順序控制電路2 0 0判定功能測試是否已結 束（步驟S24) ’若已結束(步驟S24 :是），則結束處理。 若功能測試尚未結束（步驟S24 :否），則藉屏蔽設定電 路2 5 0對應所讀取之功能測試結果而就屏蔽設定資料進行 屏蔽設定（步驟S25)。舉例言之，亦可進行屏蔽設定而在功 能測試結果中將壞塊數為預定數以上之受測元件DUT特定 為有瑕疵，而特定該種受測元件DUT。一如前述，上述之 24 201217802 屏蔽設定可諸如利用程式而自動進行。 其次，藉屏蔽設定電路250以在步驟S25中業經屏蔽設 定之屏蔽設定資料更新屏蔽設定記憶體310(步驟S26)。 接著，藉測試型樣輸出電路210開始新測試型樣資料之 輸出（步驟S20)。 然後，測試元件選擇訊號DSEL0〜DSEL79所選出之受 測元件DUT(步驟S21)。在此，雖將如前述般進行測試，但 因對於步驟S25中業經屏蔽設定之受測元件DUT，元件選擇 訊號DSEL0〜DSEL79並非賦能狀態，故不進行測試。 後續之處理則與前述之處理相同。 如上所述，依據本變形例，藉設定屏蔽設定資料而可 特定某功能測試結果為有瑕疵之受測元件DUT，即可將上 述之受測元件DUT排除於後續之功能測試之測試對象以 外。藉此，即可不對有瑕疵之受測元件DUT重複執行功能 測試，故可縮短測試時間。 另，本發明不限於上述實施例而可進行各種變形實 施。舉例言之，上述之各處理部之内部構造僅屬例示，若 可實現相同·之處理，則可採用各種變形形態。舉例言之， 第5圖所示之測試控制裝置10 0之内部構造及第6圖所示之 元件選擇訊號輸出電路220之内部構造亦可進行各種變形 實施而實現相同之處理。 又，上述實施例中已圖示之各處理部則係為說明本發 明之一實施例而僅圖示了所需之部分。因此，實際之燒機 裝置10應解釋為就各處理部追加上述圖示中未出現之各種 25 201217802 功能部而構成者 又，上述之實施例所採用之各種數值僅屬例示，可視 受測元件DUT之規格、供給之測試型樣資料之型樣等之不 同，而採用各種數值。 進而，上述實施例中，雖就將接觸測試或功能測試中 判為有瑕疲之受測元件D U τ排除於測試對象以外之一例加 以5兒明’但亦可進行屏蔽設定而將任意之正常受測元件 DUT排除於測對象以外。 上述貫施例中，雖就1受測元件DUT包含4片半導 片之例加以說明，但亦可僅包含丨片半導體晶片，或 任意片數之半導體晶片。 貫施例中’雖就受測元件DUT係NAND型快 門°己隐體之例力σ以說明，但亦可為其它半導體裝置。 【圖式簡單說明】 第1圖係本發明一實施例之燒機系統之燒機裝置之整 體正面圖。 第2圖係顯不第1圖之燒機裝置中收置有預燒板之狀態 下之内部構造例之正面配置圖。 ，第3圖係顯示第1圖之燒機裝置中，用於在燒機裝置與 又則元件之間交換控制訊號及輸出訊號之内部構造之-例 之功月色區圖。 第圖係本發明一實施例之預燒板之平面配置圖。 第5圖係顯示本發明-實施例之測試控制裝置之内部 構造之—狀1 力能區圖。 26 201217802 路之示本發明—實施狀元件選擇訊號輸出電 ★ 4構造之一例之功能區圖。 機測實關之燒㈣統所執行之燒 執行第8:係說明本發明-實施例之變形例之燒機系統所 订之燒機測試之功能測試動作之流裎圖。 【主要元件符號說明】 10···燒機裴置 20.. .門板 30.. .隔熱板 40…空室 50···凹槽 60…加熱器 220···元件選擇訊號輸出電路 230…判定電路 240…測試結果記錄部 250…屏蔽設定電路 260…接觸測試執行電路 300…元件選擇訊號設定功能電路 70…冷卻單元 310…屏蔽設定記憶體 72…冷卻壓縮機 320…邏輯電路 74…熱交換器 80…風扇 330…AND電路 340…OR電路 100…測試控制裝置 350…選擇器 110···緩衝板 「1」…輸入端子 120…驅動板 「〇」…輸入端子 130···延伸板 「S」…選擇端子 140…插入緣 BIB…預燒板 200…測試順序控制電路 /CE1〜4…晶片賦能端子 210···測試型樣輸出電路 CL···控制部 27 201217802 CR…載架 Enable···賦能訊號 Disable···失效訊號 S10〜S14、S20〜S26…流程步驟 DSELO-DSEL79…元件選擇訊號 SK…插座 DT···空氣循環管道 DUT···受測元件 /WE…寫入致能端子 28S10). In this embodiment, a contact test will be performed on 60 x 256 = 15360 DUTs under test. At this time, the decision circuit 230 reads the output signals from the above-mentioned respective test elements DUT, and determines whether the read output signals coincide with the theoretical values, and determines whether the electrical connection of the DUTs is normal. Next, the test result recording unit 24 records the contact test result in advance as the contact test result. Next, the contact test result is read from the test result recording portion 240 by the mask setting circuit 250 (step SU). In this embodiment, 15360 contact test results corresponding to the DUTs to be tested are read. Then, the mask setting circuit 250 performs mask setting on the mask setting data in response to the read contact test result (step S12). For example, when the contact test result of the DUT of the first row and the row of the first row of the first piece of the BIB is 瑕疵, the mask setting data is masked for the function test of the column A. The component selection signal DSEL is set to be disabled. The above mask settings can be made automatically, such as with a program. However, you can also manually set the mask. Next, the mask setting memory 310 is updated by the mask setting circuit 250 (step SU). In the above example, the mask setting memory 31 of the component selection signal output circuit 220 corresponding to the first >} burn-out board BIB is updated by the mask setting data masked in step S12. Then, a function test is performed (step S14). Here, the writing will be described as an example of a functional test. The functional test is performed by the test pattern output circuit 21 to generate test pattern data, and the test sample data is written into the device under test DUT selected by the component selection signals DSEL0 to DSEL79. For example, firstly, the 60-piece pre-burning board BIB is individually output by the component selection signal setting function circuit 300 according to the program, and the second row, the fourth row, the sixth row, the eighth row, the The first semiconductor wafer of the eight DUTs of the 10th row, the 12th row, the 14th row, and the 16th row is functionally tested. Thereby, the component selection signal output circuit 220 can set the component selection signals DSEL0, DSEL64, DSEL66, DSEL68, DSEL70, DSEL72, DSEL74, DSEL76, DSEL78. However, in the above example, the component selection signal DSEL74 associated with the first pre-burning panel BIB is forcibly set to be invalid based on the mask setting data, so that the sixth row A of the first pre-burning panel BIB cannot be accepted. The measuring component DUT performs writing. That is, the function test of the device under test DUT cannot be performed. In the above example, the DUT of the device under test in row 6 and column A is fatigued due to the contact test result, so it is extremely high when performing the function test. The burner device 10 of the present embodiment is configured to improve the test accuracy as described above. When the device under test DUT is determined to be 瑕疵1 in the predetermined test included in the function test, the same test is repeated one to the other until the determination is made. For innocent '疵 so far. Secondly, in the same test, the DUT of the device under test which has been determined to have a tertiary sore is finally judged to be defective. However, in this embodiment, the function test of the DUT of the test component which is not in contact with the test result is set, so that the time waste of the test which is judged as 21 201217802 can be avoided. Further, all of the terminals of the device under test DUT in the sixth row and A column may not be normally supplied with signals or power. In the above state, once the write enable terminal /WE is supplied with a signal, the device under test DUT may flow, for example, more than a normal abnormal current. At this time, it is possible that the current supply capability of the power supply device in the burning device 10 for supplying power to the plurality of DUTs under test is insufficient, and the contact test result is not sufficient. . Therefore, it may adversely affect the functional test of the DUT that should be judged to be innocent, and the misjudgment is flawed. However, in the present embodiment, the contact test result of the above-mentioned contact test is that the DUT of the sixth row and the column A of the defective unit is not supplied with the self-writing enable terminal/we, so that no abnormal current flows. As described above, according to the present embodiment, since the maskable component selection signal is formed to prevent the device under test DUT specified by the mask setting data of the mask setting memory 310 from being selected as the device under test dut to be functionally tested, Exclude any DUT under test from the test object. Therefore, by setting the mask setting data to the defective component DUT with a specific contact test result, the DUT can be excluded from the test object of the subsequent functional test. In this way, the functional test can be repeated without performing a functional test on the DUT of the test component that is in contact with the test result, thereby shortening the test time of the functional test. Further, the burning apparatus 1 of the present embodiment can be realized by adding a mask setting s repudiation 31 〇 ' to a conventional burning apparatus and masking the contact test result. Therefore, the present invention can be implemented with a simple 22 201217802 configuration with less hardware addition. (Modification) Next, another example of the operation of the function test of the burning system will be described with reference to Fig. 8. Fig. 8 is a flow chart showing the operation of the function test of the burn-in test performed by the burner system according to the modification of the embodiment of the present invention. The following steps can also be performed as a function test such as step S14 in the flowchart of Fig. 7. At this point, the mask settings will reflect the contact test results and the functional test results. Alternatively, the contact test results may not be reflected in the mask setting, and the following steps may be performed independently of the flowchart of Fig. 7. At this point, the mask settings reflect the functional test results. First, the output of the test pattern data is started by the test pattern output circuit 210 (step S20). Next, the test element selects the DUTs selected by the signals DSEL0 to DSEL79 (step S21). The test of step S21 will be described in detail below. For example, firstly, the 60-bit pre-burning board BIB is individually output by the component selection signal output circuit 220 to select the component selection signals DSEL0 to DSEL79 (first scanning) to select the second row and the fourth row of the A column. The first semiconductor wafer of the 8 test elements DUT of the 6th row, the 8th row, the 10th row, the 12th row, the 14th row, and the 16th row. Thereby, test pattern data is written to each memory cell of the first semiconductor wafer of each of the above-mentioned devices DUT. Next, the decision circuit 230 reads the round-out signal (ie, the written data) from the first 23 201217802 semiconductor wafer of the eight tested component DUTs, and determines whether the read output signal is related to the theoretical value ( That is, the test pattern data is consistent. Then, the test result recording unit 240 records the function test determination result of the determination circuit 230 as a function test result in advance. Here, for example, a section in which the number of memory cells in the 7-liter DUT is a predetermined number or more may be defined as a bad block, and the number of bad blocks is recorded as a function test result for each DUT under test. Then, the above test is repeated from the second semiconductor wafer to the fourth semiconductor wafer. Then, 'the first row, the third row, the fifth row, the seventh row, the ninth row, the eleventh row, the 13th row and the 15th row of the 8th column of the 60-piece pre-burning board BIB are individually selected. The first semiconductor wafer of the component DUT (second scan). Then, the same test was performed in the order preset by the program, and the test of 256 DUTs of each of the pre-burning plates BIB was terminated by 32 scans. Next, the output of the test pattern data is terminated by the test pattern output circuit 21 (step S22). Next, the function test result is read from the test result recording unit 240 by the mask setting circuit 250 (step S23). Then, it is judged by the test sequence control circuit 200 whether the function test has been completed (step S24)'. If it has ended (step S24: YES), the processing is terminated. If the function test has not been completed (step S24: NO), the mask setting circuit performs mask setting on the mask setting data in response to the read function test result (step S25). For example, the mask setting may be performed, and in the function test result, the DUT of the device to be tested having a predetermined number of bad blocks or more is specified as defective, and the DUT of the device under test is specified. As described above, the above-mentioned 24 201217802 mask setting can be automatically performed, for example, using a program. Next, the mask setting circuit 250 updates the mask setting memory 310 by the mask setting data masked in step S25 (step S26). Next, the output of the new test pattern data is started by the test pattern output circuit 210 (step S20). Then, the test element selects the device DUT selected by the signals DSEL0 to DSEL79 (step S21). Here, although the test is performed as described above, since the component selection signals DSEL0 to DSEL79 are not energized for the device under test DUT which is mask-set in step S25, no test is performed. Subsequent processing is the same as the aforementioned processing. As described above, according to the present modification, by setting the mask setting data to specify that the function test result is the defective device DUT, the above-mentioned device under test DUT can be excluded from the test object of the subsequent functional test. In this way, the functional test can be repeated without performing a functional test on the defective DUT, so that the test time can be shortened. Further, the present invention is not limited to the above embodiments, and various modifications can be made. For example, the internal structure of each of the above-described processing units is merely an example, and various modifications may be employed if the same processing can be realized. For example, the internal structure of the test control device 100 shown in Fig. 5 and the internal structure of the component selection signal output circuit 220 shown in Fig. 6 can be implemented in various modifications to achieve the same processing. Further, each of the processing units shown in the above embodiments is only a part of the description of the embodiment of the present invention. Therefore, the actual burning device 10 should be construed as adding the various 25 201217802 functional portions that are not present in the above-described drawings to the respective processing units. The various numerical values used in the above embodiments are merely illustrative, and the visual components are visible. The values of the DUT and the type of the test type data supplied are different, and various values are used. Further, in the above-described embodiment, the test component or the functional test is judged to be a component of the test object DU τ which is excluded from the test object, and the mask is set to be arbitrarily set. The DUT under test is excluded from the test object. In the above-described embodiment, the case where the DUT of the device under test includes four semiconductor wafers is described, but only the wafer semiconductor wafer or any number of semiconductor wafers may be included. In the example, the DUT is a NAND type shutter of the NAND type, but the other is a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a front elevational view of a burner apparatus of a firing machine system according to an embodiment of the present invention. Fig. 2 is a front view showing an internal structure example in a state in which a burn-in panel is placed in the burner unit of Fig. 1; Fig. 3 is a view showing a power month area of an example in which the internal structure of the control signal and the output signal is exchanged between the burning device and the other components in the burning device of Fig. 1. The drawing is a plan view of a pre-burning plate according to an embodiment of the present invention. Fig. 5 is a view showing the internal structure of the test control device of the present invention-embodiment. 26 201217802 The invention of the invention - the implementation of the component selection signal output power ★ 4 functional area diagram of one of the examples. The machine is tested and burned. (4) Burning performed by the system. Execution No. 8 is a flow chart showing the functional test action of the burn-in test set by the burner system of the modified example of the present invention. [Description of main component symbols] 10··· Burning machine 2020.. . Door panel 30.. Thermal insulation panel 40... Empty chamber 50···Groove 60...Heater 220···Component selection signal output circuit 230 ...determination circuit 240...test result recording unit 250...shield setting circuit 260...contact test execution circuit 300...element selection signal setting function circuit 70...cooling unit 310...shield setting memory 72...cooling compressor 320...logic circuit 74...heat Converter 80...fan 330...AND circuit 340...OR circuit 100...test control device 350...selector 110···buffer board “1”...input terminal 120...drive board “〇”...input terminal 130··· extension board "S"...selection terminal 140...insertion edge BIB...pre-burning board 200...test sequence control circuit/CE1 to 4... wafer enable terminal 210··· test pattern output circuit CL···control unit 27 201217802 CR... Enable···Enable signal Disable···Failure signal S10~S14, S20~S26... Flow step DSELO-DSEL79...Component selection signal SK...Socket DT···Air circulation pipe DUT···Measured component/WE ...write Enable terminal 28