201212741 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種印刷配線板用銅箔及使用其之積 層體，尤其係關於一種可撓性印刷配線板用銅箔及使用其 之積層體。 【先前技術】 印刷配線板歷於這半個世紀來發展快速，如今幾乎所 有電子設備中均有使用。隨著近年來對電子設備之小型 化、尚性能化之需求增大，搭載零件之高密度構裝化及訊 號之高頻化不斷進展，對印刷配線板要求導體圖案之微細 化（細間距化（fine pitch))或高頻對應等。 印刷配線板通常係經下述步驟來製造：將絕緣基板接 著於銅箔而製成積層體之後，藉由蝕刻於銅箔面形成導體 圖案。因此，要求印刷配線板用銅箔具有良好的蝕刻性。 若不對銅猪之與樹脂不接著之面實施表面處理，則蝕 刻後之銅猪電路的銅部分自銅猪表面朝下，亦 層逐漸擴展隸刻（產生壓陷）。通常會成為電路側之面 的角度較小的「壓陷」’尤其當產生較大的「壓陷」時， 亦有於樹脂基板附近發生㈣路短路而成^良品之情 形。此處，第4圖係表示於形成銅電路時產生「壓陷」而 在樹脂基板附近發生銅電路短路之―例的電路表面放0 片0 必須極力地減少此種「壓陷 伯 為了防止這種逐漸 擴展之钱刻不良’亦考慮有延長餘刻日丰p卩 守间’進行更多蝕刻， 201212741 、咸夕該Μ陷」。但是，&時將存在下述問題：當存在 達特定寬度尺寸之部位時’則該部位將會被進一步蝕 刻：故其銅fg部分的電路寬度會因而變窄，電路設計上無 法獲得所要之均—的線寬度（電路寬度），尤其是該部分 (被、’田線化之分）會發熱，有時會發生斷線。於進一步 推展電子電路之精細圖案化之過程中，目前因此種触刻不 良而引起之問題更嚴重，於電路形成上成為較大問題。 在專利文獻】中揭示有改善上述問題之方法，係於钮 刻面側之銅落形成飯刻速度比銅慢的金屬或合金層之表面 處理。此時之金屬或合金係Ni、c〇及其等之合金。於設計 電路時：由於飯刻液係自抗钮劑塗佈側，料_表面 開始次透’因’若於抗蝕劑正下方具有蝕刻速度較慢的 :屬或合金層，則可以抑制該金屬或合金層附近的鋼箱部 刀之蝕刻’而其他銅箔部分之蝕刻仍進行，因此能得到「壓 =」減少且可形成寬度更為均一之電路之效果，與先前技 V相比較可以形成較為㈣之電路’可謂之具有較大進步。 又’於專利文獻2中，形成厚度為1000〜10000Α之 CU薄膜，並於該CU薄膜上形成厚度為10〜300Α之蝕刻速 度比銅慢之Ni薄膜。 ^ 專利文獻1 :日本特開2002— 176242號公報 專利文獻2 :日本特開2〇〇〇_ 269619號公報 【發明内容】 ，需要 所記載 近年來，進-步發展電路之微細化及高密廣 具有側面傾斜更為㈣之電路、然而，專利文獻 4 201212741 之技術並不能滿足該等要求。 史二，專隹利文獻1所揭示之表面處理層，須藉由軟钱刻 來除去1而與樹脂之非接著面之表面處理銅荡在加工成 積層體之步驟中，須實施樹脂黏貼等高溫處理。這將引起 表面處理層氧化，結果導致銅笛蝕刻性劣化。 關於前者，為了縮短除去钱刻之時間，並較為乾淨地 除去’必須極力使表面處理層的厚度較薄，並且於後者之 情形下’因具有下述問冑，故須加以改良或替換為其他材 枓’該問題係··基底的鋼層因受熱而被氧化（由於會變色， 因此通稱為「燒痕」）’且抗蝕劑的塗佈'陘（均勻性、密 合性）不良或於㈣時界面氧化物過度㈣等導致發生圖 案餘刻的钱刻性、短路及雷政_安皆ώ 問題。 路及電路圖案寬度之控制性等不良之 /進而，專利文獻1和專利文獻2所揭示之表面處理層 係使用Ni或Co來形志，鈇；，丄M Α 木办珉然而廷將帶來Ni或Co會因其磁 性而對電子設備造成不良影響之擔憂。 因此，本發明的課題在於提供一種於形成電路圖案時 蝕刻性良好且適於細間距化、並且可良好地抑制磁性之印 刷配線板用銅荡及使用其之積層體。 本發明人等經潛心研究，結果發現在將包含鉑、鈀及 :之任-種以上之被覆層，以特定之金屬附著量設置於鋼 β之與樹脂不接著之面側之情形下，可形成電路側之面的 傾斜角為8〇0以上夕雷说。,, 上之電路藉此能夠形成可充分對應近年來 之電路微細化及高密度化之電路。 201212741 在基於以上見解而完成之本發明於一個態樣中，係提 供一種印刷配線板用銅箔，具備銅箔基材以及被覆層，該 被覆層被覆銅箔基材表面的至少一部分，並且該被覆層包 含姑、把及金之任一種以上，並且，被覆層中的麵附著量 為1050pg/dm2以下，把附著量為600pg/dm2以下，金附著 量為1000pg/dm2以下。 於本發明之印刷配線板用銅箔的一實施方式中，係被 覆層中的鉑附著量為20〜400pg/dm2，鈀附著量為2〇〜 250pg/dm2，金附著量為 20〜400pg/dm2。 於本發明之印刷配線板用銅箔的另一實施方式中，係 被覆層中的麵附著量為50〜300pg/dm2，纪附著量為3〇〜 180pg/dm2，金附著量為 50〜30(^g/dm2。 於本發明之印刷配線板用銅箔的又一實施方式中，係 印刷配線板為可撓性印刷配線板。 於本發明的又一方面，提供一種電子電路之形成方 法，包括下述步驟：準備由本發明銅箔所構成之壓延鋼箔 或電解銅落之步.驟；以銅箱的被覆層為姓刻面，製作銅羯 與樹脂基板之積層體之步驟；以及，利用氣化鐵水溶液^ 氣化銅水溶液對積層體進行蝕刻，除去不需要銅的部分來 形成銅電路之步驟。 於本發明的又一方面，提供一種積層體，係本發 銅4與樹脂基板之積層體。 t於本發明的又一方面，提供一種積層體，係銅層與樹 脂基板之積層體，其具備被覆銅層表面至少一部分之本發 6 201212741 明的被覆層。 ^ . $積層體的·'實施方式中，樹脂基板係聚酿亞 胺基板。 於本發明的x — .2SL α 一方面，提供一種印刷配線板，其係以 本發明積層體作為材料。 根據本發明，可 ^ ^ j Μ徒供一種在形成電路圖案時蝕刻性[Technical Field] The present invention relates to a copper foil for a printed wiring board and a laminated body using the same, and more particularly to a copper foil for a flexible printed wiring board and a laminated layer using the same body. [Prior Art] Printed wiring boards have developed rapidly over the past half century and are now used in almost all electronic devices. With the increase in the demand for miniaturization and performance of electronic devices, the high-density mounting of components and the high-frequency of signals have been progressing, and the wiring pattern is required to be fine-grained (fine pitch). (fine pitch)) or high frequency correspondence. The printed wiring board is usually produced by bonding an insulating substrate to a copper foil to form a laminated body, and then etching a copper foil surface to form a conductor pattern. Therefore, copper foil for printed wiring boards is required to have good etching properties. If the surface treatment of the copper pig and the resin is not carried out, the copper portion of the copper pig circuit after etching will face downward from the copper pig surface, and the layer will gradually expand (indentation). Usually, the "indentation" which is a small angle on the side of the circuit side is particularly good when a large "indentation" occurs, and a short circuit is formed in the vicinity of the resin substrate. Here, Fig. 4 shows that the surface of the circuit which is "indented" when the copper circuit is formed and the copper circuit is short-circuited in the vicinity of the resin substrate is placed on the surface of the circuit 0. This must be minimized. A kind of gradual expansion of the money is not bad. It is also considered to have extended the engraving of the Japanese feng feng 卩 卩 ' ' to carry out more etching, 201212741, the salty eve of the fall." However, & will have the following problem: when there is a part of a certain width dimension, then the part will be further etched: the circuit width of the copper fg portion will be narrowed, and the circuit design will not be able to obtain the desired The line width (circuit width) of the average—especially the part (the part of the 'field line') is hot, and sometimes the line breaks. In the process of further engraving the fine patterning of electronic circuits, the problems caused by such poorly-touched ones are more serious, and become a big problem in circuit formation. A method for improving the above problem is disclosed in the patent document, in which the copper drop on the facet side of the button forms a surface treatment of a metal or alloy layer having a slower cooking speed than copper. The metal or alloy at this time is an alloy of Ni, c〇, and the like. When designing the circuit: Since the rice engraving liquid is self-resisting on the coated side of the button, the surface of the material is permeable to the surface. If the etching layer has a slow etching rate: a genus or an alloy layer, it can be suppressed. The etching of the steel box knife near the metal or alloy layer is performed while the etching of the other copper foil portions is still performed, so that the effect of the "pressure =" reduction and the formation of a more uniform width circuit can be obtained, compared with the prior art V. The formation of a more (four) circuit can be said to have made great progress. Further, in Patent Document 2, a CU film having a thickness of 1000 to 10,000 Å is formed, and a Ni film having a thickness of 10 to 300 Å and an etching rate slower than that of copper is formed on the CU film. [Patent Document 1] JP-A-2002-176242 (Patent Document 2) Japanese Laid-Open Patent Publication No. Hei. No. 269 619. SUMMARY OF THE INVENTION In recent years, the development of the circuit has been further refined and high-density. A circuit having a side slope more (4), however, the technique of Patent Document 4 201212741 does not satisfy the requirements. Shi Er, the surface treatment layer disclosed in the patent document 1 must be removed by soft money to remove 1 and the surface of the non-adhesive surface of the resin is processed into a layered body, and resin bonding is required. High temperature treatment. This causes oxidation of the surface treatment layer, resulting in deterioration of copper etch resistance. Regarding the former, in order to shorten the time for removing the money, and to remove relatively cleanly, 'the thickness of the surface treatment layer must be made to be as thin as possible, and in the latter case', it is necessary to improve or replace it with other The problem is that the steel layer of the base is oxidized by heat (generally called "burn marks" due to discoloration) and the coating of the resist is not uniform (uniformity, adhesion) or At (4), the interface oxide is excessive (4), which leads to the engraving of the pattern, the short circuit and the Lei Zheng. The controllability of the width of the circuit and the circuit pattern is poor, and further, the surface treatment layer disclosed in Patent Document 1 and Patent Document 2 uses Ni or Co to shape, 鈇; Ni or Co may cause adverse effects on electronic equipment due to its magnetic properties. In view of the above, it is an object of the present invention to provide a laminate in which a copper wiring for a printed wiring board which is excellent in etching property and which is suitable for fine pitch and which can suppress magnetic properties and which is used. As a result of intensive studies, the present inventors have found that a coating layer containing at least one of platinum, palladium, and the like can be provided on the side of the steel β which is not adjacent to the resin with a specific amount of metal adhesion. The inclination angle of the surface on the side of the circuit is 8 〇 0 or more. In addition, the circuit can form a circuit that can sufficiently match the recent miniaturization and high density of the circuit. 201212741 In one aspect of the present invention based on the above findings, a copper foil for a printed wiring board is provided, comprising a copper foil substrate and a coating layer covering at least a portion of a surface of the copper foil substrate, and the coating layer The coating layer contains at least one of agglomerates, handles and gold, and the surface adhesion amount in the coating layer is 1050 pg/dm 2 or less, the adhesion amount is 600 pg/dm 2 or less, and the gold adhesion amount is 1000 pg/dm 2 or less. In one embodiment of the copper foil for a printed wiring board of the present invention, the platinum adhesion amount in the coating layer is 20 to 400 pg/dm 2 , the palladium adhesion amount is 2 〇 to 250 pg/dm 2 , and the gold adhesion amount is 20 to 400 pg / Dm2. In another embodiment of the copper foil for a printed wiring board according to the present invention, the surface adhesion amount in the coating layer is 50 to 300 pg/dm 2 , the adhesion amount is 3 〇 to 180 pg/dm 2 , and the gold adhesion amount is 50 to 30. (^g/dm2) In another embodiment of the copper foil for a printed wiring board of the present invention, the printed wiring board is a flexible printed wiring board. In still another aspect of the present invention, a method of forming an electronic circuit is provided And comprising the steps of: preparing a rolled steel foil or electrolytic copper formed by the copper foil of the present invention; and forming a laminate of the copper ruthenium and the resin substrate by using a coating layer of the copper box as a surname; A step of etching a laminate by using a vaporized iron aqueous solution, a vaporized copper aqueous solution, and removing a portion that does not require copper to form a copper circuit. In still another aspect of the present invention, a laminate is provided, which is a copper alloy 4 and a resin. In another aspect of the invention, there is provided a laminate comprising a laminate of a copper layer and a resin substrate, comprising a coating layer of at least a portion of the surface of the coated copper layer, wherein the coating layer of the present invention is disclosed in Japanese Patent Application No. 2012-12741. The realm of the layer In the embodiment, the resin substrate is a polyimide substrate. In the aspect of the invention, x-.2SL α provides a printed wiring board which is a material of the laminate of the present invention. According to the present invention, it is possible to Etch for etching when forming a circuit pattern
良好且適於細間阳外 W 匕、並且可良好地抑制磁性之印刷配線 板用銅羯及使用其之積層體。 【實施方式】 (銅箔基材） 可用於本發明之銅羯基材的形態並無特別限制，典型 而言可以屋延銅落或電解銅羯之型態來使用。"，電解 銅猪係將銅自4酸銅鑛浴電解析出至欽或不鏽鋼的滾筒 ⑷㈣上銅而製造，壓延銅“反覆進行㈣壓延心㈣ 加工和熱處理來製造。多將壓延銅落用於要求彎曲性之用 途。 銅羯基材的材料，除了通常用作印刷配線板導體圖案 之韌煉銅、無氧銅等高純度銅以外’例如亦可使用·摻雜A copper beryllium for a printed wiring board which is excellent in a fine outer space and which is excellent in magnetic properties, and a laminated body using the same. [Embodiment] (Copper foil base material) The form of the copper-ruthenium base material which can be used in the present invention is not particularly limited, and it is typically used in the form of a copper or electrolytic copper crucible. ", electrolytic copper pig system from the 4 acid copper ore bath analysis to the Qin or stainless steel drum (4) (four) on the copper, the rolling copper "repeated (four) rolling heart (four) processing and heat treatment to manufacture. More will be rolled copper For use in applications requiring bendability. The material of the matte base material is not limited to high-purity copper such as toughened copper or oxygen-free copper which is usually used as a conductor pattern of a printed wiring board.
Sn之銅、摻雜Ag之銅以及如添加有心心或瞬等之銅 合金、添加有Ni和Si等之卡遜系銅合金之類的銅合金。另 外’於本說明書中，當單獨使用術語「銅落」時，亦包含 銅合金箔。 可用於本發明之銅猪基材的厚度亦並無特別限制，只 要適度調節為適合用於印刷配線板之厚度即可例如 7 201212741 以為5〜左右。其中，於以形成精細圖案為目的之情 形下為30μηι以下，較佳為2〇μιη以下典型為$〜2〇叫左 用於本發明之銅落基材並無特別限制，例士。，亦可使 用未經粗化處理之銅基材。先前，冑常為如下情況：利 用特殊鑛敷於表面附上㈣、級之凹凸，而實施表面粗化處 理’藉由物理性的定準效應使銅羯基材具有與樹脂間之接 者性’然而’ S 一方面’就細節距或高頻電氣特性而言， 平滑之箔較好，而粗化箔會朝不利方向起發展。又，若為 未經粗化處理之銅箔基材，則由於粗化處理步驟被省略而 具有提高經濟性和生產性之效果。 (被覆層的構成） 於銅猪基材之與絕緣基板接著之面的相反側（預定形 成電路之面側）的表面至少一部分，形成有被覆層。被覆 層包含鉑、鈀及金之任丨種以上。於由鉑構成被覆層之情 形下’始附著量為1〇5〇Pg/dm2以下’較佳為2〇〜 4〇〇Mg/dm，更佳為5〇〜3〇〇pg/dm2。於由Ιε構成被覆層之 情形下’把附著量為6〇〇pg/dm2以下’較佳為20〜 250pg/dm ，更佳為3〇〜1 8〇pg/dm2。於由金構成被覆層之 情形下’金附著量為1〇〇〇Mg/dm2以下，較佳為2〇〜 400pg/dm 更佳為50〜300pg/dm2。若被覆層的翻附著量 超過1050pg/dm2、被覆層的鈀附著量超過6〇〇μ§/ί1ηι2以及 被覆層的金附著量超過1 〇〇〇(Xg/dm2 ’將分別對初期银刻性 造成不良影響。 8 201212741 (銅箔的製造方法） +發月的印刷配線板用銅箔可藉由濺鍍法形成。亦 即上’藉由濺錄法，利用被覆層來被覆銅荡基材表面的至少 p刀具體而§，係藉由濺鍵法，於銅箱的#刻面側形 成被覆層，該被覆層係由選自由姓刻速率比銅低之銘族金 屬金及銀所構成之群中的一種所構成。被覆層並不限於 藉由賤鑛法來形成’亦可利用例如電鑛、&電鍵等濕式鑛 敷法而形成。 (印刷配線板的製造方法） 可使用本發明的銅落根據常用方法來製造印刷配線板 (PWB)。以下舉出印刷配線板的製造方法之例。 卜首先，貼合銅羯與絕緣基板來製造積層體。積層有銅 治之絕緣基板，只要具有適用於印刷配線板之特性，則並 無特別限制，例如，用於剛性pwB時，可使用紙基材盼樹 脂、紙基材環氧樹脂、合成纖維布基材環氧樹脂、玻璃布 -紙複σ基材環氧樹脂、玻璃布一玻璃不織布複合基材環 氧樹脂及玻璃布基材環氧樹脂等，用於Fpc時，可使用聚 醋膜或聚醢亞胺臈等。 關於貼合之方法，在用於剛性PWB之情形下，準備以 下之預浸體：將樹脂含浸於玻璃布等基材中，且使樹脂硬 化至半硬化狀態為止。可將銅箔自被覆層的相反側之面重 疊於預浸體’並進行加熱加壓，藉此進行貼合。 在用於可撓性印刷配線板（FPC)之情形下，可使用環氧 系或丙烯酸系接著劑來將聚醯亞胺膜或聚酯膜與銅箔接著 9 201212741 (3層結構）。又，不使用接著劑之方法（2層結構），可 以列舉：澆鑄法’將作為聚醯亞胺之前驅物之聚醢亞胺清 漆（聚醢胺酸（polyamic acid)清漆）塗佈於銅箔，並透過加 熱而酿亞胺化；或積層法，於聚醯亞胺膜上塗佈熱塑性之 聚醯亞胺’並於其上疊合銅箔，並進行加熱加壓。於淺鑄 法中，在塗佈聚醯亞胺清漆之前’預先塗佈熱塑性聚醢亞 胺等猫固塗層（anchor coat)材料亦極為有效。 本發明的積層體可用於各種印刷配線板（PWB)，並無特 別限制，例如，就導體圖案的層數之觀點而言，可應用於 單面PWB、雙面PWB及多層PWB ( 3層以上），就絕緣基 板材料的種類之觀點而言，可應用於剛性PWB、可撓性PWB (FPC)及剛性一可撓性PWB中。又，本發明的積層體，並 不限定於將銅箔貼附於樹脂上而形成之上述覆銅積層板， 亦可為利用濺鍍、鍍敷而於樹脂上形成銅層之金屬喷敷材 料。 將形成有下述結構之積層體浸潰於蝕刻液中，該結構 係：在形成於以上述方法製作之積層體的銅箔上之被覆層 表面塗佈抗蝕劑，且藉由遮罩曝光圖案，藉由顯影形成抗 钱劑圖案。此時’選自由抑制蝕刻之鉑族金屬、金及銀所 構成之群中的1種所構成之被覆層，係位於銅箔上靠近抗 触劑部分之位置，抗蝕劑側之銅箔之蝕刻，係以比該被覆 層附近被蝕刻之速度更快之速度，對遠離被覆層之部位之 銅進行姓刻’藉此銅的電路圖案之触刻係大致垂直地進 行。藉此可除去不需要銅的部分，繼而剝離/除去蝕刻抗蝕 10 201212741 劑，露出電路圖案。 相對於用以在積層體形成電路圖案之蝕刻液’被覆層 的蝕刻速度充分小於銅，因此，具有改善蝕刻因數之效果。 蝕刻液可使用氣化銅水溶液或氣化鐵水溶液等，但氯化鐵 水溶液尤其有效。其原因在於：微細電路的蝕刻需要花費 時間，而氯化鐵水溶液的蝕刻速度比氣化銅水溶液快。又， 於形成被覆層之前，亦可預先於銅箔基材表面形成耐熱層。 [實施例] 以下，舉出本發明的實施例，提供這些實施例係為了 更好地理解本發明，其意圖並非在於限定本發明。 (例1 :實施例1〜3 3 ) (於銅箔形成被覆層） 準備厚度為12或17μηι的壓延銅箔（曰礦金屬製造 ci 1〇〇)來作為實施例21和實施例25〜3〇的銅箔基材。 壓延銅羯的表面粗糙度（Rz)為〇.7μιη。又，準備厚度為9μ〇ι 之未經粗化處理之電解銅箔來作為實施例22〜24的銅箔基 材。電解銅馆的表面粗糙度（尺幻為15μπι。進而，準備厚度 為8μιη之金屬噴敷CCL (曰礦金屬製造爪盹丨仙⑶，銅層側 Ra為〇.〇ΐμηι ’連結塗層的金屬附著量川為178〇叫My ’ Cr為36(^g/dm2)來作為實施例31〜33的銅箔基材。 藉由逆向濺鍍去掉附著於銅箔表面之薄氧化膜，並利 用以下裝置及條件對Au、pt及/或pd之靶進行濺鍍，藉此 形成被覆層。被覆層的厚度可藉由調整成膜時間而變化。 满1鑛所使用之各種金屬的單體係使用純度為3N者。 201212741 •裝置：批次式濺鍍裝置（ULVAC公司，型號MNS _ 6000 )Copper of Sn, copper doped with Ag, and a copper alloy such as a copper alloy to which a heart or an instant is added, or a Cason copper alloy to which Ni and Si are added. Further, in the present specification, when the term "copper drop" is used alone, a copper alloy foil is also included. The thickness of the copper pig substrate which can be used in the present invention is also not particularly limited, and it can be appropriately adjusted to a thickness suitable for a printed wiring board, for example, 7 201212741, which is about 5 Å. Among them, in the case of forming a fine pattern, it is 30 μηι or less, preferably 2 μm μη or less, and typically $2 to 2, which is not particularly limited, and is used in the present invention. It is also possible to use a copper substrate which has not been roughened. Previously, it was often the case that a special mineral deposit was applied to the surface (4), the unevenness of the grade, and the surface roughening treatment was carried out. 'The copper crucible substrate has a connection with the resin by the physical quasi-alignment effect. 'However' S On the one hand, in terms of fine pitch or high-frequency electrical characteristics, smooth foil is better, and roughened foil will develop in an unfavorable direction. Further, in the case of the copper foil substrate which is not subjected to the roughening treatment, the roughening treatment step is omitted, and the effect of improving economy and productivity is enhanced. (Structure of Coating Layer) A coating layer is formed on at least a part of the surface of the copper pig substrate opposite to the surface on the subsequent surface of the insulating substrate (the side on which the circuit is to be formed). The coating layer contains more than one of platinum, palladium and gold. In the case where the coating layer is composed of platinum, the initial adhesion amount is 1〇5〇Pg/dm2 or less', preferably 2〇~4〇〇Mg/dm, more preferably 5〇~3〇〇pg/dm2. In the case where the coating layer is composed of Ι ε, the amount of adhesion is 6 〇〇pg/dm 2 or less, preferably 20 to 250 pg/dm, more preferably 3 〇 to 18 〇 pg/dm 2 . In the case where the coating layer is composed of gold, the amount of gold adhered is 1 〇〇〇Mg/dm 2 or less, preferably 2 〇 to 400 pg/dm or more preferably 50 to 300 pg/dm 2 . If the coating layer is over 1050pg/dm2, the palladium adhesion of the coating layer exceeds 6〇〇μ§/ί1ηι2, and the gold adhesion of the coating layer exceeds 1 〇〇〇 (Xg/dm2 ' will be the initial silver score. 8 201212741 (Manufacturing method of copper foil) + The copper foil for printed wiring boards of the moon can be formed by sputtering. That is, the coating layer is used to coat the copper substrate by the sputtering method. At least the p-knives of the surface are specifically formed by the sputtering method to form a coating layer on the # facet side of the copper box, the coating layer being composed of the inscription metal gold and silver selected from the lower than the copper. One of the groups is formed. The coating layer is not limited to being formed by the bismuth ore method. It can also be formed by a wet ore method such as electric ore, & electric key. (Manufacturing method of printed wiring board) The copper slab of the present invention is manufactured by a usual method. The following is an example of a method for producing a printed wiring board. First, a copper iridium and an insulating substrate are bonded to each other to produce a laminated body. As long as it has a special feature for printed wiring boards The nature is not particularly limited. For example, when used for rigid pwB, paper substrate resin, paper substrate epoxy resin, synthetic fiber cloth substrate epoxy resin, glass cloth-paper complex σ substrate epoxy can be used. Resin, glass cloth, glass non-woven composite substrate epoxy resin, glass cloth substrate epoxy resin, etc. When used for Fpc, polyacetal film or polyimine oxime, etc. can be used. In the case of rigid PWB, the following prepreg is prepared: the resin is impregnated into a substrate such as glass cloth, and the resin is cured to a semi-hardened state. The copper foil can be superposed on the opposite side of the coating layer from the prepreg. The body' is heated and pressed to bond it. In the case of a flexible printed wiring board (FPC), an epoxy-based or acrylic-based adhesive can be used to laminate the polyimide film or polyester. The film and the copper foil are followed by 9 201212741 (three-layer structure). Further, the method of using no adhesive (two-layer structure) can be exemplified by the casting method, which is a polyimine varnish which is a precursor of polyimine. Polyamic acid varnish) coated on copper foil Heating and brewing imidization; or laminating method, coating thermoplastic polyimide on the polyimide film and laminating the copper foil thereon, and heating and pressurizing. In the shallow casting method, coating It is also extremely effective to pre-coat a cat coat material such as a thermoplastic polyimine before the phthalimide varnish. The laminate of the present invention can be used for various printed wiring boards (PWB) without particular limitation. For example, from the viewpoint of the number of layers of the conductor pattern, it can be applied to a single-sided PWB, a double-sided PWB, and a multilayer PWB (three or more layers), and can be applied to a rigid PWB from the viewpoint of the type of the insulating substrate material. In the flexible PWB (FPC) and the rigid-flexible PWB, the laminated body of the present invention is not limited to the copper-clad laminate formed by attaching a copper foil to a resin, and may be sputtered. A metal spray material which is plated to form a copper layer on the resin. The layered body having the following structure is formed by applying a resist to the surface of the coating layer formed on the copper foil of the layered body produced by the above method, and exposing it by masking The pattern is formed by development to form an anti-money agent pattern. At this time, the coating layer composed of one selected from the group consisting of platinum group metals, gold, and silver which are suppressed from etching is located on the copper foil near the anti-contact agent portion, and the copper foil on the resist side. The etching is carried out at a speed faster than the etching of the vicinity of the coating layer, and the copper of the portion away from the coating layer is etched by the circuit pattern of the copper. Thereby, the portion not requiring copper can be removed, and then the etching resist 10 201212741 can be peeled off/removed to expose the circuit pattern. The etching rate with respect to the etching liquid coating layer for forming a circuit pattern in the laminated body is sufficiently smaller than that of copper, and therefore has an effect of improving the etching factor. As the etching liquid, a vaporized copper aqueous solution or an aqueous solution of iron oxide or the like can be used, but an aqueous solution of ferric chloride is particularly effective. The reason for this is that etching of the fine circuit takes time, and the aqueous solution of ferric chloride is etched faster than the aqueous solution of vaporized copper. Further, a heat-resistant layer may be formed in advance on the surface of the copper foil substrate before the formation of the coating layer. [Examples] The following examples are given to illustrate the present invention and are not intended to limit the invention. (Example 1: Examples 1 to 3 3) (Formation of a coating layer on a copper foil) A rolled copper foil (manufactured by bismuth ore metal) having a thickness of 12 or 17 μm was prepared as Example 21 and Examples 25 to 3 A copper foil substrate. The surface roughness (Rz) of the rolled matte is 〇.7 μιη. Further, an electrolytic copper foil having a thickness of 9 μm without roughening was prepared as the copper foil substrate of Examples 22 to 24. The surface roughness of the electrolytic copper pavilion is 15μπι. Further, the metal sprayed CCL with a thickness of 8μιη (the 盹丨 金属 金属 ( 3 3 , , , , , , , , , , , , , , 3 3 3 3 3 3 3 3 3 3 3 3 〇ΐ 〇ΐ 〇ΐ 〇ΐ 〇ΐ 〇ΐ 〇ΐ 〇ΐ 〇ΐ 〇ΐ The adhesion amount was 178, and My 'Cr was 36 (^g/dm2) as the copper foil substrate of Examples 31 to 33. The thin oxide film adhering to the surface of the copper foil was removed by reverse sputtering, and the following was utilized. The device and conditions are sputtered on the targets of Au, pt and/or pd to form a coating layer. The thickness of the coating layer can be changed by adjusting the film formation time. The single system of various metals used in Man 1 Mine is used. The purity is 3N. 201212741 • Installation: batch sputtering device (ULVAC, model MNS _ 6000)
•極限真空（ultimate vacuum) : l.〇x10-5pa •濺鍍壓：0.2Pa •逆向濺鍍功率：100w •濺鍍功率：50W •成膜速度：針對各靶經一定時間成膜約〇.2pm，用三 維測定器測定厚度，計算出每單位時間的濺鍍速率。 乾：AU—50 質量。/〇Pd、Pt—50 質量 ％Pd 及 Au—5〇 質 於上述實施例中，實施例28〜30使用了以下靶 量％Pt 〉成有上述被覆層之表面之相反側的銅箔基材表 :之以下條件藉由逆向濺鑛預先將附著於銅羯基材表 此依次使去掉，並對心&單層之^進行濺鍍，藉 整成〜層成膜^層和^層的厚度可藉由調 怎取犋時間而變化。 • 裝署 . 6000 ) 欠式贿裝置（ULVAC公司，錢屬― 極限真空：1 .〇x 10- 5Pa •濺鍍壓：0.2pa 逆向溅鍍功率：100 w •把： 1層用=Ni (純度為3N)• ultimate vacuum: l.〇x10-5pa • Sputtering pressure: 0.2Pa • Reverse sputtering power: 100w • Sputtering power: 50W • Film formation speed: film formation for each target over a certain period of time. At 2 pm, the thickness was measured with a three-dimensional measuring device, and the sputtering rate per unit time was calculated. Dry: AU-50 quality. / 〇 Pd, Pt - 50% by mass of Pd and Au - 5 enamel in the above examples, Examples 28 to 30 used the following target amount % Pt > copper foil substrate having the opposite side of the surface of the above coating layer Table: The following conditions are previously attached to the copper matte substrate by reverse sputtering, which are sequentially removed, and the core & single layer is sputtered, and the layer is formed into a layer and a layer. The thickness can be varied by how to adjust the time. • Installation. 6000) Under-bribery device (ULVAC, money ― ultimate vacuum: 1. 〇x 10- 5Pa • Sputtering pressure: 0.2pa Reverse sputtering power: 100 w • Put: 1 layer with = Ni ( Purity is 3N)
Cr層用""Cr (純度為3N) 12 201212741Cr layer with ""Cr (purity 3N) 12 201212741
•濺鍍功率：5〇W •成膜速度：針對各靶經一定時間成膜約0.2μπι，用三 維測定器測定厚度’計算出每單位時間的濺鍍速率。 按照以下順序’將聚醯亞胺膜接著於銅箔基材之Ni層 和Cr層形成側表面^ (1) 使用塗佈器，對7cmx7cm之銅箔以乾燥體達25μιη 之方式塗佈宇部興產製造的UVarnish—A(聚醯亞胺清漆 (2) 將由（1)所得之附有樹脂之銅箔於空氣下使用乾燥機 以130°C乾燥30分鐘。 (3) 於氮机量设為1 〇L/miη之高溫加熱爐中，以3 5 〇。〇進 行酿亞胺化3 0分鐘。 <附著量的測定> 被覆層的Au、Pd及Pt的附著量測定，係利用王水將 表面處理銅箔樣本溶解，稀釋該溶解液，藉由原子吸光分 析法來進行。 (藉由姓刻而形成之電路形狀） 藉由於銅箔之形成有被覆層之面塗佈感光性抗蝕劑及 進行曝光步驟而印刷10條電路，進而根據以下條件來實施 除去不需要銅的部分之敍刻處理。 <蝕刻條件> •氯化鐵水溶液：（37wt%、波美度：40。） •，液溫：50°C •喷壓：0.25MPa (形成間距為50μιη之電路） 13 201212741 •抗钮劑 L/s = 33pm/17pm •完成電路下部（底部）宽度：25μηι •姓刻時間：1 0〜1 3 0秒 (形成間距為3〇μιη之電路） •抗姓劑 L/S=2^m/^m •完成電路下部（底部）宽度：15μπι •姓刻時間：30〜7〇秒 •触刻終點之確認：改變時間，按多個標準進行蝕刻， 利用光學顯微鏡確認銅未殘留於電路之間，該時間即為蝕 刻時間。 分 蝕刻後，於45勺的NaOH水溶液（100g/L)中浸潰 鐘’剝離抗飿劑。 <钱刻因數的測定條件> 蝕刻因數係用來表示下述a與銅箔厚度b之比b/ a， 該a係表示逐漸展開蝕刻時（產生壓陷時）、以及假設電路 垂直蝕刻時之來自銅箔上面的垂線與樹脂基板之交點開始 之壓陷長度的距離，該b/a數值越大，意味著傾斜角變得 越大’無触刻殘潰殘留’壓陷變小。_ i係表示部分電路 圖案的表面照，、該部分中的電路圖案的寬度方向橫剖面 不意圖及使用該示意圖之㈣因數計算方法之概略。該玨• Sputtering power: 5 〇 W • Film forming speed: The sputtering rate per unit time was calculated by filming about 0.2 μm for each target over a certain period of time and measuring the thickness by a three-dimensional measuring device. In the following order, the polyimide film was formed on the side of the Ni layer and the Cr layer of the copper foil substrate. (1) Using a coater, a 7 cm x 7 cm copper foil was coated in a dry body up to 25 μm. Produced UVarnish-A (polyimide varnish (2) The resin-attached copper foil obtained in (1) was dried at 130 ° C for 30 minutes using a dryer under air. (3) The nitrogen amount was set to 1 In a high-temperature heating furnace of 〇L/miη, it was subjected to amination for 30 minutes at 3 5 Torr. <Measurement of adhesion amount> Measurement of the adhesion amount of Au, Pd and Pt of the coating layer Water dissolves the surface-treated copper foil sample, dilutes the solution, and performs the atomic absorption spectrometry. (The shape of the circuit formed by the surname) The photosensitive surface is coated by the surface of the coating layer formed by the copper foil. The etching process and the exposure step were carried out to print 10 circuits, and the etching process for removing the portion not requiring copper was carried out according to the following conditions. <Etching conditions> • Aqueous ferric chloride solution: (37 wt%, Baume: 40 .) •, liquid temperature: 50 ° C • spray pressure: 0.25 MPa (formation of 50 μιη spacing) 13 201212741 • Anti-button agent L/s = 33pm/17pm • Finished circuit lower (bottom) width: 25μηι • Last minute: 1 0~1 3 0 seconds (formation of a pitch of 3〇μιη) • Anti-surname L/S=2^m/^m • Complete the lower part of the circuit (bottom) Width: 15μπι • Last minute time: 30~7〇 seconds • Confirmation of the end point of the touch: change the time, etch according to multiple standards, use optical microscope It is confirmed that copper does not remain between the circuits, and this time is the etching time. After the partial etching, the bell's peeling anti-caries agent is immersed in 45 scoops of NaOH aqueous solution (100 g/L). <Measurement conditions of the money engraving factor> The etching factor is used to indicate the ratio b/a of the following a to the thickness b of the copper foil, which indicates the gradual unfolding of the etch (when the embossing occurs), and the vertical line from the copper foil when the circuit is vertically etched. The distance from the intersection of the resin substrate to the indentation length, the larger the b/a value, means that the inclination angle becomes larger, and the "no-touch residual residue" becomes smaller. _ i indicates the surface of a part of the circuit pattern. Photo, the widthwise cross section of the circuit pattern in this part (Iv) the factor and the use intended schematic outline of the method of calculation. The Jue
係自電路上方藉由SEM觀察來測宗，曾山A 恍弁、木凋疋，计算出蝕刻因數（EF=b a) °藉由使用該飯刻因數，可饍 J M間早地判斷出蝕刻性之良 否。進而’傾斜角θ係藉由利用按 馆认厂 π用刼照上述順序測定之a及銅 /白的厚度b來計算反正切而算出。 ^ 出〃測疋範圍係電路長為 201212741 600μπι ’ 12點蝕刻因數 ^ 妹用其標準偏差和傾斜角 均值作為結果。 (例2，.比較例1〜3 :胚料） 準備12μιη厚、17叫厚及9μιη厚之壓延銅箱，分別按 照與例1相同的順序接著聚醯亞胺膜。繼而於相反面藉由 塗佈感光性抗蝕劑及進行曝光步驟來印刷1〇條電路，進而 以例1之條件實施除去不需要銅羯的部分之蝕刻處理。 (例3 :比較例4〜6 ) 準備厚度為12μιη之壓延銅箔，按照與例i相同的順序 接著聚醯亞胺膜。繼而，與例丨相同地於銅箔表面藉由濺 鍍來形成Au、Pd及/或Pt之各層’利用蝕刻形成電路。 例1〜3的各測定結果如表丨〜4所示。 15 201212741 [表i] 銅箱 附著量(pg/dm2) 厚度(μιη) 種類 Au Pt Pd 實施例1 12 壓延 8 實施例2 14 — — 實施例3 36 — — 實施例4 53 — — 實施例5 283 — — 實施例6 359 — — 實施例7 784 — — 實施例8 4 實施例9 — 17 — 實施例10 — 31 — 實施例11 — 58 — 實施例12 — 291 — 實施例13 — 382 — 實施例14 — 891 — 實施例15 5 實施例16 — — 12 實施例17 — — 26 實施例18 — — 41 實施例19 — — 173 實施例20 — — 227 實施例21 — — 577 實施例22 9 電解 271 — — 實施例23 282 — 實施例24 — — 162 實施例25 17 壓延 266 — — 實施例26 — 293 — 實施例27 — — 170 實施例28 12 壓延 501 — 403 實施例29 一 471 262 實施例30 528 304 — 實施例31 8 金屬喷敷CCL 159 — — 實施例32 — 166 — 實施例33 — — 73 16 201212741 [表2] 50μιη間距 (L/S=3 3 μπι/17 μπι) 30μπα間距 (L/S=25pm/5pm) 蝕刻因數 傾斜角 (°) 蝕刻因數 傾斜角 (。） 平均值 標準偏差 平均值 標準偏差 實施例1 2.7 0.2 70 1.6 0.1 58 實施例2 6.8 0.1 82 2.5 0.1 68 實施例3 7.9 0.1 83 3.1 0.2 72 實施例4 8.7 0.2 83 4.2 0.2 77 實施例5 11 0.3 85 5.4 0.4 80 實施例6 9.6 0.5 84 4.7 0.7 78 實施例7 8.8 0.8 84 4.2 1.1 77 實施例8 3.0 0.5 72 1.7 0.1 60 實施例9 7.1 0.1 82 2.6 0.1 69 實施例10 7.8 0.1 83 3.2 0.1 73 實施例11 8.9 0.1 84 4.3 0.3 77 實施例12 11 0.2 85 5.6 0.3 80 實施例13 11 0.4 85 5.1 0.5 78 實施例14 8.5 0.9 83 3.9 1.0 76 實施例15 3.4 0.3 74 1.7 0.1 60 實施例16 7.1 0.1 82 2.5 0.1 68 實施例17 7.8 0.2 83 3.0 0.2 72 實施例18 8.9 0.2 84 4.3 0.3 77 實施例19 11 0.2 85 5.4 0.4 80 實施例20 11 0.4 85 5.6 0.6 77 實施例21 8.4 0.8 83 4.0 1.3 76 實施例22 11 0.3 85 5.5 0.4 80 實施例23 11 0.2 85 5.4 0.4 80 實施例24 11 0.3 85 5.8 0.3 80 實施例25 8.5 0.2 83 3.5 0.4 74 實施例26 8.6 0.3 83 3.3 0.3 73 實施例27 9.0 0.3 84 3.8 0.4 75 實施例28 7.7 0.4 83 2.6 0.5 69 實施例29 7.8 0.4 83 2.5 0.5 68 實施例30 7.8 0.5 83 2.5 0.5 68 實施例31 11 0.1 85 5.8 0.1 80 實施例32 11 0.1 85 5.9 0.2 80 實施例33 11 0.2 85 6.1 0.3 81 17 201212741 [表3] 銅结 附著量(pg/dm2) 厚度(μιη) 種類 Au Pt Pd 比較例1 12 壓延 — — — 比較例2 17 壓延 — — — 比較例3 9 電解 — — — 比較例4 12 壓延 1102 — — 比較例5 12 壓延 一 1111 — 比較例6 12 壓延 — — 766 [表4] 50μιη間距 (L/S=3 3 μηι/17 μιη) 30μηι間距 (L/S:25pm/5pm) 蝕刻因數 傾斜角(°) 蝕刻因數 傾斜角(°) 平均值 標準偏差 平均值 標準偏差 比較例1 1.7 0.3 60 1.6 0.0 58 比較例2 1.8 0.2 61 * 氺 * 比較例3 1.8 0.2 61 1.6 0.0 58 比較例4 8.3 2.1 83 氺幸 比較例5 8.0 1.9 83 *氺 比較例6 7.9 2.1 83 *伞 ** 氺孝 * :電路上部未殘留，因此無法計算。 * * :初始触刻性較差，無法計算。 再者，如圖2(b)所示，電路的剖面形狀，精確地說並 非斜邊為直線之梯形。於表2和表4中，記載有實施例和 比較例的電路的傾斜角，但這不過為藉由圖1所示之定義 式計算出之值。 (評價） 18 201212741 (實施例1〜3 3 ) 貫施例1〜3 3均可形成飯刻因數較大且無不均、並且 剖面近似於矩形方狀之電路。 圖2係表示根據實施例2 7所形成之電路的照片及其剖 面照片。 (比較例1〜6 ) 比較例1〜3分別為銅箔表面未經處理之胚料，未能形 成刮面為矩形方狀之電路。 於比較例4〜6中，鉑附著量超過105(^g/dm2，鈀附著 量超過60(^g/dm2或者金附著量超過100(^g/dm2，因此， 未能形成剖面為矩形方狀之電路。此處，作為一例，圖3 係表示根據比較例6所形成之電路的照片。 【圖式簡單說明】 圖1 :係表示部分電路圖案的表面照片、該部分中的電 路圖案的寬度方向之橫剖面示意圖及使用該示意圖之蝕刻 因數（Etching factor; EF)之概略計算方法。 圖2 .係表示根據實施例27所形成之電路及其剖面之 照片。 圖3 .係表示根據比較例6所形成之電路之照片。 圖4’係表示於形成銅電路時產生「壓陷」而在樹脂基 板附近發生銅電路短路之一例的電路表面放大照片。 【主要元件符號說明】 無 19It is measured by SEM observation from the top of the circuit, Zengshan A 恍弁, wood withered, calculate the etching factor (EF = ba) ° By using the cooking factor, the etchability is judged early in the meal JM Good or not. Further, the "tilt angle θ" is calculated by calculating the arctangent by using the thickness a of the copper and white measured in the above-described order by the factory π. ^ The range of the measurement range is 201212741 600μπι ′ 12-point etch factor ^ The average value of the standard deviation and the tilt angle is used as the result. (Example 2, Comparative Examples 1 to 3: Blanks) A rolled copper box having a thickness of 12 μm thick and a thickness of 17 μm and a thickness of 9 μm was prepared, and the polyimide film was subsequently laminated in the same order as in Example 1. Then, on the opposite side, a one-shot circuit was printed by applying a photosensitive resist and an exposure step, and an etching treatment for removing a portion not requiring a copper bead was carried out under the conditions of Example 1. (Example 3: Comparative Examples 4 to 6) A rolled copper foil having a thickness of 12 μm was prepared, and the polyimide film was next placed in the same order as in Example i. Then, in the same manner as in the example, each layer of Au, Pd, and/or Pt is formed by sputtering on the surface of the copper foil, and an electric circuit is formed by etching. The measurement results of Examples 1 to 3 are shown in Tables 1-4. 15 201212741 [Table i] Copper box adhesion amount (pg/dm2) Thickness (μιη) Type Au Pt Pd Example 1 12 Calendering 8 Example 2 14 - Example 3 36 - Example 4 53 - Example 5 283 - Example 6 359 - Example 7 784 - Example 8 4 Example 9 - 17 - Example 10 - 31 - Example 11 - 58 - Example 12 - 291 - Example 13 - 382 - Implementation Example 14 - 891 - Example 15 5 Example 16 - 12 Example 17 - 26 Example 18 - 41 Example 19 - 173 Example 20 - 227 Example 21 - 577 Example 22 9 Electrolysis 271 - Example 23 282 - Example 24 - 162 Example 25 17 Calender 266 - - Example 26 - 293 - Example 27 - 170 Example 28 12 Calender 501 - 403 Example 29 - 471 262 Example 30 528 304 - Example 31 8 Metal Spray CCL 159 - Example 32 - 166 - Example 33 - 73 16 201212741 [Table 2] 50 μm pitch (L/S = 3 3 μπι / 17 μπι) 30 μπα pitch ( L/S=25pm/ 5pm) Etch factor tilt angle (°) Etch factor tilt angle (.) Mean standard deviation mean standard deviation Example 1 2.7 0.2 70 1.6 0.1 58 Example 2 6.8 0.1 82 2.5 0.1 68 Example 3 7.9 0.1 83 3.1 0.2 72 Example 4 8.7 0.2 83 4.2 0.2 77 Example 5 11 0.3 85 5.4 0.4 80 Example 6 9.6 0.5 84 4.7 0.7 78 Example 7 8.8 0.8 84 4.2 1.1 77 Example 8 3.0 0.5 72 1.7 0.1 60 Example 9 7.1 0.1 82 2.6 0.1 69 Example 10 7.8 0.1 83 3.2 0.1 73 Example 11 8.9 0.1 84 4.3 0.3 77 Example 12 11 0.2 85 5.6 0.3 80 Example 13 11 0.4 85 5.1 0.5 78 Example 14 8.5 0.9 83 3.9 1.0 76 Example 15 3.4 0.3 74 1.7 0.1 60 Example 16 7.1 0.1 82 2.5 0.1 68 Example 17 7.8 0.2 83 3.0 0.2 72 Example 18 8.9 0.2 84 4.3 0.3 77 Example 19 11 0.2 85 5.4 0.4 80 Example 20 11 0.4 85 5.6 0.6 77 Example 21 8.4 0.8 83 4.0 1.3 76 Example 22 11 0.3 85 5.5 0.4 80 Example 23 11 0.2 85 5.4 0.4 80 Example 24 11 0.3 85 5.8 0.3 80 Example 25 8.5 0.2 83 3.5 0.4 74 Example 26 8.6 0.3 83 3.3 0. 3 73 Example 27 9.0 0.3 84 3.8 0.4 75 Example 28 7.7 0.4 83 2.6 0.5 69 Example 29 7.8 0.4 83 2.5 0.5 68 Example 30 7.8 0.5 83 2.5 0.5 68 Example 31 11 0.1 85 5.8 0.1 80 Example 32 11 0.1 85 5.9 0.2 80 Example 33 11 0.2 85 6.1 0.3 81 17 201212741 [Table 3] Copper bond adhesion amount (pg/dm2) Thickness (μιη) Type Au Pt Pd Comparative Example 1 12 Calender — — — Comparative Example 2 17 Calendering - - Comparative Example 3 9 Electrolysis - - Comparative Example 4 12 Calendering 1102 - - Comparative Example 5 12 Calendering - 1111 - Comparative Example 6 12 Calendering - 766 [Table 4] 50 μm spacing (L/S = 3 3 μηι /17 μιη) 30μηι spacing (L/S: 25pm/5pm) Etching factor tilt angle (°) Etching factor tilt angle (°) Average standard deviation mean standard deviation Comparison example 1 1.7 0.3 60 1.6 0.0 58 Comparative example 2 1.8 0.2 61 * 氺* Comparative Example 3 1.8 0.2 61 1.6 0.0 58 Comparative Example 4 8.3 2.1 83 Lucky Comparative Example 5 8.0 1.9 83 *氺Comparative Example 6 7.9 2.1 83 *Umbrella ** 氺孝* : The upper part of the circuit does not remain, so Unable to calculate. * * : The initial etchability is poor and cannot be calculated. Further, as shown in Fig. 2(b), the cross-sectional shape of the circuit is precisely a trapezoid in which the oblique side is a straight line. In Tables 2 and 4, the inclination angles of the circuits of the examples and the comparative examples are described, but this is merely a value calculated by the definition shown in Fig. 1. (Evaluation) 18 201212741 (Examples 1 to 3 3) Each of Examples 1 to 3 3 can form a circuit having a large rice cooking factor and no unevenness, and the cross section is approximately rectangular. Fig. 2 is a photograph showing a circuit formed according to Embodiment 27 and a cross-sectional photograph thereof. (Comparative Examples 1 to 6) Comparative Examples 1 to 3 were unprocessed blanks on the surface of the copper foil, respectively, and a circuit in which the scraped surface was rectangular was not formed. In Comparative Examples 4 to 6, the platinum adhesion amount exceeded 105 (^g/dm2, the palladium adhesion amount exceeded 60 (^g/dm2 or the gold adhesion amount exceeded 100 (^g/dm2), and therefore, the cross section was not formed into a rectangular shape. Here, as an example, FIG. 3 is a photograph showing a circuit formed in accordance with Comparative Example 6. [Schematic Description of the Drawing] FIG. 1 is a photograph showing a surface of a partial circuit pattern and a circuit pattern in the portion. A schematic cross-sectional view in the width direction and an outline calculation method using an etching factor (EF) of the schematic diagram. Fig. 2 is a photograph showing a circuit formed according to Embodiment 27 and a cross section thereof. Fig. 3 is a comparison Photograph of the circuit formed in Example 6. Fig. 4' is an enlarged view of a circuit surface which is an example of a copper circuit short-circuited in the vicinity of a resin substrate when a copper circuit is formed. [Main component symbol description] None 19