201212203 六、發明說明: 立體封裝結構及其S作方法，尤 立體封裝結構及其製作方法。 【發明所屬之技術領域】 本發明係有關於一種 指一種可降低封裝厚度的 【先前技術】 /k著半導體製程技術能 功能日益強大，以致丰_曰上&升’ +導體晶片 片的腳數日日汛號的傳輸量逐漸增加，201212203 VI. Invention Description: Three-dimensional package structure and its S method, especially three-dimensional package structure and its manufacturing method. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing the thickness of a package. [Previous technology] / The technology of semiconductor process technology is increasingly powerful, so that the feet of the wafer wafers The number of transmissions of nicknames has gradually increased over the course of several days.
月的腳數亦隨之增加，進而使 二力 技的發展曰漸趨向 需求除了需要二 ==?;度的特性，各模組6The number of feet in the month has also increased, which in turn has led to the development of the second technology. In addition to the need for two ==?
達到輕薄短小的目;;穩"的。°質，更必須節省空W 利用错Γ先的P0P (package 〇n package)結構中，通棠 利用錫球設於下層封裝的上表面，I吊 ，點1而，傳統之錫球的厚度約為；體㈣Achieve light and short eyes;; stable " ° Quality, more must be saved in the use of the wrong P0P (package 〇n package) structure, overnight using the solder ball on the upper surface of the lower package, I hanging, point 1, and the thickness of the traditional solder ball Body
巧致整體封農的厚度無法進一步縮小;再者=、，故 鋅製程時，基板的變、、灰過迴 連接m“ 和其對應的接點相 製卽l 裝結構不論在產品厚度的考量或是 疋性上，均有其不足的地方。 疋 缺失本m人有鑑於上述習㈣技術於實際施用時的 精心研究事相關產業開發實務上多年之經驗， 結構。-、，、於種設計合理且有效改善上述問題之 4/16 201212203 【發明内容】 本發明之主要目的，在於提供一種立體封裝結構及其 製作方法，其係利用雷射直接成型（LDS)的方法將金屬化 圖案鍍層直接成型於封裝膠體上，以取代傳統之錫球等元 件，故可有效降低整體封裝之厚度。 為了達到上述目的，本發明係提供一種立體封裝結構 的製作方法，包含以下步驟： 步驟一：提供一電路基板，其上設有導電線路及接地 點； 步驟二：設置至少一個電子元件於該電路基板上，該 電子元件係連接於該導電線路； 步驟三：進行一雷射直接成型（LDS)方法，包括以下 步驟： 步驟三之一：成型一包覆該電子元件之第一封裝膠 體；以及 步驟三之二：成型一金屬化圖案鍍層於該第一封裝膠 體上；及 步驟四：堆疊至少一個其他電子元件於該第一封裝膠 體的表面。 本發明更提出一種立體封裝結構，包含：一電路基 板，其上設有導電線路及接地點；以及至少一個層疊設置 於該電路基板上之封裝單元，該封裝單元包括：至少一個 設置於該電路基板上之電子元件，該些電子元件係電性連 接於該導電線路；以及一包覆該電子元件之第一封裝膠 體，其中該第一封裝膠體係為一雷射直接成型（LDS)部 5/16 201212203 封▲膠體更形成有—金屬化圖案鍍層，該金屬 Γ層係電性連接於該導電線路及接地點；藉此，該 早元之。亥第—封裝勝體的表面可用以直接堆疊至少 一個其他電子元件或封Μ件/封裝單元。 乂 ^具體實施例中，可利用雷射將含金屬、金屬催化 =::、二機物之塑性材料予以改質，使其具有伽^ ^上。”猎以使導電金屬材料得以直接附著成型於塑性材 及其= :下有益的效果··本發明之立體封裝結構 產' Β八泛應用於無線通訊產品、電腦相關電子 之:小=有效降低封裝的厚度，進以達成電子產品 為使能更進一步瞭解本發明之特徵及技術 ==明之詳細說明與附圖，然而所附圖式僅提 "、兄 並非用來對本發明加以限制者。 【實施方式】 作方提出一種立體封裝結構及其製作方法，上述製 作方法主要係於一封裝單元 4衣 線路於連接端點，使後q 體上直接成型 元件/封# t t 稱上層）的電子元件或封裝 、装早7G可以直接構裝於下層的封 立體封裝結構，而不必利用錫找笪道+早兀上以形成 降低整體封裝後的厚度锡球等導電元件，故可進一步 請參考第-圖與第一 A圖所示 發明之第一具體實施例包括以下步驟·· 口第—圖，本 6/16 201212203 “步驟S101:首先，提供一電路基板丄〇，其上設有導 電線路及接地點（圖未示）；㈣電路基板i Q係為本發 明之立體封裝結構的承載單元。 步驟S1〇3:設置至少一個電子元件i丄A於該電路基 板^ 〇上，而該電子元件11 a係連接於該導電線路（圖 未示）。如第二圖所示’該電路基板上設有四個電子元件 1 1 A於其上表面，但不以此為限，而為了達成電路之目 的’該四個f子元件1 1A係電性連接於電路基板1 0之 導電線路。 步驟S105 :進行一雷射直接成型（LDS)方法，而該方 法具有以下子步驟： 步驟S1051 :成型一包覆該電子元件丄1A 装膠體1 2。 才 步驟S1053 :成型-金屬化圖案鐘層丄2丄於該第一 封裝膠體1 2上以形成一封裝單元2 〇。 一以下將詳細說明雷射直接成型（LDS)*法：上述封裝 早几2 〇的第一封裝膠體i 2係以雷射直接成型 作’其係先以模製（m_ng)方法成型該第—封裝膠體; ^即步驟S1051)，並於該第一封裝膠體丄2上以雷射形 、'舌化區域，再將金屬材料沈積於該活化區域以形成金 ，化圖案鍍層i 2 1 (即步驟S1053)，進而成型上述之雷 t直接成型（LDS)之第一封裝膠體丄2，換言之，該第一 封4膠體12係由-種無法直接將金屬材料沈積於其上 =部件，而本發明使用雷射將該第-封裝膠體12的-預 &區域（例如表面）改質形成—活化區域，再利用一金屬 7/16 201212203 沈積技術，例如化學鍍（亦稱無電鍍）、電鍍，使導電金 屬材料得以直接附著於該第一封裝膠體丄2之活化區域 上，以形成可傳導電路訊號之金屬化圖案鍍層丄2工。 具體而言，該第一封裝膠體i 2的材質係為一種含金 屬、金屬催化物或其有機物之塑性材料，其可被雷射所改 質而形成該活化區域，換言之，可·雷射將上述材料予以 改貝，使该活化區域具有金屬化的活化核心，因此，該活化 區域的活化核心會催化物理或化學反應；而在本具體實施例 中，該第一封裝膠體1 2的材質係為一種含銅之有機複合隹 材料（CU-0rganic_complex )，並利用該複合材料包覆電子 元件1 1 A。 而在步驟S1053中，較佳地將電路基板i 〇上的導電 線路及接地點向上位移’以形成立體的封裝態樣。具體而 言，該第-封«體1 2中可形成穿孔^ 2 2，而穿孔1 2 2的位置係對應電路基板丄〇上之導電線路及接地 點；再利用雷射將該第一封裝膠體工2之表面及該第一封 裝膠體1 2之該穿孔1 2 2改質形成活化區域，故可利用鲁 化學鑛、電鑛等金屬沈積方法’使導電金屬材料可直接沈 積附著於該第-封裝膠體！2之表面及該第—封裝膠體 1 2之該穿孔1 2 2，亦即’利用鑽孔方法形成對應導電 線路及接地點之穿孔i 2 2後，利用雷射活化改質，即可 利用鏟孔或填孔等製程，使金屬化圖案鑛層丄2丄電連接 於導電線路、接地點或EMI薄膜（)。 再者’上述之無電鐘步驟可包括依序將銅材料、鎳材 料及金材料成型於該活化區域而形成該金屬化圖案鑛層 8/16 201212203 1 2 1之步驟，其中所沈積的銅層約為5um，鎳層約為 3um ’金層約為〇. 1 uni ’但不以上述為限。 、藉此，在上述步驟之後，封裝單元2 〇已被製作完 成。而其表面之部分金屬化圖案鍍層丄2丄可具有導電線 路之電路功能；而其他與接地點或相連接之金屬 化圖案鍍層1 2 1則具有抑制EMI的效果，換言之，第二 圖中之電子元件1 1A可藉由金屬化圖案鍍層i 2丄而 達到電磁遮蔽的效果。The thickness of the whole package can not be further reduced; in addition, the zinc substrate, the change of the substrate, the gray back connection m" and its corresponding contact phase structure, regardless of the thickness of the product Or defamatory, there are some shortcomings. 疋 Missing this m people in view of the above (4) technology in the actual application of the careful study of the relevant industry development practice years of experience, structure. -,,, Reasonable and effective improvement of the above problems 4/16 201212203 [Invention] The main object of the present invention is to provide a three-dimensional package structure and a manufacturing method thereof, which utilizes a direct laser direct laser (LDS) method to directly plate a metallized pattern. Formed on the encapsulant to replace the traditional solder ball and other components, the thickness of the overall package can be effectively reduced. To achieve the above object, the present invention provides a method for fabricating a three-dimensional package structure, comprising the following steps: Step 1: provide a a circuit substrate on which a conductive line and a grounding point are disposed; Step 2: providing at least one electronic component on the circuit substrate, the electron The component is connected to the conductive line; Step 3: performing a laser direct structuring (LDS) method, including the following steps: Step one: forming a first encapsulant covering the electronic component; and step three of two: Forming a metallization pattern on the first encapsulant; and step 4: stacking at least one other electronic component on the surface of the first encapsulant. The invention further provides a three-dimensional package structure comprising: a circuit substrate on which And a conductive unit and a grounding point; and at least one package unit disposed on the circuit substrate, the package unit includes: at least one electronic component disposed on the circuit substrate, the electronic components are electrically connected to the conductive a circuit; and a first encapsulant covering the electronic component, wherein the first encapsulant system is a laser direct molding (LDS) portion 5/16 201212203 sealing ▲ colloid is further formed with a metallized pattern coating, the metal The Γ layer is electrically connected to the conductive line and the grounding point; thereby, the surface of the 元 第 封装 封装 封装 封装 封装 封装 封装 封装Stacking at least one other electronic component or package/package unit. In a specific embodiment, the metal-containing, metal-catalyzed =::, two-material plastic material may be modified by laser to have a gamma ^上." Hunting so that the conductive metal material can be directly attached to the plastic material and its = beneficial effect. · The three-dimensional package structure of the present invention. Β 泛 ubi are used in wireless communication products, computer-related electronics: small = Effectively reducing the thickness of the package, and further understanding of the features and techniques of the present invention to achieve the electronic product as a function of the detailed description and drawings of the present invention, however, the drawing only mentions ", the brother is not used to the present invention Limiter. [Embodiment] A three-dimensional package structure and a manufacturing method thereof are proposed, and the above-mentioned manufacturing method is mainly applied to an electronic component of a package unit 4 at a connection end point, so that a component directly on the rear q body is formed/closed. The component or package and the 7G package can be directly mounted on the lower-layer sealed three-dimensional package structure, without having to use the tin to find the ridge + early 以 to form a conductive element such as a tin ball which reduces the thickness of the whole package, so please refer to the - Figure 1 and the first embodiment of the invention shown in Fig. A include the following steps: · Port diagram - Figure 6/16 201212203 "Step S101: First, a circuit substrate is provided, on which a conductive line is provided And a grounding point (not shown); (4) the circuit substrate i Q is a carrying unit of the three-dimensional packaging structure of the present invention. Step S1〇3: providing at least one electronic component i丄A on the circuit substrate, and the electronic The component 11a is connected to the conductive line (not shown). As shown in the second figure, the circuit board is provided with four electronic components 1 1 A on the upper surface thereof, but not limited thereto, and Circuit The four f sub-elements 1 1A are electrically connected to the conductive lines of the circuit substrate 10. Step S105: performing a laser direct structuring (LDS) method, and the method has the following sub-steps: Step S1051: Forming one The electronic component 丄1A is coated with the colloid 1 2. Step S1053: a molding-metallization pattern layer 2 is formed on the first encapsulant 1 2 to form a package unit 2 〇. Direct Forming (LDS)* method: The first encapsulating colloid i 2 of the above package is laser-formed directly as 'the first molding encapsulation colloid by the method of molding (m_ng); ^ ie step S1051 And forming a gold-like material on the first encapsulant colloid 2 in a laser-shaped, 'tongued region, and then depositing a metal material on the active region to form a gold plating pattern i 2 1 (ie, step S1053), thereby forming the above The first encapsulant colloid 丄 2 of the direct molding (LDS), in other words, the first encapsulation 12 colloid 12 can not directly deposit the metal material thereon, and the present invention uses the laser to - the pre- & area (eg surface) modification of the encapsulant 12 Forming the active region, using a metal 7/16 201212203 deposition technique, such as electroless plating (also known as electroless plating), electroplating, so that the conductive metal material is directly attached to the active region of the first encapsulant 丄2 to form Specifically, the material of the first encapsulant i 2 is a plastic material containing a metal, a metal catalyst or an organic substance thereof, which can be modified by a laser. Forming the activation region, in other words, the laser can modify the material to have a metallized activation core, and thus the activation core of the activation region catalyzes a physical or chemical reaction; For example, the material of the first encapsulant 1 2 is a copper-containing organic composite tantalum material (CU-0rganic_complex), and the electronic component 1 1 A is coated with the composite material. In step S1053, the conductive lines and ground points on the circuit substrate i are preferably displaced upwards to form a three-dimensional package. Specifically, the first sealing member 22 can form a through hole ^ 2 2 , and the position of the through hole 12 2 corresponds to the conductive line and the grounding point on the circuit board, and the first package is further processed by using a laser. The surface of the colloid 2 and the perforation of the first encapsulant 12 are modified to form an activation region, so that a metal deposition method such as a chemical mine or an electric ore can be used to directly deposit a conductive metal material on the first - Encapsulation gel! The surface of the second surface and the perforation 1 2 2 of the first encapsulating colloid 1 2, that is, after the perforation i 2 2 corresponding to the conductive line and the grounding point is formed by the drilling method, the laser is used to modify the mass, and the shovel can be utilized. The process of holes or holes is such that the metallized pattern ore layer is electrically connected to the conductive line, the grounding point or the EMI film (). Furthermore, the step of the above-mentioned electric clockless step may include the steps of sequentially forming a copper material, a nickel material and a gold material in the active region to form the metallized patterned ore layer 8/16 201212203 1 2 1 , wherein the deposited copper layer About 5um, the nickel layer is about 3um 'the gold layer is about 〇. 1 uni ' but not limited to the above. Thereby, after the above steps, the package unit 2 has been fabricated. The metallized pattern plating layer 其2丄 on the surface may have the circuit function of the conductive line; and other metallized pattern plating layer 1 1 connected to the grounding point or the like has an effect of suppressing EMI, in other words, in the second figure The electronic component 1 1A can achieve the effect of electromagnetic shielding by metallizing the pattern i 2 丄.
更重要的是，由於封裝單元2 〇表面之金屬化圖案鍍 層1 2 1已具備電路基板工〇之導電線路的訊號功能，因 此其他電子元件1 1 B、1 1 C等可直接堆4於封農單元 2 〇之表面，其中電子元件1 1 B係同於電子元件工丄 a ’而電子7C件1 1 C可為-種晶圓級尺度封裝（Wafer Level Chip Scale Package，WLCSp)，但不以此為限。因此， 步驟S107則係堆疊至少一個其他電子元件丄丄b、工1 C於該第-封裝㈣丨2的表面，以達❹體構裝/封裝 的目的，且由於金屬化圖案鍍層丄2丄僅為—金屬薄層 (如金屬化圖案鍍層！ 2工之整體厚度約為81_，而； ，，體1 2之厚度約為8〇〇 _)，相較於傳統錫球的 h (約為0.4至G_5nm〇,本發明之立體_結構 縮小其厚度之功效。 一 向在步驟S107之後，更包括成型一第-包覆於該至少-個堆疊於該 面的其他電子元件11B、11C之步驟。換乂= 用拉製（molding)方法將第二封裝雜i 3包覆於電子元 9/16 201212203 件1 1 B、1 1 c，而在本具體實施 1 3係不同於第-封裝膠體1 2，第^二封裝膠體 一種非藤俨之朔讨，B甘士 弟一封裝膠體13係為 種非導體之塑材’且其中不需含有金 -般常見的x#_均可應用於本步料。战換5之 综上所述，如第二圖所示之本發 — 體封裝結構包括電路基板i Q及至少^7，例’立 電路基板1 0上之封裴單元2 〇，1 9 &又置於该 括:至少-個設置於該電路基板More importantly, since the metallization pattern plating layer 1 1 of the surface of the package unit 2 already has the signal function of the conductive circuit of the circuit substrate process, other electronic components 1 1 B, 1 1 C, etc. can be directly stacked. The surface of the agricultural unit 2, wherein the electronic component 1 1 B is the same as the electronic component process a ' and the electronic 7C component 1 1 C can be a Wafer Level Chip Scale Package (WLCSp), but not This is limited to this. Therefore, in step S107, at least one other electronic component 丄丄b, the work 1 C is stacked on the surface of the first package (four) 丨 2 for the purpose of the body assembly/package, and the metallization pattern is 丄 2 丄Only a thin layer of metal (such as metallized pattern plating! The overall thickness of the 2 work is about 81_, and;, the thickness of the body 12 is about 8〇〇_), compared to the h of the traditional solder ball (about 0.4 to G_5 nm, the effect of the stereoscopic structure of the present invention to reduce its thickness. After the step S107, it is further included to form a step of coating a plurality of other electronic components 11B, 11C stacked on the face.乂 用 = The second package impurity i 3 is coated on the electron element 9/16 201212203 pieces 1 1 B, 1 1 c by a molding method, and in the present embodiment, the 1 3 series is different from the first package body 1 2, the second ^ encapsulation colloid is a non-tank begging, B Gan Shidi a package of colloid 13 is a kind of non-conductor plastic material 'and which does not need to contain gold - common x#_ can be applied to this step As described in the above, the present invention has a circuit board i Q and at least ^7, as shown in the second figure. The sealing unit 2 〇, 1 9 & on the circuit substrate 10 is further disposed: at least one is disposed on the circuit substrate
Aj些電子兀件i1Α係電性連接於該導電線路； 一包覆該電子元件1 1Α之第-封裝膠IU 2，其中該第 -封裝膠體1 2係為-雷射直接成型(LDs)部件，該第一 封裝膠體1 2更形成有-金屬化圖⑽層工2工1 :匕：：:』1 2 1係電性連接於該導電線路及接地點。而 在本具體貫施例中，該第一封裝勝體1 2成型有至少-個 穿孔1 22 ’金屬化圖案錢層1 2 1則設置於該第一封裝 膠體1 2之表面及該第-封装膠體1 2之該穿?L1 2 f。再者’第二封裝膠體1 3係包覆於該至少一個堆疊於 違第-封裝勝體1 2之表面的其他電子树丄i B、丄丄 C二以形成層叠於封農單元2 ◦上之另—封裝單元2 0 /進而建構成本發明之立體封裝結構。 第三圖則顯示本發明之第二實施例，其中，與第 施例之差異在於··電子元件1 1A、i 1B、1 1 C的位 置不同’換言之’在本具體實施例t，電子元件11c之 晶圓級尺度封裝係設於封裝單元2 0，而金屬化圖案鑛層 1 21則同樣可達成電磁遮蔽的效果，且亦可達成縮減整 10/16 201212203 體厚度的功效。 第四圖則顯示本發明之第三實施例，其中， 施例之差異在於··本實施例係為一種 的：： 裝態樣，封裝單係成型於電路基板構 金ί化圖案鑛層121同樣成型於該第-封裝膠 之表面及該穿孔丄2 2 ;而 /體1 2 電路基板1〇之上表面。料早几20則成型於 第五圖則顯示本發明之第四實施例，其中，Aj electronic components i1Α are electrically connected to the conductive circuit; a first package encapsulant IU 2 covering the electronic component 1 1 , wherein the first encapsulation colloid 12 is a laser direct molding (LDs) component The first encapsulant 1 2 is further formed with a metallization pattern (10). The layer 1 is electrically connected to the conductive line and the ground point. In this embodiment, the first package body 1 2 is formed with at least one perforation 1 22 'metallization pattern, the money layer 1 2 1 is disposed on the surface of the first encapsulant 12 and the first The encapsulant colloid 1 2 should be worn by L1 2 f. Further, the second encapsulant 13 is coated on the at least one other electronic tree 丄i B, 丄丄C2 stacked on the surface of the singular-packaged body 1 2 to form a layer on the sealing unit 2 The other package unit 20 is further constructed to constitute the three-dimensional package structure of the present invention. The third embodiment shows a second embodiment of the present invention, wherein the difference from the first embodiment is that the positions of the electronic components 1 1A, i 1B, and 1 1 C are different 'in other words' in the present embodiment t, the electronic components The wafer level package of 11c is provided in the package unit 20, and the metallized pattern ore layer 21 can also achieve the effect of electromagnetic shielding, and can also achieve the effect of reducing the thickness of the whole 10/16 201212203. The fourth embodiment shows a third embodiment of the present invention, wherein the difference in the embodiment is that the present embodiment is one of the following:: the mounting state, the package is formed in a circuit substrate, and the gold patterned layer is 121. Also formed on the surface of the first encapsulant and the perforated crucible 2 2; and the upper surface of the body 1 2 circuit substrate 1 . The second embodiment is formed in the fifth figure to show the fourth embodiment of the present invention, wherein
把例之差異在於：本實施例係將較厚之電子元件夕 晶圓級尺度封裝與兩層較薄之電子元件丨丨A 件於同-結構面，齡之，f子元件11A 2 型於電路基板“之左半部，且湘[封裝膠體l2t 特性將兩者進行層疊；而電子元件11c之晶圓級尺度 裝則設於電路基板i 〇之右半部，再_第 / 3將整體結構包覆封裝。 玎⑽版1 第六圖則顯示本發明之第五實施例，其中，與第一實 施例之差異在於：本實施例係將多個單—封裝元件11〇 =行立體化的構裝形態，例如先將—封裝元件丄丄d設於 電路基板1 ◦，並利用上述之第—封裝膠體12、金屬化 圖案鍍層1 2 1形成最下層之封裝單元2 〇 ;再將另一封 裝元件1 1D設於第-封裝勝體丄2上，同樣利用第一封 裝膠體1 2、金屬化圖案鑛層丄2 i形成次層之封裝單元 20 ，再一步將另一封裝元件11D設於次層之第一封 4膠體1 2上，以形成最上層之封裝單元2 〇//。 綜上所述，本發明具有下列諸項優點： 11/16 201212203 、本發明之立體封裝处 日月係μ枇μ 有缚型化的結構。由於本發 月係&供-種以雷射直接成型: 金屬化圖⑽層僅是成型於模製成型二體； 膠體上的金屬線路，相較 =苐一封裝 ::本發明之立體封裝結構可大幅各:封== 2、本發明之第—縣膠體上的金屬化圖案錢層可利用鑽 孔、錢孔或填孔等製程連接於接地或咖薄膜，故 可達成電磁遮蔽的效果。 、 太二上：述僅為本發明之較佳可行實施例，非因此侷限 本發明之翻_，故舉凡制本發明朗書及圖示内容 所為之等效技術變化,均包含於本發明之範圍内。 【圖式簡單說明】 第圖至第一 A圖係為本發明立體封裝結構的製作方法 的流程步驟圖。 第二圖係為本發明第一實施例的示意圖。 第三圖係為本發明第二實施例的示意圖。 第四圖係為本發明第三實施例的示意圖。 第五圖係為本發明第四實施例的示意圖。 第六圖係為本發明第五實施例的示意圖。 【主要元件符號說明】 1 0 電路基板 電子元件 12/16 201212203 11D 單一封裝元件 12 第一封裝膠體 12 1 金屬化圖案鍍層 12 2 穿孔 封裝單元 13 第二封裝膠體 2 0、2 0 /、2 0 〃 S101〜S107 流程步驟The difference between the examples is that in this embodiment, the thicker electronic component wafer-level package and the two thinner electronic components are in the same-structured surface, and the f-component 11A 2 is The left half of the circuit board, and the [package colloid l2t characteristics are stacked; and the wafer level package of the electronic component 11c is placed on the right half of the circuit board i ,, then _ 3 / 3 will be the whole The structure is encapsulated and packaged. 玎(10)版 1 The sixth embodiment shows a fifth embodiment of the present invention, wherein the difference from the first embodiment is that the present embodiment is a plurality of single-package components 11 〇 = row stereoscopic The mounting form is, for example, first, the package component 丄丄d is disposed on the circuit substrate 1 ◦, and the package element 2 〇 is formed by using the first package encapsulant 12 and the metallization pattern plating layer 1 1 1; A package component 1 1D is disposed on the first package 丄 2, and the package element 20 of the sub-layer is formed by using the first encapsulant 2 2 , the metallization pattern layer 丄 2 i , and the other package component 11D is further set On the first 4 colloid 1 2 of the sub-layer to form the uppermost package list 2 〇 / /. In summary, the present invention has the following advantages: 11/16 201212203, the three-dimensional package of the present invention, the Japanese-Japanese system μ枇μ binding structure. Because the present system & - Direct laser molding: Metallization (10) layer is only molded into the molded two body; metal line on the gel, compared to = one package:: The three-dimensional package structure of the present invention can be substantially different: seal = 2. The metallization pattern on the first-county colloid of the present invention can be connected to the grounding or coffee film by a process such as drilling, money hole or hole filling, so that the electromagnetic shielding effect can be achieved. The invention is not limited to the preferred embodiments of the present invention, and the equivalents of the present invention are included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a flow chart of a method for fabricating a three-dimensional package structure of the present invention. The second figure is a schematic view of a first embodiment of the present invention. The third figure is a second embodiment of the present invention. The fourth figure is the third embodiment of the present invention. Fig. 5 is a schematic view showing a fourth embodiment of the present invention. Fig. 6 is a schematic view showing a fifth embodiment of the present invention. [Description of main components] 1 0 circuit board electronic component 12/16 201212203 11D single package component 12 First encapsulant 12 1 Metallization pattern plating 12 2 Perforated packaging unit 13 Second encapsulation 2 0, 2 0 /, 2 0 〃 S101~S107 Process steps
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