TW201017865A - Stacked package and method for forming conductor solder pillars therein - Google Patents

Abstract

Disclosed are a stacked package and a method for forming conductive solder pillars therein. The stacked package comprises a plurality of chip packages and a plurality of conductive solder pillars. Each chip package includes a substrate and a chip disposed on the substrate. The substrate has a plurality of through holes and a circuit layer electrically connecting to the through holes. The chip package are tightly stacked together so that the through holes between different chip packages are vertically aligned. The conductive solder pillars are formed by reflowing a plurality of solder balls jammed between the chip packages and aligned in the through holes. The conductive solder pillars are filled in the through holes to electrically connecting the circuit layers. Accordingly, this enables to rapidly achieve electrical transmissions between the chip packages vertically stacked. Manufacturing processes are simple and convenient and manufacturing cost is reduced.

Description

201017865 IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a stacked package structure and a method of forming a conductor pillar therein. [Prior Art] Trends in the current electronics market 'Most of the electronic products are required for versatility or high capacity' to meet market demand, so multiple Φ chip package structures can be stacked to form a stacked package structure. It can also be called a POP (Package Package) or a three-dimensional stacked semi-element package (3D package), that is, an integrated circuit forms a plurality of wafers after a semiconductor wafer process and a package process. The package structure, and then stacking the plurality of chip package structures on each other, and combining them into a south density integration device that does not occupy the surface joint area. Compared to the wafer stack (DOD, Die on Die), in a chip package structure, although the size of the stacked package structure will be slightly larger, it is more suitable for high yield and easy assembly and better protection for the wafer. . In addition, the side-by-side bonding method of the conventional chip package structure is more space-saving, meeting the requirements of miniaturization and high density. U.S. Patent Application No. 2,100, 047, 464, entitled "Semic 〇nduct 〇r device and method of fabricating the same" discloses a stacked package construction. As shown in FIG. 1, the stacked package structure 100 is composed of a plurality of chip package structures 110 and a plurality of solder balls 120. Each of the chip package structures 110 mainly includes a substrate ηι and a 201017865 wafer 112. The substrate 111 is formed by the leads of the lead frame. The sheet 112 is disposed under the base phase by adhesion of a die layer 113. The active surface of the wafer u2 has a plurality of pads and is flip-chip bonded to the substrate by a plurality of conductive bumps 115. Inner pad 116. The encapsulant portion of the resin 117 is as follows: the substrate ill fills the active gap of the substrate U1 to the wafer 112. The substrate 111 has a plurality of external pads U8 and a plurality of second external pads 119 on the periphery of the upper and lower surfaces for soldering of the electrodes 120. As shown in FIG. 1, the chip package structures 110 are mutually in contact with each other, but the substrates 111 are not in contact with each other to provide a gap between the solder balls 12 and the pads. The chip package structures 110 are formed by solder balls 120, and are connected by soldering. The solder balls 12 are exposed to the periphery of the substrates 111, and are easily broken or shattered. In the process of the external process, each time the stack of the chip package structure is overlapped, the back-up operation needs to be performed once, so that the solder-balls 120 can meet the first-outer pads 118 and the second external connections. Pad 119, stacking four wafer package structures 11 will require three trips. When the number of reflows of the solder balls 12〇 is increased, the product becomes worse, and it is easy to produce a soldering interface between the solder balls and the external pads. [Invention] The main purpose of the present invention is to understand the above problems. In a stacked package structure and a conductor post formed therein, the circuit is electrically connected to the upper and lower stacked chip package structures, and the first 111 balls of the die are stacked on the base. In the case of these shapes, for example, the welding quality is cracked. For the $, can process 6 201017865 simple and convenient and low production costs.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. SUMMARY OF THE INVENTION A stacked hermetic structure primarily comprises a plurality of wafer package structures and a plurality of conductor pads. Each of the wafers includes a substrate and a wafer disposed on the substrate. The substrate has a plurality of via holes and a circuit layer electrically connected to the via holes, wherein the chip package structures are They are stacked on each other such that the through holes correspond to each other in the longitudinal direction. Each of the conductor pillars is formed by a plurality of solder balls that are engaged between the chip package structures and aligned with the through holes. The guide pillars are formed according to the shape of the through holes. The substrates are brought into contact to electrically connect the circuit layers. The purpose of this month and the resolution of its technical problems can be further realized by the following technical measures. In the stacked package structure, the solder balls may have a size x such that the glow balls are not completely trapped in the through holes and the adjacent solder balls are in contact with each other before reflow. In the above-described stacked package structure, the wafers may be disposed on a plurality of upper surfaces of the corresponding substrate, and a lower surface of each of the substrates is formed with a plurality of recesses 8 aligned with the wafers. In the foregoing stacked package construction, the circuit layers may include a plurality of annular pads surrounding the through holes. In the stacked pack structure, the through holes may be located at the periphery of the corresponding substrates. In the foregoing stacked package structure, the wafers can be overlaid on the corresponding substrates. This is the case in the aforementioned stacked package configuration. The day-to-day film can be a bare die. In the foregoing stacked package construction, the conductors can be substantially the stack thickness of the chip package structures. The height is in the front material# type package material H (four) body welding _ a plurality of feed balls, which are placed on the wafer, the ^ ^ _ _ assembly, the structure of the stack and aligned to the through holes, the The feeding balls are welded and crushed, and the solder balls corresponding to the l-, Θ are reflowed to form the (four) body welding columns. The present invention - a method of forming a conductor post in a stacked package structure. As can be seen from the technical solution, the method of the stacked package of the present invention constitutes a square solder column, which has the following advantages and effects: ball " welding between a plurality of bonded chip package structures: to form a substrate The through-hole defines the shape of the conductor pillar. If it is not stacked, the wafer package structure performs a reflow operation once: the efficiency achieves the circuit assembly structure of the upper and lower stacked chip package structure: the process is simple and convenient, and the manufacturing cost is low. In addition, the guide column can make the substrate touch, and the conductor pillar and the wafer are well protected without the sealant or only a small amount of the sealant. The stacked package structure is more compact and resistant to falling. Earthquake resistance. Second, the electrical connection strength can be not damaged by the conductor fresh column, and can be increased: the electrical connection and the service life of the electrical connection of the stacked package structure. - The use of the cavity can accommodate the thickness of the wafer protruding from the substrate to ensure 201017865 without the need for reserve soldering. In addition, the wafer can save the substrate contact gap of the plurality of chip package structures, thereby reducing the package height. Remove the protection of the sealant. [Embodiment] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, and it should be noted that these drawings are simplified schematic diagrams, and only the dry heat method is used to explain the basic structure or implementation of the present invention. Method, so s *, square

The components and combinations related to the case, the components shown in the figure are not drawn in proportion to the number, shape and size of the implementation, and the ratio of a certain scale to the other related dimensions is exaggerated or simplified. \,War, U provides a clearer description. The actual number, shape and size ratio of the actual implementation is a choice of options, the detailed component layout may be more complicated. According to one embodiment of the present invention, a stacked package structure For example, a schematic cross-sectional view of the second package is shown in Fig. 2. The stacked package structure 200 mainly includes a plurality of chip package structures 21 and a plurality of guide pillars 220. Each of the chip package structures 210 mainly includes a substrate 211 and a set. The substrate 211 of the substrate 211 has a plurality of through holes 213 and a circuit layer 2 1 4 ' electrically connected to the through holes 213, wherein the chip package structures 2 are stacked on each other. In order to make the through holes 213 correspond to the longitudinal direction, the substrate 211 has a signal transmission function such as a printed circuit board, a lead frame, a circuit film or various wafer carriers, and the like. Conducting the wafer 212 electrically. The through holes 213 may be located at the periphery of the corresponding substrate 211 to be away from the wafer setting area '201017865. Laser, mechanical drilling or reactive ion etching may be used. The circuit layer 214 can include a plurality of annular pads 218 surrounding the through holes 213. The annular pads 218 are electrically connected to the conductive posts 22, and the upper and lower chip package structures are formed. 2 1 0 achieves an electrical connection relationship. In this embodiment, the opening of the annular pad 2 18 is the same as the aperture of the through holes 2 1 'except for manufacturing convenience, and does not affect The shape of the conductor posts 220 ^

In detail, as shown in Fig. 2, the wafers 212 are provided with V on a plurality of upper surfaces 215 of the corresponding substrate 211. In this embodiment, the plurality of pads 219 of the plurality of pads 212 are electrically connected to the plurality of pads 219 of the plurality of pads 219. The circuit layers 214 of the substrate 211, the solder pads 219 may be provided with bumps, but there is no arcing height ', and the conventional sealing body having a thickness exceeding the arcing height to seal the bonding wires is not required. The flip chip bonding method means that the wafers 212 are disposed on the corresponding substrate 211 with their active faces facing downward. In other embodiments, the wafers 212 may be disposed by means of an inner lead bonding (ILB), that is, the pins of the substrates 211 are pressed onto the pads 219 or pads 219 of the wafers 212. Bump (not shown). Preferably, the wafers 212 may be in a bare crystalline form in the present invention. In the present embodiment, the wafers 212 have a thickness that protrudes from one of the upper surfaces 215 of the corresponding substrate 211. In various embodiments, the wafers 2 1 2 may be partially or completely embedded in the corresponding substrate 211. Preferably, the lower surface 216 of each substrate 211 is formed with a cavity 10 217, 865, which is aligned with the wafers 212. Therefore, after the chip package structures 21 are stacked, the thickness of the wafers 212 protruding from the corresponding substrate 21 is accommodated in the adjacent chip package structure 217 to reduce the stack. The height of the package structure 200 as a whole. As shown in FIGS. 2 and 3F, each of the conductor posts 22 is formed by re-welding a plurality of solder balls 221 that are engaged between the chip package structures 210 and aligned with the through holes. The fresh column 2 is formed according to the shape of the through hole 213, and the substrates 2" are in contact with each other to electrically connect the circuit layers 214, and the infamiliar & m is compared with the 3F to 2nd drawings.

The change. Therefore, the abundance, L-two-slice package structure 210 is electrically interconnected by the conductor posts 220. This 邋 reverses the height of the second-order solder column 220

For these chip package structures 21, the thickness of the stack is hidden. One of the conductor posts 220 can be hooked to the outer surface of the hail and joined to an external printed circuit board (not shown). In the present embodiment, the stacked package structure 200 is formed by stacking two wafer package-selected 9 1 kn kn fabric structures 210, but without limitation, can be stacked upward More B-package structure 210. The number of stacks of the chip package structures 210 is limited, but only one reflow operation is required to form the conductor pads. Compared with the conventional method of stacking a chip package structure, a gentleman's 'f·卞1 is known, and the invention can effectively offend the wafers of the upper and lower stacks, and ^ ^ , the circuit of the structure Turn-on, the process is simple and convenient, and the production cost is low. In addition, the formation of the ^ ^ ^ ^ 01 , L two-conductor solder column 220 enables the substrates 211 to be in contact with each other, in the absence of # # -P ^ ^ with a sealant or only a small amount of sealant, These conductors 220 and the protection of the wafers 21217865 «Good I-body stacked package structure is more compact and resistant to shock and shock. Referring to the cross-sectional views of Figures 3A through 3F, the present invention further describes the method of forming the conductor posts 22 in the stacked package structure to demonstrate the efficacy of the present invention. First, as shown in FIG. 3A, a first layer of the chip package structure 2 is provided. The chip package structure 21 includes a substrate 2 ι and a wafer 212 disposed on the substrate 211. The substrate 211 is provided. The system has a plurality of through holes 213 and a circuit layer 214 electrically connected to the through holes 213. In this embodiment, the wafer 212 can be disposed on the upper surface 215 of the substrate 211. The lower surface 216 of the substrate 211 is formed with a cavity recess 217 that is aligned with the wafers 212. Next, as shown in Fig. 3B, a plurality of solder balls 221 are placed on the through holes 213. The solder balls 221 are made of one of tin-lead solder and lead-free solder. As shown in Fig. 3C, the solder balls are of a size such that the solder balls 221 are not completely trapped in the through holes 213 and can be engaged with the through holes 213. More specifically, the ball diameters of the balls 221 are slightly larger than the apertures of the through holes 213, so that the fresh balls 221 are engaged without falling into the through holes 213 completely. A portion of the solder balls 221 slightly more than one-half is protruding from the substrate. Then, as shown in FIG. 3C, another second layer of the chip package structure 210 is stacked over the solder balls 221, and the through holes 213 of the chip package structure 210 to be stacked are aligned with the solder balls 221 and below. The through holes 2 1 3 ' of the chip package structure 210 are aligned with 12 201017865. Then, as shown in the 3D circle, the solder balls 221 are placed on the through holes 213 of the second layer package structure 21. The first layer and the second layer of the chip package structure 21 〇 a after the stack, because the size of the balls 221 is slightly larger than the above: f丨. The aperture 213, the solder balls 221 are not completely scattered in the through holes 213 to the XL Λ ' ' 故 故 故 故 故 故 第一 第一 第一 第一 第一 第一 第一 第一 第一 基板 216 216 216 216 216 216 216 216 216 216 216 216 216 216 The substrate 211 of the package structure 210 is (four). The upper surface m, the upper and lower substrates 211 are followed by 'as shown in the third drawing, the mask is also, 1 Λ ^, 圃 not stacked a third layer of chip package structure = placing a plurality of fresh balls 221 in the third layer of chip packaging Structure 21. : the through holes 213, so that the chip package structures 21 are stacked on each other and the same?丨, ^ u Μ ^ ^ ^ 〇 is the vertical correspondence. The wafer package can be stacked up and down. ~ The package 1 ' is expected to be the number of stacks of the required package structure 21〇. The solder balls 221 placed between the wafer packages at 210° are engaged in the chip package structures 221 and aligned with the through holes 213 ′ and The adjacent fresh balls are in contact with each other before reflowing. For example, the thickness of the substrate 211 is 213 ^ such that the solder balls 221 stacked one above another in the same through hole are in contact with each other. The plurality of feed solder balls 22 are shown as a plurality of feed balls ^ 222, and the feed solder balls 222 are placed in the chip package structures 2 and after the kneading/cursor 221 The enamel body of the crystal sealing structure 210 is aligned with the through holes 13 201017865 3 during the reflow process, the feeding balls 222 are longitudinally corresponding to the welding balls 221 to form the conductors. The number of the feeds β and the total number of the solder balls 221 are equal to the number of the through holes 2 1 3 · § ·, you can make a solder ball 221 or a feed solder ball 222 fill Full of a through hole 213. Finally, as shown in Figures 2 and 3F, reflowing the solder balls 2 2 1 and the same ^

Two solder balls 22 2 are formed to form the conductor posts 220. For example, the stacked package structure 352 is placed in a multi-stage high temperature tunnel reflow furnace and the entire stack is heated to above the melting point of the solder balls, so that the solder balls 221 and the feed balls 222 corresponding to the longitudinal direction are matched. The conductive pillars 220 are formed by melting to form the conductive pillars 22 ( ) according to the shape of the through holes ( 1 ) and the substrates 211 are in contact with each other to electrically connect the circuit layers 214 . In particular, the soldering balls 221 are used to reflow the melt cohesive force 'the chip package structures 210' that are not in contact with each other when the reflow soldering forms the conductor fresh columns 220, and the chip packages are π-structured. The gap will disappear and the substrates 2 η will be in contact with each other to reduce the original package height. Therefore, the stacked package structure 200 of the present invention reflows the solder balls 221 and the feed solder balls 222 to form the conductive pillars 22 〇 in a reflow manner, and efficiently achieves the upper and lower stacks of the solar package structure 2丨〇The circuit is turned on' simple and convenient process and low production cost. At the same time, since the solder balls of the present invention are bare, and the solder balls 221 of the present invention become the conductive pillars 22, the strength of the solder balls 221 can be prevented from being damaged and protected in the through holes 213 of the substrates 211. In this case, the reliability of the electrical connection of the stacked package structure can be improved and the service life of 14 201017865 can be improved. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention in any way, although the present invention has been disclosed in the above preferred embodiments, however, it is not intended to limit the invention, Any simple change and modification made by the skilled person within the technical scope of the present invention still belong to the technical scope of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 Fig. 2 is a schematic cross-sectional view of a conventional stacked package structure. A schematic cross-sectional view of a stacked closure construction in accordance with an embodiment of the present invention. Sealed 馘 3rd to 3F®: a stack in accordance with an embodiment of the present invention! A method for constructing a conductor pillar in which a conductor pillar is formed is constructed. [Main component symbol description] 100 stacked package structure 11 〇 chip package structure 111 substrate 113 adhesive layer 114 solder pad 116 internal 塾 119 second external 塾 120 solder ball 117 sealant 112 wafer 115 conductive bump 11 8 An external meal 200 stacked package structure 212 wafer 215 upper surface 210 chip package structure 211 substrate 214 circuit layer 213 through hole 15 201017865 216 lower surface 217 cavity 219 solder pad 220 conductor 221 solder ball 218 ring pad 222 Solder ball

16

Claims (1)

201017865, patent application format, a stacked package structure comprises a plurality of chip package structures, and a chip package structure mainly comprises a wafer disposed on the substrate, the base (4) having a plurality of y «sexual connections to the a circuit layer of the via holes, wherein the chip package structures are stacked on each other, and the through holes are longitudinally corresponding; a plurality of conductor fresh columns, each of which is pinched and added... The mother conductor zinc column is formed by a plurality of solder balls re-welding between the chip package structures and aligned with the through holes The conductive welding (4) (4) the through holes (four) shape (four) ^ make the substrates contact, to electrically connect the circuit layers. 2. The stacked package structure of claim 2, wherein the solder balls have a size such that the solder balls are not completely trapped in the through holes and adjacent to the solder balls They are in contact with each other before reflow. 3. The stacked package structure of claim 1, wherein the wafers are disposed on a plurality of upper surfaces of the corresponding substrate, and a bottom surface of each of the substrates is formed with a cavity recess For these wafers. 4. The stacked package structure of claim 1, wherein the circuit layers comprise a plurality of annular turns surrounding the through holes. 5. The stacked package structure of claim 1, wherein the through holes are located at a periphery of the corresponding substrates. 6. The stacked package structure of claim 1, wherein the wafers are disposed on the corresponding substrates in a flip chip bonding manner. 7. The stacked package structure of claim 1 or 6, wherein the wafers are in a bare crystalline form in 17 201017865. The stacked package structure of claim 1, wherein the height n of the conductor posts is substantially the stack thickness of the chip package structures. 10. The stacked package structure of claim 1, wherein the guide pillars comprise a plurality of feed balls placed on the stack of the wafer sealing structure and aligned with the plurality The through-holes of the feed fresh balls and the longitudinally corresponding solder balls are reflowed to form the conductor posts. 11. A method of forming a conductor pillar in a stacked package structure, comprising the steps of: providing a plurality of chip package structures, each package structure comprising a substrate having a plurality of through holes and a substrate on the substrate a plurality of lines electrically connected to the through holes; stacking the chip package structures such that the through holes are longitudinally facing and placing a plurality of solder balls between the chip package structures Between the wafer slanting structures and aligned with the through holes; and reflowing the solder balls to form a plurality of conductive posts, the conductive posts are formed according to the shape of the through holes The substrates are in contact with each other to electrically connect the circuit layers. 12' The method of forming a conductor pillar in a stack-type package structure as described in claim U, wherein in the above-described mutual stacking step, the portion is placed before each of the wafer package structures is stacked The solder balls are in the through holes of another stacked chip package structure. 18 201017865 A method of forming a conductor fresh column in a stacked package structure as described in claim n, wherein a plurality of feed balls are placed after the chip package structures are stacked and before the solder balls are reflowed On the stack of the chip package structures and aligned with the through holes, the solder balls corresponding to the longitudinal direction are reflowed to form the conductor posts during the reflow process. 14. The method of forming a conductor post in a stacked package structure as described in claim 13 wherein the number of the feed balls and the total number of the balls are equal to the number of the holes. . 15. The method of forming a conductor post in a stacked package structure according to claim U, wherein in the step of stacking the chip packages, the solder balls have a size to enable the The solder balls are not completely trapped in the through holes and the adjacent solder balls are in contact with each other before reflow. 16. The method of forming a conductor pillar in a stacked package structure according to the above-mentioned patent application, wherein the wafers are disposed on a plurality of upper surfaces of the corresponding substrate, and a surface is formed on the lower surface of each substrate. A pocket that is aligned with the wafers. The method of forming a conductor pillar in a stacked package structure according to claim 11, wherein the circuit layers comprise a plurality of annular pads surrounding the through holes. 18, as claimed in the patent scope The method of forming a conductor post in a stacked package structure, wherein the wafers are disposed on the corresponding substrates in a flip chip bonding manner.