TW201209986A - Semiconductor package structure and manufacturing process thereof - Google Patents

Semiconductor package structure and manufacturing process thereof Download PDF

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Publication number
TW201209986A
TW201209986A TW099128499A TW99128499A TW201209986A TW 201209986 A TW201209986 A TW 201209986A TW 099128499 A TW099128499 A TW 099128499A TW 99128499 A TW99128499 A TW 99128499A TW 201209986 A TW201209986 A TW 201209986A
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Taiwan
Prior art keywords
wafer
semiconductor
primer
conductive bumps
interposer
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TW099128499A
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English (en)
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TWI398943B (zh
Inventor
Meng-Jen Wang
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Advanced Semiconductor Eng
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Priority to TW099128499A priority Critical patent/TWI398943B/zh
Priority to US12/907,028 priority patent/US8310063B2/en
Publication of TW201209986A publication Critical patent/TW201209986A/zh
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Publication of TWI398943B publication Critical patent/TWI398943B/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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201209986 /1 -NEW-FINAL-TW-20100825 六、發明說明： 【發明所屬之技術領域】 本發明疋有關於-種半導體封裝結構及其製程，且特 別是有關於一種具有穿矽導孔(thr〇ugh sinc〇n心，TSV)的 半導體封裝結構及其製程。 【先前技術】 在半導體封裝技術甲，穿梦導孔的作用是在晶片與晶 片間、晶圓與晶_製作垂直導通互連之角色，為目前三 維積體電路製程整合技術中，能實現晶片之間互連的關鍵 技，。有狀過去之積體電路封裝技術，藉由抑導孔技 術能使晶片在三維方向堆疊的密度最大化，外形尺寸降 低、’並提升7L件速度、減少信號延遲和功率消耗，因此石夕 導通孔被視為應用於三維積體電路技術之新_代的垂直式 内連線(Interconnect)結構。 一詳細*言’在半導體封裝製程當中，可先將半導體晶 圓薄化以使半導體晶Κ㈣穿料孔裸露，此時的半導體 曰曰圓了先暫時固疋在承載晶圓上，並且在未 進行切割的情況下，進行晶片對半導體晶_結合，接著 將半導體晶K絲載晶81分離，以對半導體晶圓進行後續 衣程^刀離半導體晶圓與承載晶圓時，半導體晶圓可能 曰因、’”構應力的變化而產生起曲變形的現象，降低製程良 率。 201209986 A5C.K2371-NEW-FINAL-TW-20100825 【發明内容】 度。本發明提供一種半導體封裝結構，具有铰佳的結構強 本發明提供-種半導體封裝製程，可避免半 在製造過程中翹曲變形。 日曰圓 本發明提出-種半導體封裝結構，包括綠路 -晶片、多個第-導電凸塊、第二晶片、多個第 凡 ί及三導電凸塊。線路栽板具有承載面 =於，面的底面。第一晶片設置於線路載板的承 載面上方，第一晶片具有第一表面以及相對於第一表面的 第二表面，第二表面面向線路載板，且第一 穿石夕導孔以及位於第-表面上的多個第—接塾與 接墊，第-接塾電性連接至所龍的穿料孔。第一導電 凸塊配置於第-晶片與線路載板之間，第—晶片的穿石夕導 孔分別經由第一導電凸塊電性連接至線路載板。第二晶片 配置於第-晶片上方’並且暴露出第—表面的局部區域。 第二導電凸塊分別配置於第一接墊上，第二晶片經由第二 導電凸塊雜連接輯對應的穿料孔。中介基材配置於 第一晶片上方，並且位於第一表面的局部區域内，中介基 材的頂面與第二晶片的頂面實質上相互齊平。第三導電凸 塊分別配置於第二接塾上，中介基材經由第三導電凸塊接 合至第二接塾。 在本發明之一實施例中，上述之中介基材的側面與第 一晶片的側面實質上相互齊平。 S] 5 201209986 /l-NEW-FINAL-TW-20100825 在本發明之一實施例中，上述之半導體封襞結 括第一底膠，填充於第一晶片與線路載板之間， 更包 包覆第一導電凸塊。 一底膠 在本發明之一實施例中，上述之半導 括第二底膠，填充於第二晶片與第-晶片之間；^構更包 包覆第二導電凸塊。底膠 在本發明之-實施例中’上述之半導體封裝 括第三底膠，填充於中介基材與第—晶片之間，^冓^ 包覆第三導電凸塊。 底膠 在本發明之-實施例中，上述之半導體 括多個銲球，配置於線路載板的底面。 ^冓更包 在本發明之-實施例中，上述之半導 =與㈣中介基材，一 ^ 介基材之間。 片之_及散熱片與中 在本發明之-實施财，上述之半導體 ，熱環’配置於線路載板上’並且園繞第一：片，導熱 %熱接合於散熱片與線路載板之間。 … 一實施例中’上述之散熱片接地。 本發月k出-種半導體封裝製程 晶圓，半導體晶圓具有第1而“以&供丰導體 個穿矽導孔。脑表 +導體晶_具有多 個牙石夕¥孔接耆，在第二表面上形成多個第一導電凸塊， 71 -NE W-FINAL-TW-20100825 201209986 第-導電凸塊分別電性連接至穿料孔。由第二表 側來薄化半導體㈣’以暴露出每—穿料㈣—端士 半導體晶圓的第-表面，每一穿石夕導孔的另一端連接第一 表面。在第-表面上形成多個第一接塾以及多個第 塾，其中第-接塾電性連接至所對應的穿梦導孔。接人= 個第二晶片至半導體晶圓的第一表面，其中每一第二曰 經由多個第二導電凸塊電性連接至所對應的第—接塾了形 成第二底膠於每—第二晶片與半導體晶圓之間，第二底膠 在每-第二晶片接合至半導體晶圓之前被預先形成於丰導 ，晶圓上’或是在每—第二晶片接合至半導體晶圓之後被 填入每-第二晶片與半導體晶圓之間，第二底膠包覆第二 導電凸塊。接合中介晶圓至半導體晶圓的第—表面，其中 中介晶@具有翅開孔分麟應並暴露第二晶#，中介晶 圓經由多個第三導電凸塊電性連接至所對應的第二接墊， 且中介晶圓的頂面與第二晶片的頂面實質上相互齊平。同 時，切中μ晶圓與半導體晶圓，以形成多個封裝單元，其 :半導體晶圓被裁切為多個相互分離的第—晶片，且中^ 晶圓被裁切為多個相互分離的中介基材。接合封裴單元^ =路載板’其中第—晶片的穿⑦導孔經由所對應 電凸塊電性連接至線路載板。 =判之-實施财，上狀半導體塊製程更包 =成第一底膠於第一晶片與線路載板之間，第一底膠在 t晶ί接合至線路載板之後被填人第—晶片與線路i板 弋間，第一底膠包覆第一導電凸塊。 201209986 在本發明之一實施例中，
在本發明之一實施例中， 括配置散熱片於封裝單元上， 二晶片與中介基材》 第三底膠包覆第三導電凸塊。 中，上述之半導體封裝製程更包 上’散熱片覆蓋並且熱接合至第 基於上述，在本發明的半導體封裝製程中，於半導體 晶圓被第二晶片暴露的部分配置+介晶圓，以提升整體結 構強度’而可避免半導體晶圓在製造過程中因應力變化而 產生翹曲變形的現象。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 、 【實施方式】 圖1A至圖1K為本發明一實施例之半導體封裝製程 的流程圖。請參考圖1A，首先，提供半導體晶圓5〇，其 中半導體晶圓50具有第二表面52,且半導體晶圓5〇内^ 有多個穿矽導孔126。在第二表面52上形成多個第一導電 凸塊130’第一導電凸塊130分別電性連接至穿矽導孔126。 接著’如圖1B所示，將圖1A的半導體晶圓5〇及第 一導電凸塊130固定於一承載件(例如一承載晶圓6〇)上。 請參考圖1C’由第二表面52的對側來薄化半導體晶圓 201209986 71 -NEW-FINAL.TW-20100825 50’以暴露出每一穿矽導孔丨26的一端以及半導體晶圓5〇 的第一表面54。在第一表面54上形成多個第一接墊122a 以及多個第二接墊122b，其中第一接墊122a電性連接至 所對應的穿矽導孔126。 請參考圖1D，接合多個第二晶片14〇至半導體晶圓 50的第一表面54’其中每一第二晶片14〇經由多個第二導 電凸塊150連接至所對應的第一接墊122&。請參考圖1£， 形成第二底膠18〇b於每一第二晶片14〇與半導體晶圓5〇 之間以包覆第二導電凸塊150。在本實施例中，第二底膠 180b在每一第二晶片140接合至半導體晶圓5〇之後被填 入每一第二晶片140與半導體晶圓50之間。然本發明不以 此為限，亦可在每一第二晶片140接合至半導體晶圓5〇 之前，預先形成第二底膠180b於半導體晶圓50上。 圖2為應用於圖ία至圖ΐκ之半導體封裴製程的中 介曰曰圓的示意圖。請參考圖if及圖2，接合中介晶圓70 至半導體晶圓50的第一表面54,其中中介晶圓70具有多 _ 個開孔72分別對應並暴露第二晶片140。中介晶圓70經 由多個第三導電凸塊170電性連接至所對應的第二接墊 122b’且中介晶圓70的頂面與第二晶片14〇的頂面實質上 相互齊平。需注意的是，在其它實施例中，亦可先接合中 介晶圓70至半導體晶圓50，再接合第二晶片14〇至半導 體晶圓50，本發明不對其順序加以限制。 凊參考圖1G，形成第三底膠18〇c於中介晶圓7〇與 半導體晶圓50之間以包覆第三導電凸塊17〇。在本實施例 201209986 ASEK23 71 -NEW-FINAL-TW-20100825 中，第二底膠180c在中介晶圓70接合至半導體晶圓5〇 之後被填入中介晶圓70與半導體晶圓5〇之間。然^發明 不以此為限，第三底膠18〜亦可在中介晶圓7〇&合至半 導體晶圓50之前被預先形成於半導體晶圓5〇上。此外， 第二底膠180c非本發明必要元件，亦即可以省略= 180c形成步驟。 二版膠 e月參考圖1H，移除承載晶圓6〇，並同時裁切 曰 圓70與半導體晶圓50，以形成多個封裝單元8〇，其中= 導體晶圓50被裁切為多個相互分離的第一晶片且中 介晶圓70被裁切為多個相互分離的中介基材16〇，其中中 介基材160的側面與第一晶片12〇的側面實質上^目互齊 平。半導體晶圓50例如是以膠合的方式固定於承载晶圓 60 ’當移除承載晶圓60時’半導體晶圓5〇可能會因結構 應力的變化而翹曲變形。配置於半導體晶圓5〇上的中介晶 圓70具有&升整體結構強度的效果，因此可避免半導體晶 圓50與承載晶圓60分離時產生所述翹曲變形的現象，或 降低其麵曲變形的程度。 请參考圖II，接合封裝單元8〇至線路載板11〇，其中 第-晶片120的穿石夕導孔126經由所對應的第一導電凸塊 130電性連接至線路載板11()。請參考圖丨了，形成第一底 膝180a於第一晶片120與線路載板11〇之間以包覆第一導 電凸塊130。第一底膠職在第一晶片12〇接合至線路载 板no之後被填入第一晶片120與線路載板110之間。請 參考圖1K’配置多個鲜球190於線路载板11〇的底面114, 201209986 ^.^rs2371-NEW-FINAL-TW-20100825 而完成半導體封裝結構100的製作。 半導體封装結構1〇〇包括線路載板11()、第一晶片 120、多個第一導電凸塊130、第二晶片14〇、多個第二導 電凸塊150、中介基材160、多個第三導電凸塊17〇、第一 底膠180a、第二底膠180b、第三底膠18〇c及多個銲球 190。線路載板11〇具有承載面112以及相對於承載面ιΐ2 的底面114。第一晶片120設置於線路載板11〇的承载面 112上方，第一晶片120具有第一表面122以及相對於第 _ -表面122的第二表面124 ’第二表面124面向線路載板 110’且第一晶片120具有多個穿矽導孔126以及位於第一 表面122上的多個第一接墊122a與多個第二接墊12几。 第一接墊122a電性連接至所對應的穿矽導孔126，第 二接塾122b亦連接穿矽導孔126，以達到較佳的散熱效 果。第一導電凸塊130配置於第一晶片12〇與線路載板11〇 之間，第一晶片120的穿矽導孔126分別經由第一導電凸 塊130電性連接至線路載板11〇。第二晶片14〇配置於第 • 一晶片120上方，並且暴露出第一表面122的局部區域。 第二導電凸塊150分別配置於第一接墊1223上，第二晶片 140經由第二導電凸塊15〇電性連接至所對應的穿矽導孔 126。中介基材160配置於第一晶片12〇上方，並且位於第 一表面122被第二晶片140暴露的局部區域内。 中介基材160的頂面與第二晶片14〇的頂面實質上相 互齊平。第二導電凸塊170分別配置於第二接墊122b上， 中介基材160經由第三導電凸塊17〇接合至第二接墊 E S] 11 201209986 / l-NEW-FINAL-TW-20100825 122b。銲球190配置於線路載板11()的底面114，使半導 體封裝結構100適於透過銲球190電性連接其它元件。第 一底膠180a配置於第一晶片120與線路載板11〇之間以包 覆第一導電凸塊130。第二底膠i80b配置於第二晶片140 與第一晶片120之間以包覆第二導電凸塊15〇。第三底膠 180c配置於中介基材160與第一晶片】20之間以包覆第三 導電凸塊170。此外，在其它實施例中，第三底膠18〇〇亦 可同時包覆第一晶片120、第二晶片14〇、中介基材16〇 及第三導電凸塊170。 圖3為圖1K之半導體封裝結構配置散熱片的示意 圖。請參考圖3，在完成圖丨尺所示之半導體封農結構1〇〇 之後，可配置圍繞第一晶片丨2〇的導熱環9〇b於線路载板 110上。接著，配置散熱片90a於封裝單元80上，散熱片 80覆蓋並且熱接合至第二晶片14〇與中介基材16〇，導熱 環90b熱接合於散熱片9〇a與線路載板11〇之間。所述熱 接合係指可使兩元件之間達成良好之熱傳導的接合方式， 其間可旎存在其它的導熱黏著層，如導熱膠9〇d及導熱膠 90e〇由於本實施例的中介基材16〇的頂面與第二晶片14〇 的頂面實質上相互齊平，因此第二晶片14〇與中介基材16〇 適於共同支撐散熱片9〇a，讓整體結構更為穩固。 此外，可於散熱片90a與第二晶片14〇之間以及散熱 片110與中介基材16〇之間形成導熱膠9〇e以固定散熱片 90a半導體封裝結構1〇〇產生的熱可透過導熱環9〇b及導 熱膠90c傳遞至散熱片9〇a以進行散熱。在本實施例中， 12 201209986 71 -KE W-FINAL-TW-20100825 散熱片90a除了具有散熱功能之外，半導體封裝結構1〇〇 更可藉由散熱片90a進行接地。在其它實施例中，散熱片 9〇a亦可為其它型態，如散熱片9〇a與導熱環9〇b 一體成 型，或僅配置散熱片90a而不配置導熱環9〇b。 综上所述，在本發明的半導體封裝製程中，於半導體 晶圓被第二晶片暴露的部分配置中介晶圓，以提升整體結 構強度，而可聽半導體晶圓在製造過程中因應力變化而 產生輕曲變料現象。料，半導體封裝結構具有由裁切 中介晶圓而形成的中介基材，中介基材圍繞第二晶片且可 與第二晶#共同支撐散熱#，而使半導 佳的結構強度。 太路Γ然2發明6以實施_露如上’財並麵以限定 月何所屬技術領域巾具#通常知識者，在不脫離 本發明之精神和範_，當可作些許之更動與 發明之保護範圍當視後附之中請專利範圍所界定者為=本 【圖式簡單說明】 的流=至圓1κ為本發明-實施例之_封裝製程 介晶圓圖的 於圖1Α至圓1〖之半導體封裝製程的中 示意圖 圖3為圖ικ之半導體封裝結構配技熱片的 【主要元件符號說明】
13 201209986 ASEK23 71 -NEW-FTNAL-TW-20100825 50 :半導體晶圓 52、124 :第二表面 54、122 :第一表面 60 :承載晶圓 70 :中介晶圓 72 :開孔 80 :封裝單元 90a :散熱片 90b :導熱環 90c、90d、90e :導熱膠 100 :半導體封裝結構 110 :線路載板 112 :承載面 114 :底面 120 :第一晶片 122a :第一接墊 122b :第二接墊 126 :穿矽導孔 130 :第一導電凸塊 140:第二晶片 150 :第二導電凸塊 160 :中介基材 170 :第三導電凸塊 180a :第一底膠 201209986
Aar,is2371-NE W-FINAL-TW-20100825 180b :第二底膠 180c ··第三底膠 190 :鮮球

Claims (2)

  1. 201209986 /l-NEW-FINAL-TW-20100825 七、申請專利範团： 1. 一種半導體封裝結構，包括·· 一線路载板，具有-林面以及相對於該承載面的一 底面； 一曰-第-晶片’設置於該線路載板的承載面上方，該第 -晶片具有-第-表面以及相對於該第—表面的一第二表 面’該第二表面面向該線路载板，且該第一晶片具有多個 穿梦導孔以及位於該第-表面上的多個第___接墊與多個第 一接墊’該些第一接墊電性連接至所對應的該些穿矽導孔； 多個第一導電凸塊，配置於該第一晶片與該線路載板 之間，該第一晶片的該些穿矽導孔分別經由該些第一導電 凸塊電性連接至該線路載板； 一第二晶片，配置於該第一晶片上方，並且暴露出該 第一表面的局部區域； 多個第二導電凸塊，分別配置於該些第一接塾上，該 第二晶片經由該些第二導電凸塊電性連接至所對應的該些 穿矽導孔； 中介基材’配置於該第一晶片上方，並且位於該第 一表面的局部區域内’該中介基材的頂面與該第二晶片的 頂面實質上相互齊平；以及 多個第三導電凸塊，分別配置於該些第二接塾上，該 中介基材經由該些第三導電凸塊接合至該些第二接塾。 2.如申請專利範圍第1項所述之半導體封裝結構，其 中該中介基材的側面與該第一晶片的側面實質上相互齊 201209986
  2. 71 -NEW-FINAL-TW-20100825 包括 3·如申請專利範圍第1項所述之半導體封裝結構，更 兮笛一 真充於該第一晶片與該線路載板之間， 該第底膠包覆該些第一導電凸塊。 4.如申請專利範圍第！項所述之半導體封裝結構，更 包括· -第二底膠，於該第二晶片與該第片之 該第二底膠包覆該些第二導電凸塊。 5·如申清專利範圍第丨項所述之半導體封裝結構，更 包括. 一第三底膠，填充於該中介基材與該第一晶片之 該第三底膠包覆該些第三導電凸塊。 6.如申請專職㈣丨項所述之半導體封裝結構 包括： 多個銲球，配置於該線路載板的該底面。 7·如申請專利範圍第1項所述之半導體封裝結構，更 包括： 一散熱片，覆蓋該第二晶片與該中介基材，且該散熱 片熱接合至該第二晶片與該中介基材。 ， 8·如申請專利範圍第7項所述之半導體封裝結構，更 包括： 一導熱％，配置於該線路載板上，並且圍繞該第一晶 片，該導熱環熱接合於該散熱片與該線路載板之間。 [Si 17 201209986 / l-NEW-FIKAL-TW-20100825 9. 一種半導體封裝製程，包括： 提供一半導體晶圓，該半導體晶圓具有一第二表面， 且該半導體晶圓内具有多個穿矽導孔； 在該第二表面上形成多個第一導電凸塊，該些第一導 電凸塊分別電性連接至該些穿矽導孔； 由該第二表面的對側來薄化該半導體晶圓，以暴露出 每一穿矽導孔的一端以及該半導體晶圓的一第一表面； 在該第一表面上形成多個第一接墊以及多個第二接 墊’其中該些第一接墊電性連接至所對應的該些穿矽導孔; 接合多個第二晶片至該半導體晶圓的該第一表面，其 中每一第二晶片經由多個第二導電凸塊連接至所對應的該 些第一接墊； 形成一第二底膠於每一第二晶片與該半導體晶圓之 間，該第二底膠在每一第二晶片接合至該半導體晶圓之前 被預先形成於該半導體晶圓上，或是在每一第二晶片接合 至該半導體晶圓之後被填人每H片與該半導體晶圓 之間，該第一底膠包覆該些第二導電凸塊，· 接合一中介晶圓至該半導體晶圓的該第一表面，1中 該中介晶圓具有多個分騎應並暴露該些第二晶片， 該=晶圓經由多個第三導電凸塊電性連接至所對應的該 ^接塾’且該中介晶圓的頂面與該第二晶片的頂 質上相互齊平； 同時，該中介晶料導體晶圓，以形成多個封 裝早70，其中該半導體晶圓被裁切為多個相互分離的第一 18 201209986 …一2371-NEW-FmAL-TW-20100825 ’且辦介晶圓被裁切為多個相互分離的中介基材； 接合該封裝單元至—線路餘，其中該第-晶片的該 些穿梦導孔經由所對應的該些第—導電凸塊電性連接至該 嫂^ 5^截杯。 10.如申請專利範圍第9項所述之半導體封裝製程， 更包括：
    形成第一底膠於該第·~晶片與該線路載板之間，該 第底膠在該第-晶片接合至該線路载板之後被填入該第 -晶片與該線路載板之間’該第—底膠包覆該些第一導電 凸域。 11.如申請專利範圍第9項所述之半導體封裝製程， 更包括： 开y成第二底膠於該中介晶圓與該半導體晶圓之 間’該第二底膠在該中介晶圓接合半導體晶圓之前被 預先形成於該半導體晶圓上，或是在該中介晶圓接合至該 半導體晶圓.之後被填人該中介晶圓與該半導體之' 該第三底膠包覆該些第三導電凸塊。 12.如申請專利範圍第9項所述之半導體封制 更包括： '"衣 配置-散熱片於該封裝單元上，該散熱片覆蓋並且執 接合至該第二晶片與該中介基材。 …
TW099128499A 2010-08-25 2010-08-25 半導體封裝結構及其製程 TWI398943B (zh)

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