201205099 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種托盤機構（tray unit)及半導體元件 (device)的檢查設備，特別是指一種為了進行半導體元件之 各種特性測試的托盤機構（tray unit)及半導體元件檢杳設 備。 【先前技術】 按，長久以來，存在著測試物為半導體元件而給予高溫 或低溫之溫度衝擊的半導體元件(device)檢查設備。 半導體元件(device)之檢查設備，具有例如給予半導體 元件向溫或低溫之溫度衝擊的怪溫爐，與在此怪溫爐内給予 半導體元件熱衝擊狀態下，與測試頭（test head)作電氣性的 接觸’作電氣特性測試的測試爐體（test chamber)，與從經 測試爐體（test chamber)所測試過的半導體元件，除去其所 受之熱衝擊的除熱爐。 像這樣的半導體元件(device)檢查設備為了同時測試多 個半導體元件（device)，會使用多個承載半導體元件的插座 板（socket board)。 有關像這樣使用插座板(socket board)的半導體元件檢 查設備有各種的提案。 例如，在專利公開2000-304808號公報宣告，同時增加 可檢查之半導體設備的數量，來降低檢查設備的成本。另 外’可穩定檢查工程的半導體設備之檢查設備。 在此半導體設備的檢查設備上，於印刷基板上依序裝有 加熱器多層配線基板及異方導電性橡膠片，在異方導電性橡膠 201205099 。。，置有讀半導體封裝之多層配線基板位置的定位部 圍右的上方設有推壓部品的推屋板。此推壓板的周 板形二=γΓ:°:，，纖、墊圈部品及多層配線基 ,g ^ θ右將畨封空間減壓，墊圈部品會作動，藉 搞杏電性橡膠片，半導體的封裝凸塊與多層配線基板的電 極可確實麟魏性連接。 另外*專利公開2007-309787號公報，說明可將置放 絲6托盤（杜办)之全部的半導體元件(device), -次全部移 至谷易作測試專用托盤(tray)的測試托盤(tray)構造。 先進技術文獻： 曰本專利公開2000-3Q4808號公報 曰本專利公開2007-30978 7號公報 【發明内容】 、近年來’半導體元件(device)伴隨著其高密度化及電路 的複雜化，測試一個半導體元件(device)所需的時間有變長 的傾向，為了降低測試成本，期望半導體元件(device)測試 能更加效率化。 另外，因半導體元件(device)漸漸有多包裝且少量生產 的傾向，故需頻繁地變更對應各種半導體元件(device)之溫 度條件等的測試環境。 但是’在關係到上述專利公開2000-304808號公報之前 技術，連接基板(連接board)是被固定的，對於特殊的腳排 列之半導體元件(device)，有無法迅速對應的問題存在。 另外’腳的排列會依每一半導體元件((1〜丨(^)的構造不 同而有所不同，以前必須依各種半導體元件（device)構造、 201205099 準備配合其腳排列的插座（socket)或插座板（socket board)，因此有增加成本的困擾。 此外，隨著檢查用腳(柱）數的增加，插座（s〇cket)本身 ，格就會增加。因歧會產生檢纽備之成核檢查成本升 高的問題。特別是’因細微化、高難化而需要測試時間長 的元件（兀件）增加，造成檢查效率降低及檢查成本上升等大 問題。 另外，在近年的半導體元件（元件）預燒測試（沁 test)及最終測試（f inal test)是藉由稱為上下板機 (handler)的自動機，由托盤（什即)將IC移至預 in board)上的插座^㈤^仂，或是移至測試機（“对打）之 載具(carrier)上的載具插座（carrier s〇cket)，之後在預 燒爐或疋測試上下板機（test handler)之測試平台（test stage)上作檢查。 因此，可一次檢查的處理數量的界限及高價多量使用的 插座（socket)或板(board)等等，所產生之測試成本的升高 就會成為一個很大的課題。 门 另外，部份邏輯產品是在封裝線上作測試，但含記憶體 多數的7〇件檢查都是設有檢查專用工程，而且使用專用的測 試上下板機（test handler)與一體的系統，而無法實現效 率的生產線的問題點。 另一方面，在作為比較對象之承載半導體元件的托盤 (1C托盤）是由構成半導體元件之承載部的樹脂部與承載此 脂部的高熱傳導性金屬所形成的基板(base)K構成。 另外，半導體元件與測試板(test board)作電氣性接觸 的連接基板(contact board)的對位是藉由例如在托盤的四 201205099 角落所製成的定位孔來進行。 但是，因樹脂與金屬的膨脹係數不同，以比較薄的樹脂 板作成型時，其細旨部料產生熱變形，會有因托盤(tray) 放置70件的孔與元件料型的_，而產生高精度對位困難 的問題點。 特別妓板及滅(tray)的長度是·_左右比較大尺 、時’連接基板(連接b〇ard)的腳與托盤(tray)内半導體元 ^的腳之對位⑽位解手段）_，而且減（㈣)與托盤 lfay)畔導體元件關料均是無㈣㈣，會有高精度 對位困難的問題點。 因此’本發明可提供更有效率且低成本的半導體元件測 -、及可在托盤（tray)上提升對位精度的托盤機構（吻 unit)及半導體元件的檢查設備。 為了解決上述之課題，關於申請項j發明之托盤機構 ^ ay/nit)，是可將檢查對象之半導體元件分為多個承 =，是與形成底部之底部部材與置放在此底板部材上具在水 ^向分個，各自分刺定的轉體元件辭導體元件 t盤。削述半導體讀的腳是向上的狀態，可容易裝脫 供要f試各個半導體元件的電氣特性之半導體元件檢查設 述的各轉體元件承财糾所設之定位手段尚 疋位之’，會縣在姆前述底板部材所定容許範圍之 =向的移紐㉟。知述底板部材的上面，定位在半導 孔几將的突起部’或形成有抑制半導體移動的角 别料導體几件托躺所定的方向顧_時，半導 又S'备2同向移動，藉由推向前述底板部材所設的交 *、犬起’財具備將前料導體元件與㈣半導體承 201205099 載托盤的間隙消除的手段。前述之定位手段是具備有【設在 前述半導體承載托盤的對位孔】與【設在前述半導體元件承 載托盤對向之連接板側，嵌入前述對位用的孔進行前述半導 體元件承載托盤與前述連接基板定位的對位柱】，與由前述 對位用孔拔出對位用的柱時，藉由彈力將前述半導體元件承 載托盤復歸至前述所定之方向與反方向的原位置之推壓手段 的特徵。 關於申凊項2發明的半導體元件檢查設備是具備有記載 於申請項1之托盤機構(tray unit)的承載部，與裝載在前 述托盤機構(tray unit)上的半導體元件的腳作電氣性導通 而進行電紐測試制試板。在前述測試板與前述半導體元 $承載托盤之間設有為了要將前述托盤機構(⑽如⑴所 又半導體元件承載托盤上的各個半導體元件的電極腳與前述 測試^上的電極端子料連接基板，與藉由前述連接基 板’前述的半導體元件與麵的職 構。前述的咖㈣蝴输_耕^ =該升降手段前叙置放部相對軸至所定位置時，前述 ^導f元件的腳與前述連接基板，該連接基板與前述測試 主他們各自緊密結合吸取貞壓之賴手段所構成。前述 端之2是由圈在前述連接基板框·或是前述置放部的頂 材與該置放部移動時’連接在前述連接基板框或 連接々合的塾卿材，與述連接基板框，前述 空述纽部及前料_材卿成_槽内的真 可藉由本發明得到以下效果。 若是藉由申請項1所記_發明，賴料料件承載 7 201205099 托盤去所承載的半導體元件的電氣特性的測試，則有可 測試效率及可降低測試成本的優點。 ^卜，托盤機構(tray unit)是由形成底部的底板部材 ”置放在此絲部材上且在水平方向分域個各自分 體元件數量之半導體元件承載牦盤所構成，可抑制 ==等’更雜_轉航件航件㈣辭段作電氣 另外，藉由申請項1所記载的發明，則各半導體元件 載托^是在尚柄粒手段進行定位之前，相對於底板部材 ，水平方向的移動，保持在料所定範圍内的浮動 (floatmg)構造，以定位手段所作的定赠度會提升。 更進-步’藉由中請項丨所記載之發明，可將托盤 難㈣。錄態下作雜，將使對位精 度棱升，電氣性的連接會更確實。 藉由申請項i所記載的發明，可以簡單構造使 =之腳與連接基板的對位精度提升，電氣性的連接會更確 貫。201205099 VI. Description of the Invention: [Technical Field] The present invention relates to an inspection apparatus for a tray unit and a semiconductor device, and more particularly to a tray mechanism for performing various characteristic tests of a semiconductor element ( Tray unit) and semiconductor component inspection equipment. [Prior Art] According to the prior art, there has been a semiconductor device inspection apparatus in which a test object is a semiconductor element and is subjected to a high temperature or low temperature temperature impact. The inspection device of the semiconductor device has, for example, a strange temperature furnace that gives a temperature shock to the temperature of the semiconductor element to a temperature or a low temperature, and is electrically connected to the test head in a state in which the semiconductor element is thermally shocked in the strange temperature furnace. Sexual contact 'test chamber for electrical characteristic testing, and de-heating furnace for removing the thermal shock from the semiconductor components tested from the tested test chamber. A semiconductor device inspection apparatus such as this uses a plurality of socket boards that carry semiconductor elements in order to simultaneously test a plurality of semiconductor devices. There are various proposals for a semiconductor element inspection apparatus using a socket board as described above. For example, Patent Publication No. 2000-304808 discloses that the number of semiconductor devices that can be inspected is increased at the same time to reduce the cost of the inspection apparatus. In addition, it is possible to inspect inspection equipment for semiconductor equipment. In the inspection apparatus of the semiconductor device, a heater multilayer wiring substrate and an anisotropic conductive rubber sheet are sequentially mounted on the printed substrate, in the anisotropic conductive rubber 201205099. . A positioning portion for reading the position of the multilayer wiring substrate of the semiconductor package is provided with a pusher plate for pressing the component on the upper right side. The plate shape of the push plate is 2 = γ Γ: °:,, the fiber, the gasket part and the multilayer wiring base, g ^ θ right will decompress the space, the gasket part will act, and the apricot electric rubber piece, semiconductor The package bumps and the electrodes of the multilayer wiring substrate can be connected to each other. In addition, Japanese Patent Laid-Open Publication No. 2007-309787 discloses that all of the semiconductor devices of the wire 6 tray can be moved to the test tray of the valley test tray (tray). )structure. 。 。 2000 2000 2000 2000 2000 2000 2000 -30 -30 -30 -30 -30 -30 -30 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The time required for a semiconductor device tends to become longer, and in order to reduce the test cost, it is desirable that the semiconductor device test be more efficient. Further, since semiconductor devices are gradually becoming more packaged and produced in a small amount, it is necessary to frequently change the test environment corresponding to the temperature conditions of various semiconductor devices. However, in connection with the prior art, the connection board (the connection board) is fixed, and there is a problem that the semiconductor device of the special leg array cannot be quickly responded. In addition, the arrangement of the feet will vary depending on the structure of each semiconductor component (1~丨(^). Previously, it must be constructed according to various semiconductor devices, and 201205099 is prepared to fit the sockets of its feet or The socket board has a problem of increasing the cost. In addition, as the number of inspection feet (pillars) increases, the size of the socket itself increases, and the difference is generated. The problem of increasing the cost of nuclear inspections, especially the increase in the number of components (components) that require long test times due to the miniaturization and high difficulty, which causes problems such as reduced inspection efficiency and increased inspection costs. In addition, semiconductor components in recent years. (component) burn test (沁test) and final test (f inal test) is a socket on the tray (that is, the IC is moved to the pre-in board) by an automaton called a handler. ^(五)^仂, or move to the tester (carrier) on the carrier (carrier s〇cket), then test the test handler in the pre-burner or 疋Check on the test stage. Therefore, the limit of the number of processes that can be inspected at one time and the socket or board used for high-priced and large quantities, etc., will increase the test cost, which becomes a big problem. The product is tested on the package line, but the 7-piece inspection with the majority of the memory is equipped with a special inspection project, and uses a dedicated test handler and an integrated system, and cannot achieve an efficient production line. On the other hand, the tray (1C tray) carrying the semiconductor element as a comparison object is a substrate K formed of a resin portion constituting a carrier portion of the semiconductor element and a highly thermally conductive metal carrying the grease portion. Further, the alignment of the contact board in which the semiconductor element is in electrical contact with the test board is performed by, for example, a positioning hole made at the corner of the four 201205099 of the tray. Different from the expansion coefficient of metal, when a relatively thin resin plate is used for molding, the details of the material are thermally deformed, and 70 pieces of trays are placed. With the _ of the component type, the problem of high-precision alignment is difficult. The length of the special fascia and the tray is the length of the _, and the foot and the tray of the connecting substrate (connecting b〇ard) (tray) the position of the semiconductor element ^ (10) bit solution) _, and minus ((4)) and the tray lfay) side conductor elements are not (4) (four), there will be problems with high precision alignment. The present invention can provide a more efficient and low-cost semiconductor device measurement, and an inspection device for a tray unit and a semiconductor element that can improve the alignment accuracy on a tray. In order to solve the above problems, the tray mechanism ^ ay / nit of the invention of claim j is capable of dividing the semiconductor component to be inspected into a plurality of bearings, and is formed on the bottom member and the bottom member. The rotating element of the rotating element is divided into two pieces, and each of the rotating elements is a t-disc. The state in which the semiconductor read pin is in the up state is easy to be removed, and the positioning means for each of the swivel components of the semiconductor component inspection and design which are required to test the electrical characteristics of the respective semiconductor elements are still in place. The county is in the range of the allowable range of the above-mentioned bottom plate member. It is known that the upper surface of the bottom plate member is positioned in the protrusion portion of the semi-conductive hole or the direction in which a plurality of corner conductors for suppressing the movement of the semiconductor are placed, and the semi-conductive and S'-reading 2 move in the same direction. By means of the intersection of the bottom plate member and the dog, the means for eliminating the gap between the front material conductor element and the (4) semiconductor carrier 201205099 carrier tray is eliminated. The positioning means is provided with a "alignment hole provided in the semiconductor carrier tray" and a side of the connection plate provided on the opposite side of the semiconductor element carrier tray, and the hole for inserting the alignment is performed to perform the semiconductor element carrier tray and the aforementioned When the alignment column for positioning the substrate is removed, and the column for alignment is pulled out from the alignment hole, the pressing means for returning the semiconductor component carrier tray to the original position in the opposite direction and the opposite direction by elastic force is used Characteristics. The semiconductor element inspection apparatus according to the invention of claim 2 is provided with a carrier unit described in the tray unit of claim 1, and is electrically connected to the leg of the semiconductor element mounted on the tray unit. And the electric button test test board. Between the foregoing test board and the semiconductor element carrier tray, there is provided a substrate for connecting the electrode pins of the respective semiconductor elements on the semiconductor component carrying tray and the electrode terminal of the test piece to the tray mechanism (10) And the structure of the semiconductor element and the surface of the above-mentioned connecting substrate 'the aforementioned substrate. The above-mentioned coffee (4) butterfly _ _ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ And the connecting substrate, wherein the connecting substrate and the test main body are respectively closely combined with the means for sucking and pressing, and the end 2 is formed by the top plate of the connecting substrate frame or the placing portion When the placing portion moves, the connection between the connecting substrate frame and the joining of the sapling material and the connecting substrate frame, the contents of the hollow portion and the front material, and the groove can be obtained by the present invention. If the invention is based on the invention, the test of the electrical characteristics of the semiconductor components carried by the 201205099 pallet is tested, and the test efficiency and the test cost can be reduced. Advantages. The tray unit is formed by a bottom plate member forming a bottom portion, which is placed on the wire member and is divided into a plurality of semiconductor component carrier disks in the horizontal direction. =[More] _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The movement in the horizontal direction maintains the floatmg structure within the range specified by the material, and the contribution degree by the positioning means will increase. Further, the invention can be made difficult by the invention described in the item (4) In the recording state, the alignment accuracy will be sharpened, and the electrical connection will be more accurate. With the invention described in the application item i, the alignment accuracy of the foot and the connection substrate can be improved simply. Electrical connections will be more consistent.
藉由申請項1所記載的發明，可以簡 件承載托舰復至原麵位置。 #4+導體7C ^藉::請項1所記載的發明，可對應腳位排列不同的半 ^請或獨料導體元件，可提制試效率及降低測Ϊ 彼j外藉由申清項2所記載的發明，半導體元件腳與連 接基板可更確實地作電氣性連接。 【實施方式】 201205099 本發明所知：供之一種「托盤機構（tray 及半導體 元件（device)的檢查設備」，以下，為了實施本發明最佳形 態，將一面參照圖面來具體說明。在此，於附加的圖面同 一個部材是以同一個符號作表示。另外，重覆的說明會省 略。再者，在此的說明是實施本發明的最佳形態，但不侷限 於此形態。 由圖1至ffl 3所示之第1實施形態的半導體元件檢查設 備Μ1具有承載檢查對象為半導體元件d如圖8、圖9所示 之托盤機構(托盤unit)(承載半導體元件托盤的一例） 及在托盤機構(tray unit)U 1所承載半導體元件⑽電極腳 1 〇 1作電氣性導制試半導體元件電氣特性的測試機 構(test unit)2 ◦ 〇 (元件檢查手段的一例）所用之測試母 板TM (測試母板的一例）·及設在測試母板丁M對向、對 應測試母板ΤΜ腳排列之第1的接觸針（連接柱^^ 〇 2 (導 電手段的一例）的第1連接基板〇 i及在第丨連接基板◦工 對向’可因應半導體元件D電極腳i Q i的制與測試母板τ Μ上之腳排列有所不同而轉換腳排列的可更換之轉換板3 〇 〇.及設在轉換板3 〇 0與托盤機構(tray unit)之間、因應 半導體元件D電極腳1 〇 1的排列設有接觸針(連接柱）工 ◦ 3 (導電手段的一例）、與該接觸針(連接柱）丄〇 3直 接與半導體元件D作導通的第2連接基板C 2.及藉由第1連 接基板C1、轉換板3〇〇與第2連接基板C2、將半導體 το件D與連接在測試母板TM之測試機構2 Q 〇作電氣性連 接的連接機構400(連接手段的一例）。 201205099 半導體元件承載托盤（框（Frame)2002)可分複數個承載 半導體元件D檢查對象，托盤機構(tray unit)可裝載複數個 框(Frame)2002 。 托盤機構(tray unit)U可設計成具有儲存測試機構(test unit)2000所作檢查之結果的相關資訊（例如包含識別托盤機 構(tray unit) U1 之ID 資料等）記憶體(Memory)、rfID(IC標 籤）或標籤識別（Bar code)等（無圖示）功能。 依據這個，例如根據托盤的ID(識別號碼），可進行將不 良品以良品替換、分類不良品等的處理，可提高便利性。 另外，以導電膠、異方性導電片等代替接觸針(連接柱), 來構成前面記載的導電手段。 測試機構(test un i t) 20 0是可設在圖2所示的測試母板τ Μ的正上方，或設在測試母板tm的延長部的正面侧2〇〇，裡 面侧200也都可以。 同時測試機構(test unit)200也藉由同軸電缓線的連接 等，設在外部也可以。 另外，在此實施的形態上，半導體元件D是要電極腳ιοί朝 上地置放在托盤機構(tray unit) U1上。 具有藉由第1連接基板Cl、轉換板3 〇〇與第2連接基 板C 2、將半導體元件D與連接在測試母板tm之測試機構 2 0 〇作電氣性連接的連接機構4 〇 〇 (連接手段的一 例）。 在此實施的形遙上，連接機構400具有裝載托盤機構(tray unit) U1的裝載部401.及將裝載部4〇i對第2連接基板c 2作 201205099 昇降的作動器（actuator)(例如，以汽缸所構成的昇降手段 402)。 且在此實施的形態上，連接機構400是由設在裝載部4〇1兩 側之昇降手段4〇2，與藉由昇降手段4〇2上升至裝載部4〇1所訂 的位置為止時’吸負壓使半導體元件!)上的電極腳1〇1和連接 基板C 2作緊密結合的真空幫浦5〇〇(減壓方式範例)所構成。 另外’減壓手段是藉由真空幫浦5〇〇,將以設在圈住第2連 接基板C 2的連接基板框403，或是設在裝載部401上部，裝 載部401上升時，連接基板框4〇3或是裝载部4〇1都會碰到的墊 圈密封部品404與連接基板框403、第1連接基板C1及、裝載 部401所形成的減壓爐體55〇内的空氣，抽成真空。 另外，真空幫浦500具有減壓調整的減壓閥560。 既是、藉由昇降手段402對連接基板框403加壓，下壓半 導體元件D的表面及托盤機構（托盤⑽沅）讥的上面，對墊圈 密封部品404加預壓後，起動連接在真空幫浦500的減壓閥 560，減壓爐體550開始減壓，藉由熱板7〇1會更加下壓半導體 兀件D及托盤機構(tray unit)ui，第丨連接基板c i、轉換板 3 0 0與第2連接基板C 2會對測試母板TM加壓，置放在 托盤機構(tray unit)Ul的半導體元件D和測試母板τ Μ間全 部的接觸會以所定的力，全部被連接。 這樣藉由此實施的形態的半導體元件檢查設備Ml可機 動地對應特殊腳排列的半導體元件!)或特殊構造的半導體元 件，可提升測試效率的同時降低測試的成本。 減壓方式並不限於上面所記載的配置，若藉由第丨連接基 201205099 板Cl、轉換板3 〇 〇與第2連接基板c 2,可將半導體元件 D和測試母板TM作緊密之電氣連接的構造也可採用。 在托盤的基板（Base)2001的角是由有複數個定位孔 600(圖1到圖3表示範例4角落）與從測試母板τ Μ下方伸出的 定位柱(對位柱)作崁合來進行對位。 半導體元件檢查設備Ml具有將各個托盤機構(tray unit) U1裝載的半導體元件D的周圍溫度調整至所訂定之測試環境溫 度的溫度調整手段。 在本實施狀態内的溫度調整手段是由設在例如tray的基 板Base2001的下方，介於導熱板7〇〇、熱板7〇2之間的致冷晶 片模組（Peltier module)、加熱器（Heater)等熱源800所構 成。 另外，並沒有特別限定，導熱板7〇〇是由厚度幾毫米程度的 紹材質'銅材質、不鏽鋼材質、黃銅材質等來製作。 熱源800若由冰水機的冷媒或熱媒，或用LN2也可以，或 者藉由致冷晶片模組(Peltier module)、加熱器（Heater)、 冷媒（包含LN2)及熱媒的冷卻與加熱的組合也可以。 藉由這樣構成的溫度調整手段，像以前一樣怪溫槽内不 用放置托盤機構(tray unit) U1，可簡單地調整測試環境溫 度’提咼測試的便利性及高速化的同時可降低測試成本。 熱源800可藉由安裝致冷晶片模組(peltier m〇dule)可容 易做兩溫測試及低溫測試’或是高低溫的循環測試。 符號900是托盤機構(tray unit) U1下方的支樓受力部。 接下來針對本實施狀態之半導體元件的檢查設備跑的動 201205099 作加以說明。 首先，在半導體元件的檢查設備Ml可更換轉換板3 0 0與 第2連接基板c 2來對應檢查對象之半導體元件D的特性（腳 排列、構造等）。 接著，將置放檢查對象半導體元件D的托盤機構（tray unit) U1安裝於裝載部4〇1 ; 緊接著、作動升降手段402，托盤機構(tray unit) U1 會連同裝載部401—起上升。 若達到所訂定之高度時，真空幫浦500會被啟動而抽取上 述減壓爐體550内的空氣。 藉此，半導體元件D上的電極腳1〇1、和第1連接基板C1、 第2連接基板C2、轉換板300，測試母板TM會緊密地作電氣性 連接。 接下來藉由溫度調整手段，半導體元件D到達所設定的溫 度為止的加熱或冷卻後，測試母板TM、測試機構2〇〇會動作， 對母個半導體元件D進行檢查處理。 另外，在檢查其它構造的半導體元件D時，更換所對應的 連接基板C2和轉換板300後，依上述的順序進行檢查。 這樣藉由此實施的形態的半導體元件檢查設備Μ1可機 動地對應特殊腳排列的半導體元件!)或特殊構造的半導體元 件’可提升測試效率的同時降低測試的成本。 另外，在此實施的形態，是指將半導體元件D的腳向上的 情況’本發明也可適用於半導體元件⑽腳向下情況。 接著，請參考圖8〜圖12是說明第3實施的形態之半導體元 13 201205099 件的檢查設備M3。 在半導體元件的檢查設備M3是具有將檢查對象的半導體 元件D分為複數個並列裝載1或2以上的托盤機構(tray unit) U1，每個托盤機構(tray unit) U1上的半導體元件])腳都向 上裝載狀態下，一次性測試每個半導體元件!)的電氣性特性的 測試板（元件檢查手段的一例：圖8沒顯示），托盤機構（计砂 unit) U1是由鋁等金屬所製作的底板部品（基板)2〇〇1與置放 在此基板2001且水平方向分割成數個，各自分配到複數個半 導體元件D的半導體元件裝載的拖盤(例如樹脂或金屬製的框） 2002a、2002b、2002c所形成。 另外，各個框2002a、2002b、2002c是在另外所設置定位 的設備（參考圖5〜圖12)，還未作定位之前，對基板 (Base)2001的水平方向的移動（例如：箭頭A所標示的移動方向） 維持在所設定的容許範圍内（例如：接觸到圖9的表示之對位用 的孔2003之角落為止的範圍）而成為所謂的浮動構造。 另外，基板2001的材料不限鋁質材料，熱傳導率有 100W/(m · K)以上的材料更好。 此外，在此實施的形態，框(Frame)分割成3個，但這是沒 有限足的，2個以上的話分割多少個都沒問題。 在每個框2002a、2002b、2002c的邊緣鑽有為了要在與連 接機板之間對位各個框2002a、2〇〇2b、2〇〇2c用的對位孔 2003。 另外，在基板2001的四角鑽有為了對位托盤機構（ unit) U1全體的位置用的孔2〇〇5。 201205099 在對位用的孔2003和5對位用的孔2005會崁入在設備内對 位用的柱，來進行各個部品的定位。 可藉此依對位的柱來進行位置補償。 另外、可抑制托盤機構(托盤機構)U1的熱變形措施。 在此實施的形態，如圖5〜圖9所示’一個的托盤機構(tray unit)Ul 的旁邊設有兩個框2〇〇2(2〇〇2a、2002b、2002c)。 在此實施的形態，各個框2002是承載複數個腳向上的半 導體元件D(例如DDR3、BGA包裝(Package))。 各個框2002是的上下周邊部設有3個對位用孔2〇〇3和3個 浮動對位用孔2004。 對位用的孔2003和浮動對位用孔2〇〇4，由圖12(a)、（b) 所示，沿著箭頭A方向，呈長圓形的形狀。 如圖5〜圖7所示，在連接基板1〇22上，設有可插入對位用孔 2003的對位用柱1024。 對位用柱1024的形狀並沒有特別限定，例如圖7所示，要 與對位用孔2003長圓形狀相似的截面形狀(徑向截面形狀）。 如此，在此實施的形態，定位用的對位孔2〇〇3是沿著所定 的方向（在此是指箭頭A方向）成長圓形狀，可插入對位用孔 2003之定位用的對位柱1024是呈與對位用孔2〇〇3相似的載面 形狀。然而對位用柱1024嵌入對位用孔2003就足以進行半導 體元件承載托盤2002和連接基板1〇22的定位。因此，對位用 孔2003也可以用長圓孔以外的孔，例如圓形，橢圓形、矩形 等。可插入對位用孔2003之定位用的對位柱1〇24，若可順暢地 嵌入對位用孔2003且可定位，即使與對位用孔2〇〇3形狀無相 15 201205099 似也可。 如圖9的（a)、（b)所示，在基板2〇〇丨上方置放半導體元件 D之所訂位置，設有為了引導半導體元件D之到定位的交叉兩 邊凸起2006。 故對位用柱1024嵌入對位用孔2003後，藉由對位用柱 1024與對位用孔2003的相接合，各個框2002會往箭頭A方向 移動（參考圖8〜圖12)，同時框2〇〇2所承載之半導體元件D也會 向同方向移動，往設在基板2〇〇1的交又兩邊凸起2〇〇6推壓 後，可讓半導體元件D和框2002間無間隙，而進行高精度之定 位。 在此實施的形態’如圖8和圖9所示，在基板2〇〇1所訂的 位置’设有板彈簧2009，當對位用柱1〇24由對位用孔2〇〇3拔出 時，板彈簧設備2009的彈力會讓各個框2〇〇2往箭頭人之反方向 復歸，半導體元件D也同時復歸至原位置。 在基板2001上有固定孔2008，浮動定位柱2〇〇7由浮動定 位用孔2004插入後，前端部份會壓入固定孔2〇08作固定（參考 圖12的（c))。 然後請參照圖4〜圖12，針對第2實施的形態之半導體元件 檢查設備M2加以說明。 半導體元件檢查設備M2具有托盤機構U1，及對承載於托盤 機構U1上之半導體元件D電極腳2〇1〇(參考圖1〇〜圖12)作電氣 性導通後，測試此半導體元件D之電氣特性之連接於測試機構 (元件檢查手段之一例：無圖示）的測試板1021，及設置於測試 板1021與構成下部真空爐體1〇1〇的框之間的將托盤機構 201205099 (tray unit)Ul上所備之半導體元件承載托盤2002所承載之各 個半導體元件D的電極腳2010與測試板1〇21具有的電極腳做電 氣性連接的配線構造（導電手段）的連接基板1〇22,及與藉由連 接基板1022與連接半導體元件d及測試板1〇21的測試機構作電 氣性連接的連接機構(參考圖5〜圖7)。 測試板1021可配合半導體元件D的種類及半導體元件J)的 電極腳2010之排列作更換。 接下來、針對在第2實施的形態之半導體元件檢查設備M2 的對位動作概要加以說明。 首先，將托盤機構U1設置於下部真空爐體之基板1010，接 著藉由連接基板1022的對位柱1023與托盤的基板2001之對位 用孔2005來進行對位。藉此可定位托盤機構υι。 其次、藉由被分割的框2002上之對位用孔2003與連接基 板1002上的對位柱1〇24,進行對位。 最後進行連接基板1022之腳1026的前端與半導體元件D的 電極腳之間的對位。 藉此可抑制框2002的熱變形，對元件D的電極腳和測試板 更能確實的連接。 用以取代藉由對位用柱1024與對位用孔2003的相接合移 動框2002的機構，也可在框2〇〇2之外部設置將框2〇〇2本體往 箭頭A方向推壓的機構。 請參照圖4〜圖6，針對在第2實施的形態之半導體元件檢 查設備M2加以說明。 如圖4〜圖6所示，上部結構是在測試板1 〇21的下側設置有 17 201205099 被分割後之3個連接基板1022。 測試板1021的四角設有後述要的插入導"柱1〇14的導引 孔 1007。 符號1004是各種電路部品及接線連接器的實裝區域。 測試板1021的一側也可設置端連接器（edge connector) ° 在測試板1021的下方設有連接基板框（上部真空爐體 框)1006 。 一 如圖4〜圖6所示，在連接基板框1006周圍設有〇形環等的密 封部品1012。 下部構成部是在金屬製(例如鋁製）的裝載部（下方真空爐 體1010)設置有前示圖8所示之托盤機構(tray unit)ul。 基板1010的四角設有插入測試板1021側導引孔1〇〇7之導 引柱1014。 在下部之裝載部基板1010的一部份，設有真空閥門的安 裝口 1013。 在裝載部基板1010下方，設有散熱片或熱源所構成的溫 控部1015。 針對托盤機構(tray unit) U1，會在第3實施的形態之半 導體元件檢查設備M3詳細說明，在此省略。 如圖5〜圖9所表示，作為連接機構，具有負壓吸取空氣使半 導體元件D電極腳2010與連接基板1022、及連接基板1〇22與測 試板1021,各自緊密結合的減壓機構1〇〇〇(減壓手段）。 在本實施的形態，減壓機構1000是由測試板1021、連接 201205099 基板1022及㈣部材廳所形成的第—的賴舰腿，及 連接在吸取第一減壓爐體1〇〇2内空氣之真空閥門安裝口 low 的第-真空幫浦（如圖所示），及包圍連接基板體的連接基 板框1006，及设在裝載部1〇1〇的端部介於該裝載部移動時與 連接基板框1006之間的密封部品所形成之第2減壓爐體1〇〇2， 及連接在吸取第2減壓爐體1〇〇2内空氣之真空閥門安裝口 1〇13 的第2真空幫浦（無圖示)所構成。 並沒有特別限制，首先，最初藉由第丨真空幫浦來減壓第i 減壓爐體1001，接著，以第2真空幫浦來減壓的第2減壓爐體 1002，藉此可確實的將半導體元件J)和測試板1〇21進行電氣性 連接。 也可設計成一個真空幫浦來代替第1真空幫浦及第2真空 幫浦，以閥門切換控制，只要可將第丨減壓爐體1〇〇1及第2減 壓爐體1002的空氣抽成真空即可。 例如在托盤機構(tray unit)Ul設置底板，此底板所使 用之材料的熱傳導率只要在l〇〇W/(m . κ)以上即可。 更具體地說明’底板是銅時（熱傳導率385W/(m · κ)、比 重（8. 9g/cm3)) ’是鋁時（熱傳導率2〇〇w/(m · K)、比重 (2.7g/cm3))，或是黃銅時（熱傳導率· κ)、比重 (8. 7g/cm3))都可使用。 藉此，提高托盤機構(tray unit) U1底板的熱傳導率， 半導體元件檢查的效率就會向上提升。 在拖盤的基板2001的複數處設置有如圖8〜圖12所示之板 彈簧2009 ’而可將框2〇〇2往箭頭A方向的反方向推壓，復歸至 19 201205099 原位即可。 在圖9的（a)、（b)，這是-個例子，在欲推壓半導體元件d 側的兩邊設置有凸起，但在基板聰設置能將元件定位之角 孑L(圖示省略）等的其它好的方式也可。 其次，參考圖13、®U ’簡單朗半㈣元件檢查系統 S卜 如圖13所示，半導體元件檢查系統幻是由適用於本發明之 半導體元件的檢查設讎，包括托盤機構(tray unit)ul在内 的測試半導體元件D電氣特性之半導體測試設備M1〇、及將半 導體元件D的翻轉及移轉之半導體元件托盤移轉設備、及 選擇半導體元件D良否之自動選擇機M12所構成。 半導體測試設備M10上具有測試機構20〇。 在半導體測試設備M10上是將從半導體元件托盤移轉設備 Mil所移送來的托盤機構(tray unit) U1以預熱部3〇〇1進行預 熱後，藉由圖1〜圖3等所示之構成的半導體元件檢查設備m， 對托盤機構(tray unit) U1所承載全部的半導體元件[)作電氣 特性測試。 之後，將托盤機構(tray unit) U1移送到除熱部3〇〇2，除 熱後移送到半導體元件托盤移轉設備犯1。 在半導體元件托盤移轉設備Mil，測試前出貨托盤—半導 體元件D托盤移轉—在托盤處理設備3003的過程，會將托盤機 構(tray unit) U1移送至半導體測試設備M10 ,在半導體測試 叹備M10由測試托盤回來之托盤機構(tray unh)讥是由托盤 處理設備3004處理—半導體元件D反轉與移轉—在測試後出貨 201205099 托盤的過程，會送到半導體元件自動選擇機M12,或是托盤處理 設備3004->半導體元件D的托盤移轉—空的測試托盤的流程移 送。 在半導體元件自動選擇機Ml 2是將由測試後出貨托盤運所 送來的半導體元件D ’根據檢查結果，取出不良品良品填補 〜在良品出貨托盤流程，將半導體元件D依測試結果加以選 擇。 關於除去的不良品，在托盤機構(tray unit) U1具有健存 識別資訊等的記憶體、RFID(IC標籤）或有條碼機的情況下， 也可根據這些的訊息分類不良品。 也可構成適用半導體元件的檢查設備Ml之測試平台分為 卜N(N為整數)段堆疊多段構造的半導體元件檢查系統S2。 以上是發明人對這項發明依實施形態作具體說明，但應 戎考慮本明細書所公開之實施形態不局限於在全部的點以範 例所公開的技術。既是，本發明之技術性範圍不只是基於在上 述實施形態之說明所限制的解釋，始終應依據申請專利範圍之 圮載來解釋，包含申請專利範圍之記載技術與均等的技術及 申請專利的範圍内的所有變更。 本發明之半導體元件檢查設備及使用該檢查設備的半導 體元件的檢查系統是適用於需要特性測試之各式各樣半導體 疋件的檢查設備，如SDRAM、Static RAM、Flash memory、 Logic元件、Analog Logic混載元件等各式各樣半導體元件 的測試對象都可適用。 上列洋細s兒明係針對本發明之一可行實施例之具體說 21 201205099 雛太级Λ實施例並非用以限制本發明之專利範圍，凡未脫 月技藝精神所為之等效實施或變更，例如：等變化 之等效性實施例，均應包含於本案之專利範圍中。 【圖式簡單說明】According to the invention described in the application 1, the carrier can be carried to the original position. #4+导体7C ^ Borrow:: The invention described in item 1 can be used to adjust the test efficiency and reduce the measurement of the test. According to the invention of 2, the semiconductor element leg and the connection substrate can be electrically connected more reliably. [Embodiment] 201205099 In the present invention, a "tray mechanism (inspection device for a tray and a semiconductor device)" will be specifically described below with reference to the drawings in order to implement the best mode of the present invention. The same components are denoted by the same reference numerals, and the repeated description will be omitted. The description herein is the best mode for carrying out the invention, but the invention is not limited thereto. The semiconductor element inspection apparatus Μ1 of the first embodiment shown in FIG. 1 to FIG. 3 has a tray mechanism (a tray unit) (an example of a semiconductor element carrier) which is a semiconductor element d as shown in FIGS. 8 and 9 and A test unit used in a test unit 2 ◦ 〇 (an example of a component inspection means) for electrical characteristics of an electrical component of a semiconductor device (10) carried by a tray unit U 1 Plate TM (an example of a test board) and a first contact pin (connecting post ^^ 〇2) (a case of a conductive means) which is placed on the test board D and the corresponding test board. The first connection substrate 〇i and the second connection substrate of the second connection substrate are different from the arrangement of the test element τ Μ of the responsive semiconductor element D electrode leg i Q i and the switch pin arrangement is replaceable The conversion board 3 is provided between the conversion board 3 〇0 and the tray unit, and the contact pin (connection column) is provided in accordance with the arrangement of the semiconductor element D electrode legs 1 〇 1 (electrical means An example of the second connection substrate C2 that is directly connected to the semiconductor element D with the contact pin (connection post) 丄〇3, and the first connection substrate C1, the conversion plate 3A, and the second connection substrate C2. And a connection mechanism 400 (an example of a connection means) for electrically connecting the semiconductor device D to the test mechanism 2 Q connected to the test mother board TM. 201205099 The semiconductor component carrier tray (frame 2002) can be divided into several Carrying the semiconductor element D to inspect the object, the tray unit can be loaded with a plurality of frames 2002. The tray unit U can be designed to have relevant information for storing the results of the inspections performed by the test unit 2000 ( For example, including an identification tray mechanism ( Tray unit) ID data of U1, etc.) Memory, rfID (IC tag), or tag code (Bar code) (not shown) function. According to this, for example, according to the ID (identification number) of the tray, It is possible to improve the convenience by replacing the defective product with a good product, classifying the defective product, etc. In addition, a conductive paste, a connecting conductive pin, or the like is replaced with a conductive paste or an anisotropic conductive sheet to form the conductive means described above. The test unit (test un it) 20 0 may be disposed directly above the test board τ 所示 shown in FIG. 2 or on the front side 2 延长 of the extension of the test board tm, and the inner side 200 may also be . At the same time, the test unit 200 is also provided externally by a connection of a coaxial electric slow line or the like. Further, in the embodiment to be implemented, the semiconductor element D is placed on the tray unit U1 with the electrode electrodes ιοί upward. There is a connection mechanism 4 that electrically connects the semiconductor element D to the test mechanism 20 connected to the test mother board tm by the first connection substrate C1, the conversion board 3, and the second connection substrate C2 ( An example of the connection means). In the embodiment, the connection mechanism 400 has a loading unit 401 for loading a tray unit U1 and an actuator for lifting and lowering the loading unit 4〇i to the second connection substrate c 2 for 201205099 (for example) , the lifting means 402) formed by the cylinders. In the embodiment, the connecting mechanism 400 is raised by the lifting means 4〇2 provided on both sides of the loading unit 4〇1, and is raised by the lifting/lowering means 4〇2 to the position set by the loading unit 4〇1. A vacuum pump 5 〇〇 (an example of a decompression method) in which the electrode pin 1 〇 1 on the 'negative negative pressure causes the semiconductor element!' and the connection substrate C 2 are tightly coupled. Further, the "decompression means is a vacuum pump 5", and is connected to the connection substrate frame 403 which is disposed around the second connection substrate C 2 or to the upper portion of the mounting portion 401, and when the loading portion 401 is raised, the substrate is connected. The air in the gasket sealing member 404 and the connecting substrate frame 403, the first connecting substrate C1, and the pressure reducing furnace body 55 formed by the mounting portion 401 are sucked by the frame 4〇3 or the mounting portion 401. Vacuum. In addition, the vacuum pump 500 has a pressure reducing valve 560 that is pressure-reduced. The surface of the semiconductor element D and the upper surface of the tray mechanism (tray) are pressed by the lifting and lowering means 402, and the upper surface of the tray mechanism (tray) is preloaded, and then the vacuum pump is started. The pressure reducing valve 560 of 500 starts to decompress the pressure reducing furnace body 550, and the semiconductor element D and the tray unit ui are further pressed by the hot plate 7〇1, the second connecting substrate ci, the conversion board 30 0 and the second connection substrate C 2 pressurize the test mother board TM, and all contacts between the semiconductor element D placed on the tray unit U1 and the test mother board τ are connected by a predetermined force. . Thus, the semiconductor element inspecting apparatus M1 of the form thus implemented can be mechanically corresponding to the semiconductor element of the special leg arrangement!) or the specially constructed semiconductor element, which can improve the test efficiency while reducing the cost of the test. The decompression method is not limited to the configuration described above, and the semiconductor element D and the test mother board TM can be closely electrically connected by the second connection base 201205099 board C1, the conversion board 3 〇〇, and the second connection substrate c 2 . The construction of the connection can also be used. The corner of the substrate 2001 is composed of a plurality of positioning holes 600 (Fig. 1 to Fig. 3 shows the corners of the example 4) and a positioning post (alignment column) extending from below the test mother plate τ 崁To carry out the alignment. The semiconductor element inspection apparatus M1 has temperature adjustment means for adjusting the ambient temperature of the semiconductor element D loaded by each tray unit U1 to a predetermined test environment temperature. The temperature adjustment means in the present embodiment is a Peltier module and a heater interposed between the heat conducting plate 7A and the hot plate 7A2 under the substrate Base2001 such as a tray. Heater) is composed of a heat source 800. Further, it is not particularly limited, and the heat transfer plate 7 is made of a material such as copper material, stainless steel material or brass material having a thickness of several millimeters. The heat source 800 may be cooled or heated by a refrigerant or a heat medium of an ice water machine, or by LN2, or by a Peltier module, a heater (Heater), a refrigerant (including LN2), and a heat medium. The combination is also ok. With the temperature adjustment means thus constructed, it is possible to easily adjust the temperature of the test environment without placing a tray unit U1 in the temperature tank as before. The convenience of the test and the high speed can be reduced while reducing the test cost. The heat source 800 can be easily subjected to a two-temperature test and a low-temperature test by installing a peltier module or a high-low temperature cycle test. Symbol 900 is a branch receiving portion below the tray unit U1. Next, the operation 20120099 of the inspection device of the semiconductor element of the present embodiment will be described. First, the inspection device M1 of the semiconductor element can replace the conversion plate 300 and the second connection substrate c 2 to correspond to the characteristics (foot arrangement, structure, and the like) of the semiconductor element D to be inspected. Next, a tray unit U1 on which the semiconductor element D to be inspected is placed is attached to the loading unit 4〇1; next, the lifting unit 402 is actuated, and the tray unit U1 rises together with the loading unit 401. When the predetermined height is reached, the vacuum pump 500 is activated to extract the air in the decompression furnace body 550. Thereby, the electrode leg 1A1 on the semiconductor element D and the first connection substrate C1, the second connection substrate C2, the conversion board 300, and the test mother board TM are closely electrically connected. Next, after the semiconductor element D reaches the set temperature by heating or cooling by the temperature adjustment means, the test mother board TM and the test means 2 are operated, and the mother semiconductor element D is inspected. Further, when the semiconductor element D of another structure is inspected, the corresponding connection substrate C2 and the conversion board 300 are replaced, and the inspection is performed in the above-described order. Thus, the semiconductor element inspecting device 1 of the form thus implemented can be mechanically corresponding to the semiconductor element of the special leg arrangement!) or the specially constructed semiconductor element' can improve the test efficiency while reducing the cost of the test. Further, the embodiment implemented here refers to the case where the semiconductor element D is turned up. The present invention is also applicable to the case where the semiconductor element (10) is down. Next, referring to Fig. 8 to Fig. 12, an inspection apparatus M3 of a semiconductor element 13 201205099 of the third embodiment will be described. The inspection device M3 of the semiconductor element has a tray unit U1 in which a plurality of semiconductor elements D to be inspected are stacked in parallel, or one or more, and a semiconductor element on each tray unit U1] A test board for testing the electrical characteristics of each semiconductor component at a time when the feet are loaded upwards (an example of the component inspection means: not shown in Fig. 8), the tray mechanism (counting unit) U1 is made of a metal such as aluminum The manufactured bottom plate member (substrate) 2〇〇1 and a tray placed on the substrate 2001 and divided into a plurality of horizontally, and each of which is assigned to a plurality of semiconductor elements D is mounted on a tray (for example, a resin or metal frame) 2002a , 2002b, 2002c formed. In addition, each of the frames 2002a, 2002b, and 2002c is a device that is additionally positioned (refer to FIGS. 5 to 12), and moves in the horizontal direction of the substrate 2001 before being positioned (for example, the arrow A indicates The moving direction) is maintained in a set allowable range (for example, a range that comes into contact with the corner of the hole 2003 for alignment shown in FIG. 9) and becomes a so-called floating structure. Further, the material of the substrate 2001 is not limited to an aluminum material, and a material having a thermal conductivity of 100 W/(m·K) or more is more preferable. Further, in the embodiment implemented here, the frame is divided into three, but this is not limited, and it is not problematic if two or more are divided. At the edge of each of the frames 2002a, 2002b, 2002c, a registration hole 2003 for aligning the respective frames 2002a, 2〇〇2b, 2〇〇2c with the connection plate is drilled. Further, holes 2〇〇5 for aligning the positions of the entire unit U1 are drilled at the four corners of the substrate 2001. 201205099 The holes 2005 for the alignment holes 2003 and 5 will be inserted into the column for alignment in the device to position each part. This allows position compensation based on the aligned column. In addition, the thermal deformation measure of the tray mechanism (tray mechanism) U1 can be suppressed. In the embodiment to be implemented, two frames 2〇〇2 (2〇〇2a, 2002b, 2002c) are provided beside the one tray unit U1 shown in Figs. 5 to 9 . In the embodiment implemented herein, each block 2002 is a semiconductor element D (e.g., DDR3, BGA package) that carries a plurality of feet. Each of the upper and lower peripheral portions of the frame 2002 is provided with three alignment holes 2〇〇3 and three floating alignment holes 2004. The alignment hole 2003 and the floating alignment hole 2〇〇4 have an oblong shape in the direction of the arrow A as shown in Figs. 12(a) and (b). As shown in Fig. 5 to Fig. 7, on the connection substrate 1 22, a alignment post 1024 into which the alignment hole 2003 can be inserted is provided. The shape of the alignment pillar 1024 is not particularly limited. For example, as shown in Fig. 7, a cross-sectional shape (radial cross-sectional shape) similar to the shape of the alignment hole 2003 is used. As described above, in the embodiment, the positioning hole 2〇〇3 for positioning is formed in a circular shape along a predetermined direction (herein, the direction of the arrow A), and can be inserted into the alignment position for the positioning hole 2003. The column 1024 is in the shape of a carrier similar to the alignment hole 2〇〇3. However, the alignment of the alignment posts 1024 into the alignment holes 2003 is sufficient for positioning of the semiconductor component carrier tray 2002 and the connection substrate 1〇22. Therefore, the alignment hole 2003 may also use a hole other than the oblong hole, such as a circular shape, an elliptical shape, a rectangular shape or the like. The alignment column 1〇24 for positioning the alignment hole 2003 can be smoothly inserted into the alignment hole 2003 and can be positioned, even if it has no phase with the alignment hole 2〇〇3. As shown in (a) and (b) of Fig. 9, a predetermined position of the semiconductor element D is placed over the substrate 2A, and a cross-over projection 2006 for guiding the positioning of the semiconductor element D is provided. Therefore, after the alignment column 1024 is inserted into the alignment hole 2003, the alignment column 1024 and the alignment hole 2003 are joined, and the respective frames 2002 are moved in the direction of the arrow A (refer to FIG. 8 to FIG. 12). The semiconductor element D carried by the frame 2〇〇2 also moves in the same direction, and is pressed between the two sides of the substrate 2〇〇1 and the protrusions 2〇〇6, so that there is no semiconductor element D and the frame 2002. Clearance, and high-precision positioning. In the embodiment of the present embodiment, as shown in FIGS. 8 and 9, a plate spring 2009 is provided at a position set by the substrate 2〇〇1, and the alignment column 1〇24 is pulled by the alignment hole 2〇〇3. When it comes out, the spring force of the leaf spring device 2009 will cause each frame 2〇〇2 to return to the opposite direction of the arrow man, and the semiconductor component D will also return to the original position at the same time. On the substrate 2001, there is a fixing hole 2008. After the floating positioning post 2〇〇7 is inserted by the floating positioning hole 2004, the front end portion is pressed into the fixing hole 2〇08 for fixing (refer to (c) of Fig. 12). Next, a semiconductor element inspection apparatus M2 according to the second embodiment will be described with reference to Figs. 4 to 12 . The semiconductor component inspection apparatus M2 has a tray mechanism U1, and electrically conducts the semiconductor component D by electrically conducting the semiconductor component D electrode leg 2〇1〇 (refer to FIGS. 1A to 12) carried on the tray mechanism U1. A test board 1021 whose characteristics are connected to a test mechanism (an example of a component inspection means: not shown), and a tray mechanism 201205099 (tray unit) provided between the test board 1021 and a frame constituting the lower vacuum furnace body 1〇1〇 a connection substrate 1〇22 of a wiring structure (conductive means) for electrically connecting the electrode legs 2010 of the respective semiconductor elements D carried by the semiconductor element carrier tray 2002 and the electrode pads of the test board 1〇21, And a connection mechanism electrically connected to the test unit that connects the semiconductor element d and the test board 1 21 by the connection substrate 1022 (refer to FIGS. 5 to 7). The test board 1021 can be replaced with the type of the semiconductor element D and the arrangement of the electrode legs 2010 of the semiconductor element J). Next, an outline of the alignment operation of the semiconductor element inspection apparatus M2 of the second embodiment will be described. First, the tray mechanism U1 is placed on the substrate 1010 of the lower vacuum furnace body, and then aligned by the alignment holes 10 of the substrate 110 of the connection substrate 1022 and the substrate 2001 of the tray. Thereby, the tray mechanism υι can be positioned. Next, alignment is performed by the alignment holes 2003 on the divided frame 2002 and the alignment posts 1〇24 on the connection substrate 1002. Finally, the alignment between the front end of the leg 1026 of the connection substrate 1022 and the electrode leg of the semiconductor element D is performed. Thereby, the thermal deformation of the frame 2002 can be suppressed, and the electrode legs of the element D and the test board can be more reliably connected. Instead of the mechanism for moving the frame 2002 by the alignment of the alignment column 1024 and the alignment hole 2003, the frame 2〇〇2 body may be placed in the direction of the arrow A outside the frame 2〇〇2. mechanism. The semiconductor element inspection apparatus M2 of the second embodiment will be described with reference to Figs. 4 to 6 . As shown in FIG. 4 to FIG. 6, the upper structure is provided with three connection substrates 1022 which are divided into 17 201205099 on the lower side of the test board 1 〇21. The four corners of the test board 1021 are provided with guide holes 1007 for inserting guides "columns 1" 14 which will be described later. Reference numeral 1004 is a mounting area of various circuit components and wiring connectors. An edge connector may also be provided on one side of the test board 1021. ° A connection substrate frame (upper vacuum furnace frame) 1006 is provided below the test board 1021. As shown in Fig. 4 to Fig. 6, a sealing member 1012 such as a ring-shaped ring is provided around the connection substrate frame 1006. The lower structure portion is provided with a tray unit ul as shown in Fig. 8 in a loading portion (lower vacuum furnace body 1010) made of metal (for example, aluminum). The four corners of the substrate 1010 are provided with guide posts 1014 inserted into the side guide holes 1〇〇7 of the test board 1021. A portion of the lower loading portion substrate 1010 is provided with a vacuum port mounting port 1013. Below the loading unit substrate 1010, a temperature control portion 1015 composed of a heat sink or a heat source is provided. The tray unit U1 will be described in detail with respect to the semiconductor element inspection apparatus M3 of the third embodiment, and will not be described here. As shown in FIG. 5 to FIG. 9, as a connection mechanism, a vacuum-reducing mechanism 1a in which a negative-pressure suction air is used to closely bond the semiconductor element D electrode leg 2010 and the connection substrate 1022, and the connection substrate 1〇22 and the test board 1021 is provided. 〇〇 (decompression means). In the embodiment of the present embodiment, the pressure reducing mechanism 1000 is a first-lower leg formed by the test board 1021, the 201205099 substrate 1022, and (4) the material hall, and is connected to the first decompression furnace body 1〇〇2. a first vacuum pump (as shown) of the vacuum valve mounting port low, and a connecting substrate frame 1006 surrounding the connecting substrate body, and an end portion provided at the loading portion 1〇1〇 is moved between the loading portion and The second decompression furnace body 1〇〇2 formed by the sealing member connected between the substrate frames 1006 and the second vacuum valve mounting port 1〇13 connected to the air in the second decompression furnace body 1〇〇2 Vacuum pump (not shown). There is no particular limitation. First, the first decompression furnace body 1001 is decompressed by the first vacuum pump, and then the second decompression furnace body 1002 decompressed by the second vacuum pump is used. The semiconductor element J) and the test board 1〇21 are electrically connected. It can also be designed as a vacuum pump instead of the first vacuum pump and the second vacuum pump, and the valve switching control can be performed as long as the air of the third decompression furnace body 1〇〇1 and the second decompression furnace body 1002 can be used. Draw a vacuum. For example, a tray is provided in a tray unit U1, and the material used for the substrate has a thermal conductivity of at least l/W/(m. κ). More specifically, when the bottom plate is copper (thermal conductivity 385 W/(m · κ), specific gravity (8.9 g/cm 3 )), when it is aluminum (thermal conductivity 2 〇〇 w / (m · K), specific gravity (2.7 g/cm3)), or brass (thermal conductivity · κ), specific gravity (8.7 g / cm3) can be used. Thereby, the thermal conductivity of the U1 substrate of the tray unit is increased, and the efficiency of inspection of the semiconductor element is increased upward. The plate springs 2009' shown in Figs. 8 to 12 are provided at a plurality of places on the substrate 2001 of the tray, and the frame 2〇〇2 can be pressed in the opposite direction of the arrow A direction, and can be returned to the original position of 201205099. In (a) and (b) of FIG. 9, this is an example in which a bump is provided on both sides of the side on which the semiconductor element d is to be pressed, but an angle 孑L at which the element can be positioned is set on the substrate. Other good ways to wait for). Next, referring to FIG. 13, a UU's simple half (four) component inspection system S. As shown in FIG. 13, the semiconductor component inspection system is arbitrarily set by an inspection device suitable for the semiconductor component of the present invention, including a tray unit. The semiconductor test equipment M1〇 for testing the electrical characteristics of the semiconductor element D, the semiconductor element tray transfer device for inverting and transferring the semiconductor element D, and the automatic selection machine M12 for selecting the semiconductor element D are included. The semiconductor test equipment M10 has a test mechanism 20A. In the semiconductor test apparatus M10, the tray unit U1 transferred from the semiconductor element tray transfer apparatus Mil is preheated by the preheating unit 3〇〇1, as shown in FIGS. 1 to 3 and the like. The semiconductor element inspection apparatus m having the configuration described is electrically tested for all the semiconductor elements [2] carried by the tray unit U1. Thereafter, the tray unit U1 is transferred to the heat removing unit 3〇〇2, and after heat removal, it is transferred to the semiconductor element tray transfer apparatus. In the semiconductor component tray transfer apparatus Mil, the pre-test shipping tray-semiconductor component D-tray transfer--in the process of the pallet processing apparatus 3003, the tray unit U1 is transferred to the semiconductor test equipment M10, and the semiconductor test sighs The tray mechanism (mray unh) that the M10 is returned from the test tray is processed by the tray processing device 3004 - the reverse and transfer of the semiconductor component D - the process of shipping the 201205099 tray after the test is sent to the semiconductor component automatic selection machine M12 Or, the tray processing apparatus 3004-> the tray transfer of the semiconductor element D-the flow transfer of the empty test tray. In the semiconductor component automatic selection machine M1 2, the semiconductor component D' sent by the shipment tray after the test is taken out according to the inspection result, and the defective product is taken out and filled in. In the good product shipment tray flow, the semiconductor component D is selected according to the test result. . In the case of a defective device, if the tray unit U1 has a memory such as health identification information, an RFID (IC tag), or a bar code machine, the defective product may be classified based on the messages. The test platform of the inspection apparatus M1 constituting the semiconductor element can also be divided into a semiconductor element inspection system S2 having a segmented multi-segment configuration of N (N is an integer). The above is a detailed description of the invention by the inventors, but it should be considered that the embodiments disclosed in the present specification are not limited to the techniques disclosed by way of example. The technical scope of the present invention is not limited to the explanation based on the description of the above embodiments, and should be interpreted in accordance with the scope of the patent application, including the technical scope of the patent application and the scope of the equivalent technology and patent application. All changes within. The semiconductor component inspection apparatus of the present invention and the inspection system of the semiconductor component using the inspection apparatus are inspection apparatuses suitable for various semiconductor components requiring characteristic testing, such as SDRAM, Static RAM, Flash memory, Logic component, Analog Logic A test object of various semiconductor elements such as a mixed component can be applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION The present invention is not intended to limit the scope of the patents of the present invention, and equivalent implementation or alteration of the technical spirit of the present invention. For example, equivalent embodiments of variations, etc., should be included in the scope of the patent in this case. [Simple description of the map]
Jii】是有關本發明第1之實施形態的半導體元件檢查設備 、 造之側面圖（a)、A-A線透視圖（b)、b-B線 透視圖（c)。 【圖2】是有關本發明第丨之實施形態的半導航件檢查設備 之說明圖。 【圖3】是有關本發明第丨之實施賴的半導體元件檢查設備 之一部分放大圖。 【圖4】是有關本發明第2之實施形態的半導體元件檢查設備 之分解斜視圖。 【圖5】是有關本發明第2之實施形態的半導體元件檢查設備 之一層構造之真空爐體的概略構造圖。 【圖6】是有關本發明第2之實施形態的半導體元件檢查設備 之二層構造之真空爐體的概略構造圖。 【圖7】半導體元件承載把盤對位用柱之構造圖。 【圖8】托盤機構（tray unit)之平面圖（a )及側面圖 (b )。 【圖9】詳細之托盤的元件收放部的平面圖（a )及側面圖 (b )。 【圖10】托盤與連接基板對位後狀態的說明圖。 【圖1 1】托盤承載元件後(對位前）狀態的說明圖。 【圖1. 2】連接基板與托盤全體之對位用的孔的說明圖 22 201205099 (a)、連接基板與托盤上部框之對位用的孔的說明圖 托盤上部框之浮動機構的說明圖（c)。 【圖13】半導體元件檢查系統構造之說明圖。 【圖14】半導體元件檢查系統構造之說明圖。 【主要元件符號說明】 101電極聊 102連接針 103連接針 200測試機構 300轉換板 4〇〇連接機構 401裝載部 402升降手段 403連接基板框 404密封部品 500真空幫浦 550減壓爐體 560減壓閥 6〇〇定位孔 601對位柱 7〇〇導熱板 701熱板 702熱板 _熱源 23 201205099 900承受部 1000減壓機構 1001第一減壓爐體 1002第二減壓爐體 1004電路部品及同軸連接器實裝區域 1005端連接器 1006連接基板框 1007導引孔 1010基板(下部真空爐體） 1012密封部品 1013真空閥安裝口 1014導引柱 1015溫控部 1016真空閥安裝口 1021測試母板(Tester Mother基板） 1022連接基板 1023對位柱（連接基板和托盤機構之間） 1024對位用柱(連接基板和半導體承載托盤之間） 1025密封部品 1026 腳 2001 基板(Base) 2002框(被分割半導體承載托盤） 2002a、2002b、2002c 拖盤 2003對位用孔（連接基板和半導體承載托盤之間） 2004浮動對位用孔 2005對位用孔（連接基板和托盤機構之間） 24 201205099 2006突起 2007浮動對位用柱 2008固定孔 2009板彈簧 2010半導體元件的電極腳 3001預熱部 3002除熱部 3003托盤處理設備 3004托盤處理設備 C1 第1的連接基板 C2 第2的連接基板 D 半導體元件Jii is a semiconductor element inspection apparatus according to a first embodiment of the present invention, a side view (a), an A-A line perspective view (b), and a b-B line perspective view (c). Fig. 2 is an explanatory view of a half-navigation member inspection apparatus according to an embodiment of the present invention. Fig. 3 is a partially enlarged view of a semiconductor element inspecting apparatus according to the third embodiment of the present invention. Fig. 4 is an exploded perspective view showing a semiconductor element inspecting apparatus according to a second embodiment of the present invention. Fig. 5 is a schematic structural view showing a vacuum furnace body having a layer structure of a semiconductor element inspecting apparatus according to a second embodiment of the present invention. Fig. 6 is a schematic structural view showing a vacuum furnace body having a two-layer structure of a semiconductor element inspecting apparatus according to a second embodiment of the present invention. Fig. 7 is a structural diagram of a column for aligning a semiconductor element with a semiconductor element. Fig. 8 is a plan view (a) and a side view (b) of a tray unit. Fig. 9 is a plan view (a) and a side view (b) of the component accommodating portion of the tray. Fig. 10 is an explanatory view showing a state after the tray and the connection substrate are aligned. [Fig. 1 1] An explanatory diagram of the state after the tray is loaded with the component (before the registration). [Fig. 1. 2] Explanation of the hole for aligning the entire substrate and the tray. Fig. 22 201205099 (a) Explanation of the hole for alignment between the connection board and the upper frame of the tray (c). Fig. 13 is an explanatory diagram showing the structure of a semiconductor element inspection system. Fig. 14 is an explanatory diagram showing the structure of a semiconductor element inspection system. [Main component symbol description] 101 electrode chat 102 connection pin 103 connection pin 200 test mechanism 300 conversion plate 4 〇〇 connection mechanism 401 loading portion 402 lifting means 403 connection substrate frame 404 sealing parts 500 vacuum pump 550 decompression furnace body 560 minus Pressure valve 6 〇〇 positioning hole 601 aligning column 7 〇〇 heat conducting plate 701 hot plate 702 hot plate _ heat source 23 201205099 900 receiving part 1000 pressure reducing mechanism 1001 first decompression furnace body 1002 second decompression furnace body 1004 circuit parts And coaxial connector mounting area 1005 end connector 1006 connection substrate frame 1007 guide hole 1010 substrate (lower vacuum furnace body) 1012 sealing part 1013 vacuum valve mounting port 1014 guide column 1015 temperature control part 1016 vacuum valve mounting port 1021 test Motherboard (Tester Mother substrate) 1022 connection substrate 1023 alignment column (between the connection substrate and the tray mechanism) 1024 alignment column (between the connection substrate and the semiconductor carrier tray) 1025 sealing part 1026 foot 2001 substrate (Base) 2002 frame (Segmented semiconductor carrier tray) 2002a, 2002b, 2002c Tray 2003 alignment hole (between the connection substrate and the semiconductor carrier tray) 2004 Floating alignment hole 2005 alignment Hole (between the connection substrate and the tray mechanism) 24 201205099 2006 Protrusion 2007 Floating Alignment Post 2008 Fixing Hole 2009 Leaf Spring 2010 Electrode Element 3001 Preheating Section 3002 Heat Removal Section 3003 Pallet Processing Equipment 3004 Pallet Processing Equipment C1 First connection substrate C2 second connection substrate D semiconductor element
Ml〜M3半導體元件的檢查設備 M10半導體元件測試設備Ml~M3 semiconductor component inspection equipment M10 semiconductor component test equipment
Mil半導體元件托盤移轉設備 M12半導體元件自動選擇機Mil semiconductor component tray transfer equipment M12 semiconductor component automatic selection machine
Sl，S2檢查系統 U1 托盤機構（tray unit) 25Sl, S2 inspection system U1 tray unit (tray unit) 25