201203377 六、發明說明： 【發明所屬之技術領域】 本毛月\關於一種製作金氧半導體電晶體的方法，尤才曰 種於疋義夕晶*夕開口（polysilicon slot)之前形成蠢晶層的 方法。 【先前技術】 在半導體產業中，由於多晶石夕材料具有抗熱性質，因此 在製作典型金屬氧化物半導體(MOS)電晶體時通常會使用多 晶石夕材料來製作電晶體的閘極電極，使其源極與汲極區域得 以在高溫下一起進行退火。其次，由於多晶矽能夠阻擋以離 子佈植所摻雜之原子進入通道區域，因此在閘極圖案化之後 能容易地再進行高溫形成自行對準的源極與汲極區域。 隨著半導體元件的尺寸越來越小’電晶體的製程步驟也 有許多的改進，以製造出體積小而高品質的電晶體。習知製 作金氧半導體電晶體的閘極時通常是先於一半導體基底表 面全面性覆蓋一多晶矽層以及〆設於多晶矽層上的硬遮 罩，然後對多晶矽層及硬遮罩進行兩次微影暨触刻製程 (photo-etching process)，藉此將多aa石夕層及硬遮罩圖案化以 2〇12〇3377 。其中第一 一次的微f彡賊㈣程較佳將硬201203377 VI. Description of the invention: [Technical field of invention] This method relates to a method for fabricating a MOS transistor, which is specially formed in the formation of a stupid layer before the polysilicon slot method. [Prior Art] In the semiconductor industry, since a polycrystalline material has thermal resistance, a polycrystalline stone material is usually used to fabricate a gate electrode of a transistor in the production of a typical metal oxide semiconductor (MOS) transistor. The source and the drain region are allowed to anneal together at a high temperature. Secondly, since the polysilicon can block the atoms doped by the ion implantation into the channel region, the high temperature can be easily formed to form the self-aligned source and drain regions after the gate patterning. As the size of semiconductor components is getting smaller, the process steps of transistors have also been improved to produce small-sized and high-quality transistors. Conventionally, the gate of a MOS transistor is generally covered with a polysilicon layer and a hard mask disposed on the polysilicon layer before the surface of a semiconductor substrate, and then the polysilicon layer and the hard mask are twice. The photo-etching process is used to pattern the multi-aa stone layer and the hard mask to 2〇12〇3377. The first time the micro-f thief (four) is better will be hard
形成電晶體的閘極 遮罩及多晶矽層圖 案，而楚—， 夕日然而’由於習知製程是在成長蟲晶層之前就形成上述之 多晶矽開口，因此形成多晶矽開口的蝕刻率通常會影響到後 續的製程。舉例來說，若第二次微影暨蝕刻製程中的蝕刻率 較低，多晶矽閘極中的開口通常無法被完全蝕刻開而產生多 晶矽殘留（polysilicon residue)，而導致後續成長的磊晶層產 生橋接現象（line end bridge)。反之，若蝕刻製程的蝕刻率過 高，則多晶矽層上的硬遮罩會在蝕刻過程中被過度消耗並造 φ 成後續閘極側壁之側壁子的耗損。隨著侧壁子的耗損，部分 閘極側壁會暴露出來，因此後續進行磊晶成長製程時在閘極 側壁便會長出不需要的磊晶結構。 【發明内容】 因此本發明是揭露一種製作金氧半導體電晶體的方 法，以解決上述習知以兩道微影暨蝕刻製程製作多晶矽開口 5 201203377 的問題。 本發明較佳實施例是揭露一種製作金氧半導體電晶體 的方法。首先提供一半導體基底，然後形成一矽層於該半導 體基底表面。接著對财層進行―第—微影暨㈣製程，以 形成-閘極圖案’隨後形成—蟲晶層於閘極圖案兩側之該半 導體基底中，再對閘極圖案進行一第二微影暨蝕: 於開極圖案中形成至少-開口（slot)並藉此開口將開極圖案 實體分離以形成二閘極。 •本發明另—實施例是揭露—種金氧半導體電晶體，其包 含：一半導體基底；-閘極設於半導體基底上，該閘極且有 四側壁’且該四側壁#之兩對向側壁具有側壁子而另兩對向 側』無側壁子，以及—遙晶層設於側壁子兩側之半導體基底 内。 土 _ 【實施方式】 請參照第】圖至第6圖，第⑽至以圖為本發明較佳 實施例製作一金氧半導體電晶體之示意圖。如第ί圖所示， 首先提供—半導體基底12，例如—梦基底或—絕緣層上覆石夕 SO底等。域在半導體基底η上 疋義至少—主動區域14，並形成複數個隔離主動區域14的 201203377 淺溝隔離（shallow trench isolation, STI)16 結構。 然後形成一由氧化物、氮化物等之介電材料所構成的閘 極絕緣層⑽未*)在半導縣底12表面，接著在閘極絕緣層 上依序形成一厚度約i 000埃（angstr0m)的多晶矽層以及一石θ 遮罩在多晶矽層上。在本實施例中，硬遮罩可由二 (Sl〇2)、氮化石夕或氣氧化石夕（si〇N)等材料所構成，而夕匕曰夕 層可由不具有任何摻質(und()ped)的多晶石夕材料 曰曰石夕 摻質的多晶矽材料所構成，此皆屬本發明所涵蓋的範 接著對硬遮罩及多晶石夕層進行一微影暨敍刻 (photo-etching)製程，例如先形成一圖案化光阻 在硬遮罩上’並彻圖案化光阻層當作遮罩進行 不） 製程’以單:欠_或逐捕刻㈣，去除部分叫=轉移 晶矽層及閘極絕緣層，並剝除此圖案化光阻層於、、多 域14形成一由圖案化之閘極絕緣層18、圖案化：動區 2 〇及圖案化之硬遮罩2 2所構成的閘極圖案2 4。夕曰曰矽層 請同時參照第2圖，第2圖為第1圖進行第一 儀刻後之閘極上視®。如圖巾所示，經過上述第—人微衫暨 触刻製程後本實施例較佳於半導體基|12上一:人微影暨 條狀的閘極圖案24，且每條閘極圖案24均由=數個長 緣層18、圖案化多晶石夕層2〇及圖案化硬遮罩=絕 7 201203377 然後如第3 m „ , 斤不’進行第一階段的側壁子製程，例如先依 ^ 氣化矽層（圖未示）及氮化矽層（圖未示）於半導體基 " 然後以回蝕刻（etch back)的方式去除部分該氧化矽 層氣化石夕層’以於閘極圖案24側壁形成一由氧化矽層26 及氮4夕層28所構成的第—側壁子3〇。 ；壤行一選擇性蟲晶成長（selectiVe epitaxiai growth， SEG)製程， ， 、 以於半導體基底12中形成應變矽。例如可先形 、u。案化光阻層（圖未示）於半導體基底12上，並進行一蝕 刻於間極圖案24兩側的半導體基底12中形成二凹槽 3 接f進行一表面清洗製程，用以完全移除凹槽34表面 的原生氧化物與其他不純物質。隨後再利用選擇性磊晶成長 製程實質卜 填滿這兩個凹槽34而形成磊晶層36。其中本實 施例於第〜相 调壁子3〇及磊晶層36形成前又可先進行一淺摻 雜製程，將\ ? N型或p型摻質植入閘極圖案24兩側的半導體 基底12中^ 乂形成一輕摻雜汲極32，且在本實施例中，磊晶 曰 的柯料可依據電晶體的特性或製程需求任意調整，而 不侷限於此。 例如’若製作電晶體為PMOS電晶體，較佳於凹槽34 中形成由鍺化矽所構成的磊晶層36，且此磊晶層36可對 PM0S電晶體的通道區域施加一磨縮應力（compressive 201203377 strain)，進而提升PMOS電晶體的電洞遷移率。反之，若製 作的電晶體為NMOS電晶體，則較佳於凹槽34中成長由由 碳化矽（SiC)所構成的磊晶層36，並以此磊晶層對NMOS電 晶體的通道區域施加一拉伸應力（tensiie strain)，以提升 NMOS電晶體的電子遷移率。 接著請同時參照第4圖及第5圖，其中第4圖為延續第 3圖之剖面示意圖帛5圖則為本實施例之多晶梦閘極上示 圖士圖中所示，先去除多晶石夕層20上的硬遮罩22，然後 形成-側壁子材料層’例如依序沈積一氧化石夕層（圖未示）及 IU匕石夕層（圖未示）於半導體基底12上。接㈣行—微影祕 刻製程：例如先形成一圖案化光阻層(圖未示)於多晶矽層20 上並、圖案化光阻層為遮罩進行一餘刻製程，去除僅設於 淺溝隔離16上的多晶⑪層扣’例如部分多晶石夕層20的頭尾 兩私及中間部分’以於長條狀的閘極圖案Μ中形成至少一 多晶棒(poly sl〇t)38 ’並藉此開口 3 8將間極圖案 分離成兩個_46。隨後去除圖案化紐層並清洗半 底12表面所剩餘的殘餘物，然 : 行一回帽程，以於側壁;(== 層4〇及氮化㈣42所構成的第二_子44氧化石夕 在本實％例中，第5圖中僅以―㈣2 同時省略其他摻雜區，如 ^ ，]^ 幸二夂雜汲極與磊晶層等結構。如圖 9 201203377 中所示，多晶矽開口 38較佳將長條狀的閘極圖案24分隔為 兩部分’且由於本實施例是於形成多晶矽開口 38時同時去 除部分氧化矽層40及氮化矽層42並分隔出兩個多晶矽閘極 46 ’因此分隔後之各多晶矽閘極46的至少兩對向側壁並無 設有任何側壁子。換句話說，多晶矽閘極46的四個側壁中 有兩個對向側壁設有由氧化矽層40及氮化矽層42所構成的 第二側壁子44，而另外兩個對向側壁則無任何側壁子。 需注意的是’本實施例於硬遮罩去除之後才形成多晶矽 開口 38的主要目的是為了後續重工(rew〇rk)製程的考量。亦 即，在形成多晶矽開口 38時的黃光製程通常有機會進行重 工，而於重工製程前，半導體基底12上的主動區域14由於 硬遮罩22已於先前製程中移除，因此裸露出來的矽基底表 面並無任何保護。然而，由於重工時所通入用來去除圖案化 光阻材料的氧氣通常會於砂基底表面形成原生氧化物 (native oxide)或產生凹洞（recess)，因此本實施例較佳先去除 多晶石夕層2G上的硬遮罩22，然後再覆蓋先前所述的氧化石夕 層及氮化㈣於半導體基底12上，—方面可作為後續形成 第-側壁子的材料層’另—方面又可作為蚀刻多晶石夕開口的 遮罩並保護主動區域。 、然而’本實施例雖以硬遮罩去除之後才形成多晶石夕開口 38為例’但不侷限於這個順序’本發明又可在蠢晶層托形 201203377 成後的任何一個時間點來形成多晶矽開口 38,此製程選擇也 屬本發明所涵蓋的範圍。 另外又需注意的是，上述實施例中形成第二側壁子的製 程較佳在回钱刻製程前依序沈積一氧化石夕層與一 it化石夕 層，然後再以一次回蝕刻同時去除部分氧化矽層及氮化矽層 以形成第二側壁子。但不侷限於這個作法，例如本發明又可 在形成多晶矽開口前先僅沈積一層氧化矽層，然後等多晶矽 ® 開口形成後再沈積一氮化矽層，而形成不同的金氧半導體電 晶體結構。 舉例來說，本發明可於去除硬遮罩之後先沈積一氧化矽 層40於半導體基底12上，然後依據上述製程形成多晶矽開 口 38，接著再沈積一氮化矽層42於半導體基底12上，並以 回蝕刻同時去除部分氧化矽層40及氮化矽層42以形成第二 _ 側壁子44。如第6圖所示，由於部分的氧化石夕層40較佳在 形成多晶矽開口 38時被去除，因此第二側壁子44的氧化矽 層40僅會設於閘極46的兩對側壁上，而第二側壁子44的 氮化矽層42則由於是在多晶矽開口 38形成後才沈積，因此 較佳設於閘極46的四個側壁上。 此外，依據本發明另一實施例，本發明可於去除硬遮罩 之後先沈積一氧化矽層40於半導體基底12上，然後依據上 201203377 述製程形成多晶⑪心38。接著先以 分氧化㈣40形成第二_子 去除部 於半導俨其庙19 !· …、後再沈積一氮化矽層42 屏42以道回㈣齡去㈣分氤化石夕 曰 心成一第二側壁子。雖然此製程在順序上盘上述實 ^例略微不同，但可同樣製作出如第6圖所揭露之電晶體結 綜上所述，相較於習知是在形成遙晶層之前就先製作出 多晶石夕開口，本發明較佳先以第一次微影暨㈣ % 長條狀的多晶㈣極圖案，然後於多晶㈣極圖案兩側= 遙s曰曰層’之後再以第二次微影暨_製程定義出多晶石夕開口 並將多晶矽閘極實體分離以形成兩個閘極。由於定義多晶矽 開口的步驟是在蠢晶層形成後才實施，本發明可避免前述定 義多晶矽開口時因蝕刻率過高而產生磊晶層橋接現象或蝕疋 刻率過低而造成磊晶層長在閘極側壁的問題。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第6圖為本發明較佳實施例製作一金氧半導體電曰 體之示意圖。 12 201203377 【主要元件符號說明】 12 半導體基底 14 主動區域 16 淺溝隔離 18 閘極絕緣層 20 多晶矽層 22 硬遮罩 24 閘極圖案 26 氧化矽層 28 氮化石夕層 30 第一側壁子 32 輕摻雜汲極 34 凹槽 36 蠢晶層 38 多晶碎開口 40 氧化矽層 42 氮化矽層 44 第二側壁子 46 閘極 13Forming the gate mask of the transistor and the polysilicon layer pattern, and Chu-, however, because the conventional process is to form the above polysilicon opening before the growth of the insect layer, the etching rate of the polysilicon opening is usually affected. Process. For example, if the etch rate in the second lithography and etching process is low, the openings in the polysilicon gate are generally not completely etched to produce polysilicon residues, resulting in subsequent growth of the epitaxial layer. Line end bridge. On the other hand, if the etching rate of the etching process is too high, the hard mask on the polysilicon layer is excessively consumed during the etching process and is φ as the sidewall of the subsequent gate sidewall. As the sidewalls are depleted, some of the gate sidewalls are exposed, so that an unwanted epitaxial structure is formed on the sidewalls of the gate during the subsequent epitaxial growth process. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a method of fabricating a MOS transistor to solve the above-described problem of fabricating a polysilicon opening 5 201203377 by two lithography and etching processes. DETAILED DESCRIPTION OF THE INVENTION A preferred embodiment of the invention discloses a method of fabricating a MOS transistor. A semiconductor substrate is first provided and then a layer of germanium is formed on the surface of the semiconductor substrate. Then, the first layer is performed on the financial layer to form a gate pattern, and then a silicon gate layer is formed in the semiconductor substrate on both sides of the gate pattern, and then a second lithography is performed on the gate pattern.暨 Eclipse: At least a slot is formed in the open pattern and the opening is physically separated by the opening to form a second gate. Another embodiment of the present invention discloses a MOS transistor comprising: a semiconductor substrate; a gate disposed on the semiconductor substrate, the gate having four sidewalls and two opposite sides of the four sidewalls The side walls have side walls and the other two opposite sides have no side walls, and the remote crystal layer is disposed in the semiconductor substrate on both sides of the side walls. Soil _ [Embodiment] Referring to Fig. 6 to Fig. 6, (10) to Fig. 1 is a schematic view showing the fabrication of a MOS transistor according to a preferred embodiment of the present invention. As shown in Fig. 1, first, a semiconductor substrate 12 is provided, for example, a dream substrate or an insulating layer overlying a stone base. The domain is at least the active region 14 on the semiconductor substrate η, and forms a plurality of 201203377 shallow trench isolation (STI) 16 structures that isolate the active region 14. Then, a gate insulating layer (10) composed of a dielectric material such as an oxide or a nitride is formed on the surface of the bottom 12 of the semiconductor, and then a thickness of about i Å is sequentially formed on the gate insulating layer. The polycrystalline layer of angstr0m) and a stone θ are masked on the polysilicon layer. In this embodiment, the hard mask may be composed of a material such as two (Sl〇2), a nitrided stone or a gas oxidized stone (si〇N), and the outer layer may have no dopant (und( The ped) polycrystalline stone material is composed of a polycrystalline germanium material, which is covered by the present invention, and then subjected to a lithography and lithography of the hard mask and the polycrystalline stone layer (photo) -etching) process, for example, first forming a patterned photoresist on a hard mask and 'patterning the photoresist layer as a mask to perform no process'. Single: under- or retracing (four), remove part = Transferring the germanium layer and the gate insulating layer, and stripping the patterned photoresist layer, the multi-domain 14 forms a patterned gate insulating layer 18, patterning: the moving region 2 〇 and the patterned hard mask The gate pattern 24 of the cover 2 2 is formed. Please refer to Figure 2 at the same time. Figure 2 is the first view of the gate after the first lithography. As shown in the figure, after the above-mentioned first human micro-shirt and etch process, the present embodiment is preferably on the semiconductor substrate|12: a human lithography and strip gate pattern 24, and each gate pattern 24 All by = several long-edge layers 18, patterned polycrystalline slabs 2 〇 and patterned hard masks = 绝 7 201203377 and then as the 3 m „ , 斤 不 'to carry out the first stage of the side wall process, for example first According to the gasification layer (not shown) and the tantalum nitride layer (not shown) on the semiconductor substrate " and then etch back to remove part of the yttrium oxide layer gasification layer to the gate The sidewall of the pole pattern 24 forms a first sidewall 3〇 composed of a yttrium oxide layer 26 and a nitrogen layer 28. The selectiveiVe epitaxiai growth (SEG) process, for semiconductors A strain enthalpy is formed in the substrate 12. For example, a photoresist layer (not shown) may be formed on the semiconductor substrate 12, and a recess is formed in the semiconductor substrate 12 etched on both sides of the interpolar pattern 24. 3 followed by a surface cleaning process to completely remove the native oxide from the surface of the recess 34 He is not pure material. Then the selective epitaxial growth process is used to fill the two grooves 34 to form the epitaxial layer 36. The present embodiment is formed before the first phase-adjusting wall 3〇 and the epitaxial layer 36 are formed. Alternatively, a shallow doping process may be performed to implant a ?N-type or p-type dopant into the semiconductor substrate 12 on both sides of the gate pattern 24 to form a lightly doped gate 32, and in this embodiment The epitaxial enamel material can be arbitrarily adjusted according to the characteristics of the transistor or the process requirements, and is not limited thereto. For example, if the transistor is made of a PMOS transistor, it is preferable that the groove 34 is formed of bismuth telluride. The epitaxial layer 36, and the epitaxial layer 36 can apply a compressive stress to the channel region of the PMOS transistor (compressive 201203377 strain), thereby increasing the hole mobility of the PMOS transistor. Conversely, if the transistor is fabricated Preferably, the NMOS transistor is grown in the recess 34 by an epitaxial layer 36 composed of tantalum carbide (SiC), and the epitaxial layer applies a tensile stress to the channel region of the NMOS transistor. To increase the electron mobility of the NMOS transistor. Referring to FIG. 4 and FIG. 5 , wherein FIG. 4 is a cross-sectional view of the continuation of FIG. 3 , and FIG. 5 is a schematic view of the polycrystalline dream gate shown in the present embodiment, and the polycrystalline stone layer is removed first. The hard mask 22 on the 20, and then the - sidewall material layer is formed, for example, a layer of a oxidized stone layer (not shown) and an IU layer (not shown) are sequentially deposited on the semiconductor substrate 12. - lithography process: for example, first forming a patterned photoresist layer (not shown) on the polysilicon layer 20, and patterning the photoresist layer for the mask to perform a process of engraving, removing only the shallow trench isolation 16 The upper polycrystalline 11 layer buckle 'for example, the first and the second private and intermediate portions of the partial polycrystalline layer 20 are formed to form at least one polycrystalline rod (poly sl〇t) 38 ' in the elongated gate pattern Μ. The opening pattern is thereby separated into two _46s. Subsequently, the patterned layer is removed and the remaining residue on the surface of the half bottom 12 is cleaned, but: a hat process is performed for the sidewall; (== layer 4〇 and nitride (4) 42 constitute the second_sub 44 oxidized stone In the case of the real case, in Fig. 5, only the other doped regions are omitted by "(4)2, such as ^,]^, and the structure of the doped dipole and the epitaxial layer. As shown in Fig. 9 201203377, the polysilicon opening is shown in Fig. 9 201203377. 38 preferably divides the elongated gate pattern 24 into two portions' and since the present embodiment is formed, the partial germanium oxide layer 40 and the tantalum nitride layer 42 are simultaneously removed and the two polysilicon gates are separated. 46' Therefore, at least two opposite sidewalls of each of the polysilicon gates 46 after separation are not provided with any sidewalls. In other words, two of the four sidewalls of the polysilicon gate 46 are provided with a layer of tantalum oxide. 40 and the second sidewall spacer 44 formed by the tantalum nitride layer 42, and the other two opposite sidewalls do not have any sidewalls. It should be noted that the main structure of the polysilicon opening 38 is formed after the hard mask is removed in this embodiment. The purpose is to consider the process of the rework (rew〇rk) process. The yellow light process when forming the polysilicon opening 38 typically has the opportunity to be reworked, and prior to the rework process, the active region 14 on the semiconductor substrate 12 has been removed from the prior process because the hard mask 22 has been removed, thereby exposing the surface of the germanium substrate and There is no protection. However, since the oxygen used to remove the patterned photoresist material during rework usually forms a native oxide or a recess on the surface of the sand substrate, this embodiment is preferred. First, the hard mask 22 on the polycrystalline layer 2G is removed, and then the previously described oxidized stone layer and nitrided (four) are overlaid on the semiconductor substrate 12, which can be used as a material layer for subsequently forming the first sidewall. On the other hand, it can be used as a mask for etching polysilicon opening and protecting the active region. However, the present embodiment is formed by using a hard mask to remove the polycrystalline spine opening 38 as an example, but is not limited to this order. The present invention can form the polysilicon opening 38 at any point after the formation of the doped layer 201203377. This process selection is also within the scope of the present invention. In the above embodiment, the process of forming the second sidewalls is preferably performed by sequentially depositing a layer of a oxidized stone layer and an layer of a fossil layer before the etching process, and then removing the partial yttrium oxide layer and nitrogen by etching once. The ruthenium layer is formed to form the second sidewall. However, the method is not limited to this. For example, the present invention can deposit only a layer of ruthenium oxide before forming the opening of the polysilicon, and then deposit a layer of tantalum nitride after the formation of the opening of the polysilicon ruthenium. For example, the present invention can deposit a hafnium oxide layer 40 on the semiconductor substrate 12 after removing the hard mask, and then form a polysilicon opening 38 according to the above process, followed by deposition of a polycrystalline germanium opening 38. The tantalum nitride layer 42 is on the semiconductor substrate 12, and a portion of the tantalum oxide layer 40 and the tantalum nitride layer 42 are simultaneously removed by etch back to form a second sidewall spacer 44. As shown in FIG. 6, since a portion of the oxidized layer 40 is preferably removed when the polysilicon opening 38 is formed, the yttrium oxide layer 40 of the second sidewall 44 is disposed only on the opposite sidewalls of the gate 46. The tantalum nitride layer 42 of the second sidewall portion 44 is deposited on the four sidewalls of the gate 46 since it is deposited after the polysilicon opening 38 is formed. In addition, in accordance with another embodiment of the present invention, the present invention can deposit a ruthenium oxide layer 40 on the semiconductor substrate 12 after removing the hard mask, and then form the polycrystalline 11 core 38 according to the process described in 201203377. Then, the second _ sub-removal part is formed by partial oxidation (4) 40 in the semi-conducting 俨 俨 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 Two side walls. Although the process is slightly different in the above-described embodiment of the above-described process, the same can be made as in the transistor splicing disclosed in FIG. 6, which is produced before the formation of the crystal layer. In the present invention, the first lithography and the (four) % strip-shaped polycrystalline (tetra) pattern are preferred, and then the polycrystalline (tetra) pattern is printed on both sides = the remote s layer The secondary lithography process defines a polycrystalline spine opening and separates the polysilicon gate entities to form two gates. Since the step of defining the opening of the polysilicon is performed after the formation of the doped layer, the present invention can avoid the occurrence of epitaxial layer bridging due to excessive etching rate due to excessive etching rate or excessive etching rate when the polycrystalline germanium opening is defined. The problem with the sidewalls of the gate. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 through Fig. 6 are schematic views showing the fabrication of a MOS semiconductor body in accordance with a preferred embodiment of the present invention. 12 201203377 [Description of main components] 12 Semiconductor substrate 14 Active region 16 Shallow trench isolation 18 Gate insulating layer 20 Polysilicon layer 22 Hard mask 24 Gate pattern 26 Cerium oxide layer 28 Nitride layer 30 First side wall 32 Light Doped drain 34 recess 36 doped layer 38 polycrystalline opening 40 yttrium oxide layer 42 tantalum nitride layer 44 second sidewall sub 46 gate 13