1303459 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種金氧半導體電晶體和互補式金氧半 導體電晶體的製作方種先製相極/及極延^申 區，再製作磊晶層的金氧半導體電晶體和互補式金氧半導 體電晶體的製作方法。 “ 【先前技術】. 隨著半導體元件尺寸越來越小，電晶體製程 許多的改進，以期製造出小體積、高品質的電晶體\ 先前技術的電晶體製程是在矽基底上形成閉極結構之 後’再利用可降低熱預算(thermal budget)的離子植入法， 以於閘極結構相對兩側的矽基底中形成源極延伸（s⑽we extension)區與没極延伸（drain extension)區，或者稱為_摻 雜(lightly doped drain，LDD)源極/汲極。接著，於間極奸構 侧邊形成側壁子（spacer)，並利用此閘極結構及側壁子做為 遮罩，進行離子植入步驟，以於矽基底中形成源極/汲極· 區。而為了要將電晶體的閘極、源極與汲極適當電性連接 於電路中’因此需要形成接觸插塞(C〇ntactplUg)來進行導 通。且為了改善金屬材質之接觸插塞與半導體材質之閉極 結構、源極/汲極區之間的歐米接觸（〇hmic c〇ntact)，通常 會再利用自動對準金屬石夕化物（self-alignecj siiicide，salieide) 1303459 製程，在閘極結構、源極/汲極區的表面形成一金屬矽化物。 然而，在進行自動對準金屬矽化物製程中，金屬層中 的金屬會擴散進矽基底甲並消耗掉源極/汲極區中的矽，不 但原本源極/汲極區中的晶格結構會遭到破壞，甚至導致汲 極/源極和基底之間的1>]^接合與金屬矽化物過近，而產生 漏電。尤其在超淺介面（ultrashall〇wjuncti〇n，USL)的設計 中，更可能會造成元件失效的狀況。 目前，較佳的解決方法是利用利用選擇性蟲晶成長 (selective epitaxial growth ’ SEG)製程，架高電晶體的没極/ 源極，以贱金屬魏物與⑪基底直接接觸源 極/汲極延伸區。但是，選擇性磊晶製程的溫度，言塭二 690度至79〇度，所以會破壞已形成的源極/沒極^ 因此如何研發出一種能製作源極/汲極延伸區又同' 作磊晶層的方法，係為重要該領域重要課題。、把製 【發明内容】 晶體的方法 以 本發明係提供一種製作金氧半導體電 解決上述問題。 的方法，包 又於閘極結 本發明係提供一種製作金氧半導體 含提供一基底，且於基底上形成一閘極結=， 1303459 構周圍形成一偏側壁子，於偏側壁子周圍形成一犧牲側壁 子°再者’於閘極結構之兩侧形成數個磊晶層，且磊晶層 位於犧牲側壁子之外側，之後去除犧牲側壁子，並形成數 個1;及極/源極延伸區於偏側壁子外側的基底中以及磊晶層 中。 本發明係提供一種製作互補式金氧半導體電晶體的方 # 法，包含提供一基底，並形成一第一閘極結構、一第二閘 極結構於基底上，且於第一、第二閘極結構周圍形成第一、 第二偏側壁子，再於第二偏側壁子周圍形成一犧牲側壁 子。接著，於第二閘極結構之兩側形成數個磊晶層，這些 蟲晶層位於該犧牲側壁子之外侧，然後，去除犧牲側壁子， 於第一閘極結構之兩側之基底中形成數個第一没極以原極 延伸區，以及於第二閘極結構之第二偏側壁子外侧之基底 參 中形成數個第二汲極/源極延伸區。 本發明係提供一種製作互補式金氧半導體電晶體的方 法，包含提供一基底，形成第一、第二閘極結構於基底上， 於第、第一閘極結構周圍形成第一、第二偏側壁子。接 著，於第一、第二偏側壁子周圍形成一第一、第二犧牲側 J子，於第一、第二閘極結構之兩側形成數個磊晶層，這 些磊晶層分別位於第一、第二犧牲側壁子之外側。然後， 去除第、第一犧牲側壁子，以及於第―、第二問極結構 1303459 之兩匈之基底尹形成複數個第―、第二汲極/源極延伸區。 ，由於本發明之源極/及極延伸區係於選擇性蟲晶製程 =製作，所以選擇縣晶製程之高溫，不會破壞源極/沒 有延^區’使得本發明所製作的電晶體具有超液介面又具 、磊阳層，金屬矽化物與基底不會直接接觸，同時又維持 源極/汲極延伸區。 i 【實施方式】 清參考第1圖至第4圖，第.丨圖至第4圖係為本發明 第一較佳實施例之製作方法示意圖。半導體晶片1〇〇具有 一基底102、一閘極結構1〇4和一淺溝隔離(STI)111包圍著 問極結構1〇4，且閘極結構1〇4包含有一閘極絕緣層1〇6、 摻雜多晶石夕層（doped poly-silicon)108和一頂保護層（cap layer)ll〇 〇 w 隨後利用一沈積(deposition)製程和一非等向性#刻 * (anis〇tr〇pic etching)製程，於閘極結構104周圍形成一偏侧 壁子（offset spacer)112。接著，在於基底102和閘極結構104 上方沈積一氮化矽層（未顯示），然後，進行一非等性向性 回蝕刻，以於偏侧壁子112周圍再形成犧牲側壁子114。 請參考第2圖，以閘極結構104之頂保護層110以及 1303459 犧牲侧壁子114為蝕刻遮罩，進行一蝕刻製程，以於閘極 結構104相對兩侧之基底1〇2中分別形成一凹槽(recess)2〇2。接 著’進行一選擇性蟲晶（selective epitaxial growth，SEG)製 程，於各凹槽202中形成一磊晶層204，其中磊晶層204 之材質可為矽、鍺化矽（SiGe)或者碳化矽（siC)。然後，去 除犧牲側壁子114，接下來，進行一輕摻雜離子佈植製程 和雷射回火(laser anneal)，於閘極結構1〇4之偏側壁子m > 兩側的基底102和磊晶層204之表面，形成汲極/源極延伸 區 304 〇 請參考第4圖，再沈積一氮化矽層.(未顯示）覆蓋於 閘極結構104、偏側壁子112、磊晶層204和基底1〇2上， 並進行一非等向性钕刻，以於偏側壁子丨12周圍再形成一 主要側壁子302。接著，利用頂保護層11〇以及主要侧壁 _ 子302作為離子佈植遮罩，進行一離子佈植和雷射回火， .以於主要側壁子3〇2外側之磊晶層204中形成汲極/源極 402。之後，進行自對準金屬矽化物（salicide)製程，以於閘 極結構104、汲極/源極402上方，分別形成金屬矽化物（未 顯示）。而其中閘極結構104和汲極/源極4〇2係構成金氧 半導體電晶體。 ’ 在此第一較佳實施例中，除上述製作汲極/源極402的 作法外，另外亦可於製作磊晶層2〇4時，直接於選擇性磊 1303459 晶時加入掺質’使付形成的為晶層2Q4係為具有摻質的遙 晶，可直接作為没極/源極；又或者可於製作蠢晶層2〇4時， 還是遙晶形成不具有摻質的蠢晶層2()4，但於蠢晶層如 完成後’犧牲側壁子114未去除前，進行離子佈植製程， 使蠢晶層204具有摻質，可作為沒極/源極使用。又上述實 施例適用於PMOS、NMOS，其相關製程為f知此項技藝者 所熟知，在此不贅述。 "" 請參考第5圖至第8圖，第5圖至第8圖係為本發明 第二較佳實施例之製作方法示意圖。半導體晶片具有 一基底502，基底502具有摻雜井5〇3，在此第三較佳實施 例中掺雜井503係為Ν型井，基底5〇2上方具有閑極結構 504、506 ’且另有淺溝隔離5丨i包圍著閘極結構5〇4、5〇6， 其中閘極結構506位於摻雜井503上方。且閘極結構5〇4、 506 ^包含有閘極絕緣層508、514、摻雜多晶石夕層5丨〇、 516和頂保護層512、518。 隨後利用一氮化矽沈積製程和一非等向性蝕刻製程， 於閘極結構504周圍形成偏側壁子52〇，接續著，再進行 一沈積製％和一非等向性蝕刻製程，於閘極結構5〇6周圍 形成偏側壁子522，且偏側壁子522由非氮化矽的介電材 質所構成。接著，於基底502和閘極結構504、5〇6上方沈 積一層氮化矽層526。後續在於氮化矽層526上方形成一 1303459 ®案化硬遮罩528 ’例如—圖案化光阻層，且此圖案化硬 遮罩528係位於閘極結構504和部分基纟502的上方。接 下來’對氮化石夕層526進行一非等性向性㈣，並以圖案 化硬遮罩528為餘刻遮罩，以於閘極結構5()6之偏側壁子 522周圍形成一犧牲側壁子524。接著，利用圖案化硬遮罩 528、間極結構5〇6之頂保護層518以及犧牲侧壁子524作 為蝕刻遮罩，進行一蝕刻製裎，以於閘極結構506相對兩 側之基底502中各形成一凹槽53〇，而凹槽53〇完成後， 即可去除圖案化硬遮罩528。 請參考第6圖，接著，進行一選擇性磊晶製程，於各 凹槽530中分別形成磊晶層602，其中磊晶層602之材質 可為矽、鍺化矽（SiGe)或者碳化矽（SiC)。 請參考第7圖，進行一蝕刻製程，移除氮化矽層526、 偏侧壁子520、犧牲側壁子524。接下來，利用一遮罩（未 顯示），例如一圖案化光阻層，遮蓋住閘極結構5〇6和部分 基底502 ’並進行一離子佈植製程和雷射回火，以於問極 結構504兩側的基底502中，形成汲極/源極延伸區7〇2。 爾後，去除覆蓋在閘極結構506上的遮罩，並再形成另一 個遮罩（未顯示），例如一圖案化光阻層，遮蓋住問極纟士構 504和部分基底502,進行一離子佈植和雷射回火，以於問 極結構506兩侧的摻雜井503中，以及蟲晶層6〇2的表面， 1303459 源極延伸區彻。在本第二較佳實施例中’汲極/ 源極延伸區702係為N型輕摻雜區域，而沒極/源極延伸巴 704係為P型輕摻雜區域。另外，除上述先形纽極/源極 延伸區702，後形纽極/源極延伸區期的製程外，亦可 在其他變化型的製程中’先形成沒極/源極延伸區704，後 形成汲極/源極延伸區702。 # _參考第8圖，接續著，再沈積-氮化石夕層（未顯示） 於基底502上，並進行一非等向性餘安】，以間極結構撕 周圍形成次偏侧壁子802，且於閘極結構5〇6之偏側壁子 112周圍形成主要侧壁子8〇4。接下來，利用—遮罩（未顯 示），例如一圖案化光阻層，以遮蓋住閘極結構5〇6和部分 基底502 ,並進行一離子佈植製程和雷射回火，以於閘極 結構504之次偏側壁子8〇2以外之兩側的基底5〇2中，形 _ 成汲極/源極8〇6。爾後，去除覆蓋在閘極結構506上的遮 •罩，並再形成另一個遮罩（未顯示），例如一圖案化光阻層， 遮蓋住閘極結構504和部分基底502，再進行一離子佈植 製程和雷射回火，以於閘極結構5〇6之主要側壁子8〇4之 兩侧的蟲晶層602中，形成汲極/源極808。另外，除上述 先形成没極/源極806，後形成汲極/源極808的製程外，亦 可在其他變化型的製程中，先形成汲極/源極808，後形成 >及極/源極806。之後，再進行自對準金屬石夕化物（saiicide) 製程，以於閘極結構504、506、汲極/源極806、808上方， 13 1303459 形成金屬破化物（.未顯示）。而其中開極結構5()4、5〇6、 •汲極/源極806、娜係構成互補式金氧半導體（——η卿 ，mental oxide semiconductor，CMOS )電晶體。 在此第一杈佳實％例中，除上述製作汲極/源極8⑽的 作法外，亦可於製作磊晶層602時，直接於選擇性磊晶時 加入摻質，則形成的磊晶層602為具有摻質的磊晶，並作 •為汲極/源極使用；又或者可於製作磊晶層602時，還是磊 晶形成不具有摻質的磊晶層602,但於磊晶層6〇2完成後， 且犧牲側壁子524未去除前，進行離子佈植製程，使磊晶 層602具有摻質，利用其作為没極/源極。又上述製程是以 pM〇S具有蟲晶層的CMOS作為說明，而本發明亦適用於 NMOS具有磊晶層的CMOS。 • 請參考第9圖至第12圖，第9圖至第12®係為本發 •明第三較佳實施例之製作方法示意圖。如第9圖所示，半 導體晶片9〇〇具有一基底902，基底902具有摻雜井9〇3 , 在此第三較佳實施例中摻雜井9〇3係為N型井，基底 上方具有閘極結構904、906，且另有淺溝隔離911包圍著 閘極結構904、906 ,其中閘極結構9〇6位於該摻雜井 上方。且閘極結構904、906皆包含有閘極絕緣層9〇8、914、 摻雜多晶矽層910、916和一頂保護層912、918。 1303459 隨後利用一沈積製程和一非等向性蝕刻製程，於閘極 結構904、906周圍形成分別偏側壁子920、922。接著， 於基底902和閘極結構904、906上方沈積一層氮化石夕層（未 顯示），並進行一非等向蝕刻製程，於閘極結構9〇4、9〇6 周圍的偏側壁子920、922外側，分別再形成犧牲侧壁子 924、926。值得注意的是，偏侧壁子，92〇、922和犧牲侧壁 子924、926係由不同蝕刻選擇比之材質所組成。 明參考第10圖，接著進行一餘刻製程，以利用閘極結 構904、906之頂保護層912、918及犧牲側壁子似、 作為蝕刻遮罩，使得犧牲側壁子924兩侧之基底9〇2中， 形成凹槽1002,且於犧牲側壁子926兩侧之推雜井则中， 形成凹槽1GG4。接著，進行—選擇性蟲晶製程，於凹槽 1002、1004中分別形成磊晶層讓、刪，其中磊晶層 驅、顧之材質可為珍、鍺化邦iGe)或者碳化雜q。 請參考第11圖，進行一钕刻製程，移除犧牲側壁子 924、926。接下來，於閘極結構9〇6和部分基底術上巧 成-圖案化光阻層（未顯示），並進行—離子佈植製程和; 射回火，於閘極結構9〇4兩側之偏側壁？ 外側的基义 902中，以及磊晶層1ηΛ 川〇6的表面，形成汲極/源極延伸區 1102。接著’去除上述之圖案化光阻層，並且形成另一布 圖案化光阻層，遮蓋住閘極結構刪和部分基底術，並 1303459 進行-離子佈植製程和雷射，以於 090 Αι ;閘極、、告構9〇ό兩側 之偏谢壁子922外側的摻 •矣而，淤氺、立1 乂及蕊日日層〗008的 H及極/源極延伸區1104。在本第三較佳實施例 中，汲極/源極延伸區11Q2 U^2係為N型輕摻雜區域， / 源極延伸區1104#A 认 飞而/及極/ wr η 換雜區域。其中，形成汲極/ 源極延伸區1102、_的順序亦可調換。 ❼考第12圖’接續著，再沈積一氮化石夕層（未顯示） 於基底9G2上，並進行—非等向性侧，以閘極結構9⑽、 撕周_成主要侧壁子⑽2、丨綱。接下來，於閉極結 構906和部分基底902上形成一圖案化光阻層（未顯示）， 並進行-離子佈植製程和雷射回火，以於閘極結構，之 主要側壁子1202之兩側的蠢晶層讓中，形成汲極/源極 1206之後，去除上述之圖案化光阻層，並且於閘極結構 904和部分基底902上形成另一個圖案化光阻層（未顯 示），並進行一離子佈植製程和雷射回火，以於閘極結構 906之主要側壁子1204之兩側的磊晶層1〇〇8中，形成汲 極/源極1208。最後，再進行自對準金屬矽化物(salicide) 製程’以於閘極結構904、906、汲極/源極1206、1208上 方，形成金屬矽化物（未顯示）。而其中閘極結構904、906、 汲極/源極1206、1208係構成互補式金氧半導體電晶體。 在此第三較佳實施例中，除上述製作汲極/源極丨206、 1303459 1208的作法外，亦可於製作磊晶層1〇〇6、1〇〇8時，直接 於選擇性蟲ΘΘ時加入摻質，則形成的蠢晶層1⑼6、1〇〇8為 ，具有摻質的磊晶，可作為汲極/源極；又或者可於製作磊晶 層1006、1008時，還是磊晶成不具有摻質的磊晶層1〇〇6、 1008 ’但於磊晶層1〇〇6、1〇〇8完成後，且犧牲側壁子924、 926未去除前，進行離子佈植製程，使磊晶層1006、1008 具有摻質，將磊晶層1006、1〇〇8作為汲極/源極使用。本 _ 發明並不侷限於上述製程中PMOS和NMOS於同一製程蝕 刻凹槽、進行磊晶，亦可依照需求利用硬遮罩，分別製作 PMOS和NMOS的凹槽和磊晶層。 又值得注意的是，在前述各較佳實施例中，基底之材 質可為矽基底、矽覆絕緣基底、或者各種含有矽、鍺、鍺 化矽、碳化矽等化合物的基底；閘極絕緣層可由氧化層、 馨氧化鼠、氮層、二氧化石夕，或石夕酸給(hafnium silicates)這類 .南介電常數(High-k)材料所構成。而閘極不只可由上述之多 <晶矽構成，也可由金屬等導電材質構成，甚至可為虛設 (dummy)閘極。另外，犧牲側壁子、主要側壁子則可由〇〇、 ΟΝ、OON、ΟΝΟ、ONONO等材質構成，而金屬矽化物的 金屬部分可由鈦(Ti)、鈷(Co)、鎳(Ni)等金屬所構成。 由於本發明之源極/汲極延伸區係於選擇性磊晶製程 之後製作，所以選擇性磊晶製程之高溫，不會破壞源極/汲 1303459 極延伸區’使得本發明所製作的電晶體具有超淺介面又具 有磊a曰層，金屬矽化物與基底不會直接接觸，同時又維持 源極/沒極延伸區。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，冑應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第4 ®係為本發明第—較佳實關之製作方法示意圖。 第5圖至第8圖係為本發明第二較佳實施例之製作方法示意圖。 第9圖至第12嶋為本發明第三較佳實施例之製作方法示意圖。 【主要元件符號說明】1303459 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a gold-oxygen semiconductor transistor and a complementary MOS transistor, and then fabricating a phase-precision phase and a polarity extension region. A method of fabricating a metal oxide semiconductor transistor and a complementary MOS transistor. "[Prior Art]. With the smaller and smaller size of semiconductor components, many improvements in the transistor process, in order to produce small-volume, high-quality transistors. The prior art transistor process is to form a closed-pole structure on the germanium substrate. Then 'reusing an ion implantation method that reduces the thermal budget to form a source extension (s(10)we extension) region and a drain extension region in the germanium substrate on opposite sides of the gate structure, or It is called a lightly doped drain (LDD) source/drain. Then, a spacer is formed on the side of the interpolar structure, and the gate structure and the side wall are used as a mask to perform ions. The implantation step is to form a source/drain region in the germanium substrate. In order to properly electrically connect the gate, source and drain of the transistor to the circuit, it is necessary to form a contact plug (C〇 ntactplUg) is used for conduction, and in order to improve the contact between the metal contact plug and the closed-end structure of the semiconductor material and the source/drain region, 自动hmic c〇ntact is usually used again. Shi Xihua (self-alignecj siiicide, salieide) 1303459 Process, forming a metal telluride on the surface of the gate structure and the source/drain region. However, in the process of auto-aligning the metal telluride, the metal in the metal layer diffuses. Into the substrate and consume the germanium in the source/drain region, not only the lattice structure in the original source/drain region is destroyed, but also the 1 between the drain/source and the substrate] ^The junction is too close to the metal telluride to generate leakage. Especially in the design of ultrashallow interface (USL), it is more likely to cause component failure. At present, the better solution is to utilize Selective epitaxial growth (SEG) process, the immersion/source of the high-voltage crystal, directly contacting the source/dipper extension with the bismuth metal and the 11 substrate. However, the selective epitaxial process The temperature is 690 degrees to 79 degrees, so it will destroy the formed source / immersion ^ So how to develop a method that can make the source / drain extension and the same as the epitaxial layer Important for the important field The invention provides a method for fabricating a metal oxide semiconductor to solve the above problems. The method of the invention further comprises the step of providing a substrate for forming a metal oxide semiconductor. And forming a gate junction on the substrate =, a partial sidewall is formed around the 1303459 structure, a sacrificial sidewall is formed around the partial sidewall, and then a plurality of epitaxial layers are formed on both sides of the gate structure, and The crystal layer is located on the outer side of the sacrificial sidewall, after which the sacrificial sidewall is removed and a plurality of 1 are formed; and the pole/source extension is in the substrate outside the sidewall and in the epitaxial layer. The present invention provides a method for fabricating a complementary MOS transistor, comprising providing a substrate and forming a first gate structure, a second gate structure on the substrate, and the first and second gates. A first and a second side wall are formed around the pole structure, and a sacrificial side wall is formed around the second side wall. Then, a plurality of epitaxial layers are formed on both sides of the second gate structure, the insect layers are located on the outer side of the sacrificial sidewalls, and then the sacrificial sidewalls are removed to form in the substrate on both sides of the first gate structure. A plurality of first poles are formed in the primary pole extension region, and a plurality of second drain/source extension regions are formed in the base substrate outside the second side wall of the second gate structure. The present invention provides a method of fabricating a complementary MOS transistor, comprising providing a substrate, forming first and second gate structures on the substrate, forming first and second biases around the first and first gate structures Side wall. Then, a first and a second sacrificial side J are formed around the first and second side walls, and a plurality of epitaxial layers are formed on both sides of the first and second gate structures, and the epitaxial layers are respectively located at the first 1. The second side of the second sacrificial sidewall. Then, the first and first sacrificial sidewalls are removed, and the first and second drain/source extension regions of the two Hungarian bases of the first and second interrogation structures 1303459 are formed. Since the source/pole extension region of the present invention is in the selective insect crystal process=production, the high temperature of the county crystal process is selected, and the source/non-extension region is not destroyed, so that the transistor produced by the invention has The ultra-liquid interface has a Leiyang layer, and the metal halide does not directly contact the substrate while maintaining the source/drain extension. i [Embodiment] Referring to Figs. 1 to 4, the drawings from Fig. 4 to Fig. 4 are schematic views showing a manufacturing method of the first preferred embodiment of the present invention. The semiconductor wafer 1 has a substrate 102, a gate structure 1〇4, and a shallow trench isolation (STI) 111 surrounding the gate structure 1〇4, and the gate structure 1〇4 includes a gate insulating layer 1〇 6. Doped poly-silicon 108 and a cap layer ll 〇〇 w then utilize a deposition process and an anisotropic # * * (anis〇tr The 〇pic etching process forms an offset spacer 112 around the gate structure 104. Next, a tantalum nitride layer (not shown) is deposited over the substrate 102 and the gate structure 104, and then an anisotropic etch back is performed to form the sacrificial sidewalls 114 around the sidewall spacers 112. Referring to FIG. 2, the top protective layer 110 of the gate structure 104 and the sacrificial sidewalls 114 of the gate structure 104 are etched masks, and an etching process is performed to form the substrates 1 〇 2 on opposite sides of the gate structure 104, respectively. A recess 2〇2. Then, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer 204 in each of the grooves 202. The material of the epitaxial layer 204 may be germanium, germanium telluride (SiGe) or tantalum carbide. (siC). Then, the sacrificial sidewalls 114 are removed, and then, a lightly doped ion implantation process and a laser anneal are performed on the sidewalls of the gate structure 1 〇 4 and the substrate 102 on both sides and The surface of the epitaxial layer 204 is formed with a drain/source extension 304. Referring to FIG. 4, a layer of tantalum nitride is deposited. (not shown) is overlying the gate structure 104, the sidewall spacers 112, and the epitaxial layer. 204 and the substrate 1〇2, and an anisotropic engraving is performed to form a main sidewall 302 around the sidewall spacer 12. Then, using the top protective layer 11 〇 and the main sidewall _ sub 302 as ion implantation masks, an ion implantation and laser tempering are performed to form in the epitaxial layer 204 outside the main sidewall 3〇2. Bungee/source 402. Thereafter, a salicide process is performed to form a metal telluride (not shown) over the gate structure 104 and the drain/source 402, respectively. The gate structure 104 and the drain/source 4〇2 constitute a MOS transistor. In the first preferred embodiment, in addition to the above-described method of fabricating the drain/source 402, it is also possible to add a dopant directly to the selective protrusion 1303459 when the epitaxial layer 2〇4 is formed. The formed layer 2Q4 is a doped crystal with a dopant, which can be directly used as a immersion/source; or it can be used to form a stupid layer 2 〇 4, or a crystallite to form a doped layer without dopants. 2 () 4, but after the stupid layer is completed, the ion implantation process is performed before the sacrificial sidewall 114 is not removed, so that the stray layer 204 has a dopant and can be used as a immersion/source. The above embodiments are applicable to PMOS and NMOS, and the related processes are well known to those skilled in the art and will not be described herein. "" Please refer to Figs. 5 to 8 and Fig. 5 to Fig. 8 are schematic views showing the manufacturing method of the second preferred embodiment of the present invention. The semiconductor wafer has a substrate 502 having a doping well 5〇3. In the third preferred embodiment, the doping well 503 is a Ν-type well having a free-standing structure 504, 506' above the substrate 5〇2 and Another shallow trench isolation 5丨i surrounds the gate structures 5〇4, 5〇6, wherein the gate structure 506 is located above the doping well 503. The gate structure 5〇4, 506^ includes a gate insulating layer 508, 514, a doped polycrystalline layer 5, 516, and a top protective layer 512, 518. Then, using a tantalum nitride deposition process and an anisotropic etching process, a sidewall spacer 52 is formed around the gate structure 504, followed by a deposition % and an anisotropic etching process. A sidewall spacer 522 is formed around the pole structure 5〇6, and the sidewall spacer 522 is made of a dielectric material other than tantalum nitride. Next, a layer of tantalum nitride 526 is deposited over the substrate 502 and the gate structures 504, 5〇6. Subsequent to the tantalum nitride layer 526 is formed a 1303459 ® cased hard mask 528', such as a patterned photoresist layer, and the patterned hard mask 528 is over the gate structure 504 and a portion of the substrate 502. Next, an unequal isotropic (four) is applied to the nitride layer 526, and the patterned hard mask 528 is used as a residual mask to form a sacrificial sidewall around the sidewall spacer 522 of the gate structure 5 () 6 . Sub 524. Next, using the patterned hard mask 528, the top protective layer 518 of the interpole structure 5〇6, and the sacrificial sidewall 524 as an etch mask, an etching process is performed to form the substrate 502 on opposite sides of the gate structure 506. A recess 53 is formed in each of the recesses 53, and after the recess 53 is completed, the patterned hard mask 528 can be removed. Referring to FIG. 6 , a selective epitaxial process is performed to form an epitaxial layer 602 in each of the grooves 530 , wherein the material of the epitaxial layer 602 may be tantalum, germanium telluride (SiGe) or tantalum carbide ( SiC). Referring to FIG. 7, an etching process is performed to remove the tantalum nitride layer 526, the sidewall spacers 520, and the sacrificial sidewall spacers 524. Next, a mask (not shown), such as a patterned photoresist layer, covers the gate structure 5〇6 and a portion of the substrate 502' and performs an ion implantation process and laser tempering to solve the problem. In the substrate 502 on both sides of the structure 504, a drain/source extension 7〇2 is formed. Thereafter, the mask overlying the gate structure 506 is removed, and another mask (not shown) is formed, such as a patterned photoresist layer, covering the erectus 504 and a portion of the substrate 502 for performing an ion. The implant and the laser are tempered to ask the doping well 503 on both sides of the pole structure 506, and the surface of the serpentine layer 6〇2, the 1303459 source extension region. In the second preferred embodiment, the drain/source extension 702 is an N-type lightly doped region and the immersion/source extension 704 is a P-type lightly doped region. In addition, in addition to the above-described precursor-shaped/source extension region 702 and the process of the rear-shaped button/source extension region, the immersion/source extension region 704 may be formed first in other variations of the process. A drain/source extension 702 is then formed. # _ Referring to Fig. 8, successively, a deposition-nitriding layer (not shown) is formed on the substrate 502, and an anisotropic remnant is performed, and a sub-bias sidewall 802 is formed around the interpole structure. The main sidewalls 8〇4 are formed around the side wall 112 of the gate structure 5〇6. Next, a mask (not shown), such as a patterned photoresist layer, is used to cover the gate structure 5〇6 and a portion of the substrate 502, and an ion implantation process and laser tempering are performed to serve the gate. In the substrate 5〇2 on both sides of the pole structure 504, the second side of the pole structure 504 is formed into a drain/source 8〇6. Thereafter, the mask covering the gate structure 506 is removed, and another mask (not shown) is formed, such as a patterned photoresist layer, covering the gate structure 504 and a portion of the substrate 502, and then performing an ion. The implantation process and the laser tempering form a drain/source 808 in the worm layer 602 on both sides of the main sidewall 8 〇 4 of the gate structure 5〇6. In addition, in addition to the above process of forming the gate/source 806 and forming the drain/source 808, the drain/source 808 may be formed first in other variations of the process, and then formed into a > / Source 806. Thereafter, a self-aligned metal saiicide process is performed to form a metal break (not shown) above the gate structures 504, 506, the drain/sources 806, 808, and 13 1303459. Among them, the open-pole structure 5 () 4, 5 〇 6, • the drain/source 806, and the Na system constitute a complementary MOS semiconductor crystal cell. In the first example, in addition to the above-described method of fabricating the drain/source 8 (10), the epitaxial layer 602 can be formed, and the dopant is added directly during selective epitaxy, and the epitaxial layer is formed. The layer 602 is a doped epitaxial layer and is used as a drain/source; or when the epitaxial layer 602 is formed, an epitaxial layer 602 having no dopant is formed by epitaxy, but epitaxial After the layer 6〇2 is completed, and before the sacrificial sidewall 524 is removed, an ion implantation process is performed to make the epitaxial layer 602 have a dopant, which is used as a gate/source. Further, the above process is explained by a CMOS having a pM〇S having a crystal layer, and the present invention is also applicable to a CMOS having an epitaxial layer of an NMOS. • Please refer to Fig. 9 to Fig. 12, and Fig. 9 to Fig. 12® are schematic diagrams showing the manufacturing method of the third preferred embodiment of the present invention. As shown in FIG. 9, the semiconductor wafer 9 has a substrate 902 having a doping well 9〇3. In the third preferred embodiment, the doping well 9〇3 is an N-type well above the substrate. There are gate structures 904, 906, and a shallow trench isolation 911 surrounds the gate structures 904, 906, wherein the gate structures 9〇6 are located above the doped well. The gate structures 904, 906 each include a gate insulating layer 9〇8, 914, a doped polysilicon layer 910, 916, and a top protective layer 912, 918. 1303459 A sidewall process 920, 922 is then formed around the gate structures 904, 906 using a deposition process and an anisotropic etch process. Next, a layer of nitride layer (not shown) is deposited over the substrate 902 and the gate structures 904, 906, and an anisotropic etching process is performed on the sidewall spacers 920 around the gate structures 9〇4, 9〇6. On the outer side of 922, sacrificial sidewalls 924, 926 are formed respectively. It is worth noting that the partial sidewalls, 92〇, 922 and sacrificial sidewalls 924, 926 are composed of different etching options than the material. Referring to FIG. 10, a process is then performed to utilize the top protective layers 912, 918 of the gate structures 904, 906 and the sacrificial sidewalls as an etch mask such that the substrate on both sides of the sidewall 924 is sacrificed. In the second embodiment, the groove 1002 is formed, and in the push-well well on both sides of the sacrificial side wall 926, the groove 1GG4 is formed. Then, a selective insect crystal process is performed, and an epitaxial layer is formed and removed in the grooves 1002 and 1004, wherein the epitaxial layer drive, the material of the material can be Jane, Suihuabang iGe) or carbonized q. Referring to Figure 11, an engraving process is performed to remove the sacrificial sidewalls 924, 926. Next, a photoresist layer (not shown) is formed on the gate structure 9〇6 and part of the substrate, and the ion implantation process and the igniting are performed on both sides of the gate structure 9〇4. Side wall? In the outer base 902, and on the surface of the epitaxial layer 1n, the drain/source extension 1102 is formed. Then 'removing the patterned photoresist layer described above, and forming another patterned photoresist layer, covering the gate structure and part of the basal technique, and performing an ion implantation process and a laser on the 1303459 to 090 Α; The gate and the eccentricity of the outer wall 922 on both sides of the 〇ό 矣 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In the third preferred embodiment, the drain/source extension 11Q2 U^2 is an N-type lightly doped region, / the source extension 1104#A recognizes the fly and/and the pole/wr η change region . The order in which the drain/source extension regions 1102 and _ are formed may also be reversed. Referring to Fig. 12, a nitriding layer (not shown) is deposited on the substrate 9G2, and the non-isotropic side is formed, with the gate structure 9 (10) and the tearing perimeter _ into the main sidewall (10) 2丨纲. Next, a patterned photoresist layer (not shown) is formed on the closed-pole structure 906 and a portion of the substrate 902, and an ion implantation process and a laser tempering are performed to form a gate structure, and the main sidewall 1202 After the doping layer on both sides is formed, after forming the drain/source 1206, the patterned photoresist layer is removed, and another patterned photoresist layer is formed on the gate structure 904 and a portion of the substrate 902 (not shown). And performing an ion implantation process and laser tempering to form a drain/source 1208 in the epitaxial layer 1〇〇8 on both sides of the main sidewall 1204 of the gate structure 906. Finally, a self-aligned metal salicide process is performed to form a metal telluride (not shown) above the gate structures 904, 906 and the drain/sources 1206, 1208. The gate structures 904, 906 and the drain/sources 1206 and 1208 constitute a complementary MOS transistor. In the third preferred embodiment, in addition to the above-described method of fabricating the drain/source electrodes 206, 1303459 1208, it is also possible to directly select the selective insects when the epitaxial layers 1〇〇6 and 1〇〇8 are produced. When the dopant is added, the doped crystal layer 1(9)6, 1〇〇8 is formed, and the epitaxial layer having the dopant can be used as the drain/source; or when the epitaxial layer 1006, 1008 is formed, or The crystallized epitaxial layer 1〇〇6, 1008' does not have a dopant, but after the epitaxial layers 1〇〇6, 1〇〇8 are completed, and the sacrificial sidewalls 924 and 926 are not removed, the ion implantation process is performed. The epitaxial layers 1006 and 1008 are doped, and the epitaxial layers 1006 and 1 8 are used as the drain/source. The invention is not limited to the PMOS and NMOS etching recesses in the same process in the above process, and the epitaxial etching is performed, and the PMOS and NMOS recesses and epitaxial layers can be respectively fabricated by using a hard mask according to requirements. It is also noted that, in the foregoing preferred embodiments, the material of the substrate may be a germanium substrate, a germanium insulating substrate, or various substrates containing germanium, germanium, germanium, germanium, and the like; a gate insulating layer. It can be composed of an oxide layer, a oxidized mouse, a nitrogen layer, a dioxide dioxide, or a hafnium silicates. The gate can be composed not only of the above-mentioned crystals, but also of a conductive material such as metal, or even a dummy gate. In addition, the sacrificial side wall and the main side wall may be made of materials such as tantalum, niobium, OON, niobium, ONONO, etc., and the metal part of the metal telluride may be made of metal such as titanium (Ti), cobalt (Co), or nickel (Ni). Composition. Since the source/drain extension of the present invention is fabricated after a selective epitaxial process, the high temperature of the selective epitaxial process does not destroy the source/汲1303459 pole extension' such that the transistor fabricated by the present invention It has an ultra-shallow interface and a Lei-A layer. The metal telluride does not directly contact the substrate while maintaining the source/polar extension. The above are only the preferred embodiments of the present invention, and the equivalent variations and modifications made by the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 4 are schematic views showing the manufacturing method of the first preferred embodiment of the present invention. 5 to 8 are schematic views showing a manufacturing method of a second preferred embodiment of the present invention. 9 to 12 are schematic views showing a manufacturing method of a third preferred embodiment of the present invention. [Main component symbol description]
100、500、900 102、502、902 半導體晶片 基底 104、504、506、904、906 閘極結構 106、508、514、908、914 閘極氧化層 108、510、516、910、916摻雜多晶石夕層 110、512、518、912、918 頂保護層 111 ' 511、911 淺溝隔離 112、520、522、920、922 偏侧壁子. 114、524、924、926 犧牲側壁子 202、530、1002、1004 凹燐 18 1303459 204、602、1006、1008 遙晶層 304、702、704、1102、1104 汲極/源極延伸區 402、806、808、1206、1208 没極/源極 503 、 903 摻雜井 526 氮化石夕層 528 圖案化硬遮罩 802 次偏側壁子 302、804、1202、1204 主要側壁子100, 500, 900 102, 502, 902 semiconductor wafer substrate 104, 504, 506, 904, 906 gate structure 106, 508, 514, 908, 914 gate oxide layer 108, 510, 516, 910, 916 doped The spar layer 110, 512, 518, 912, 918 top protective layer 111 ' 511, 911 shallow trench isolation 112, 520, 522, 920, 922 side wall. 114, 524, 924, 926 sacrificial sidewall spacer 202, 530, 1002, 1004 recesses 18 1303459 204, 602, 1006, 1008 tele-crystal layers 304, 702, 704, 1102, 1104 drain/source extensions 402, 806, 808, 1206, 1208 gate/source 503 903 doped well 526 nitrided layer 528 patterned hard mask 802 times side wall sub-frames 302, 804, 1202, 1204 main side wall
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