TW201201292A - Semiconductor bio-sensors and methods of manufacturing the same - Google Patents

Abstract

A method of manufacturing a semiconductor bio-sensor comprises providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions, forming a second dielectric layer, a third dielectric layer and a fourth dielectric layer in sequence over the patterned first conductive layer, forming cavities into the fourth dielectric layer, forming vias through the cavities, exposing the second portions of the patterned first conductive layer, forming a patterned second conductive layer on the fourth dielectric layer, forming a passivation layer on the patterned second conductive layer, forming an opening to expose a portion of the fourth dielectric layer over the first portion of the patterned first conductive layer, and forming a chamber through the opening.

Description

201201292 • --------- VI. Description of the Invention: _ * Technical Field of the Invention The present invention relates to a method of fabricating a semiconductor device, and more particularly to the manufacture of a semiconductor biosensor method. [Prior Art] With the growth of the semiconductor industry and the advancement of semiconductor processes, computers, communications, and products have been increasingly designed to be compact and miniaturized. As such, biosensors are manufactured with a reduced size target to achieve portable and miniaturized requirements. 1A to 1C are schematic cross-sectional views showing a method of fabricating a semiconductor biosensor of the prior art. Referring to Fig. 1A, a substrate 1 is provided. The first dielectric layer n may include, for example, hafnium oxide (Si. 2). The first dielectric I U may be subsequently formed on the substrate 10. The first dielectric layer 11 can be used as a pad layer. Referring to FIG. 1B, the patterned conductive layer 12 may include, for example, a polysilicon 矽 which may be formed on the first dielectric layer U. The patterned conductive layer 12 can be used as the sensing resistor of the biosensor 1. The portion of the patterned conductive layer: portion 12-1 may be implanted or lightly miscellaneous by the first type of impurity, for example, the n-type impurity doping may provide the impedance required to sense the resistance. In addition, the second portion 2_2 of the patterned conductive layer 12 can be heavily implanted or re-doped by the first type of impurity to form an electrical contact region of the sense resistor. Referring to Figure 1C, a second dielectric layer 14 is formed on the patterned second conductive layer 12 and the first dielectric layer. The second dielectric layer 14 can include, for example, a dioxotomy. The second dielectric layer can be used as an insulating layer for the sense resistor of the biosensor. ' 201201292

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The demand for integration of Pic sensor biometrics with other semiconductor components is increasing, and biosensing semiconductors (CMOS) processes must be used to fabricate biosensors and semiconductor components. However, unfortunately, the biosensing written thin insulating layer 14 and the conductive layer 12, if not properly protected, may be easily destroyed in the CMOS process. Therefore, the development of a manufacturing method for manufacturing a semiconductor biosensor and other semiconductor components in a CM〇s process is one of the needs of related companies.

SUMMARY OF THE INVENTION The present invention is generally directed to a manufacturing method that can be fabricated on a single wafer in combination with a semiconductor biosensor and other CMOS components. An embodiment of the present invention can provide a method of fabricating a semiconductor fabrication method. The method can include providing a substrate on the substrate to form a patterned first conductive layer on the first dielectric layer, the patterned first conductive layer including a first portion and a pair of second portions. The second part is the first part of the package, and the fourth layer is formed on the patterned first conductive layer. The fourth dielectric layer has a higher rate than the pattern. The third dielectric layer is formed on the second dielectric layer. The fourth dielectric layer 'the fourth dielectric layer _ rate is greater than the third dielectric layer == using isotropic (four) to form a plurality of holes in the fourth dielectric layer, • 1 is formed by non-specific etching through these holes Patterning the first conductive layer to circumscribe the second conductive layer and filling the holes, and forming a plurality of potentials in the upper part of FIG. 2: forming, in the patterning, the first Forming an opening that exposes a portion of the fourth dielectric layer 201201292 i, through which the chamber is formed by isotropic etching between the plurality of pads. According to some embodiments of the present invention, a method of manufacturing a semiconductor biodetector is also provided. The method may include providing a substrate, forming a first dielectric layer on the substrate, forming a patterned first conductive layer on the first dielectric layer, and patterning the first conductive layer to include a first portion and a pair of second portions, Forming a second dielectric layer, a third dielectric layer, and a fourth dielectric layer on the patterned first conductive layer, forming a plurality of holes in the fourth dielectric layer to form a plurality of holes extending through the holes a via hole, the second portion of the patterned first conductive layer is exposed, a patterned second conductive layer is formed on the fourth dielectric layer, and a protective layer is formed on the patterned second conductive layer to be patterned first An opening is formed over the first portion of the conductive layer, the opening exposing a portion of the fourth dielectric layer and forming a chamber therethrough. Several embodiments of the present invention may further provide a semiconductor biosensor. The semiconductor biosensor includes a substrate, a first dielectric layer on the substrate, a patterned first conductive layer on the first dielectric layer, and the patterned first conductive layer includes a first portion and a first package a second portion of the second portion, the second dielectric layer on the patterned first conductive layer, the second dielectric layer having a ratio greater than the patterned first conductive layer: located on the second dielectric layer The third dielectric layer is located on the fourth dielectric layer on the third dielectric layer, the etching rate of the fourth dielectric layer is greater than the etching rate of the third dielectric layer, and one of the butting pads on the second portion is electrically Optionally connected to the second portion, the patterned second conductive layer on the pad, and the channel region between the pads and exposing the third dielectric layer. Other characteristics and advantages of the present invention will be apparent from the description of the section of the specification. Features and advantages of the present invention will be realized and attained by the <RTIgt; The above summary and the following detailed description are merely illustrative of exemplary embodiments of the invention and are not intended to limit the invention. The above description of the present invention is intended to be illustrative of the preferred embodiments of the invention. [Embodiment] The following is a detailed description of several embodiments and the accompanying drawings. Wherever possible, the same or similar parts are indicated in the drawings. It must be noted that the drawings are mostly in a simplified form and the invention should not be limited to the particular precise dimensions of the drawings. 2A through 2M are cross-sectional views showing a method of fabricating a semiconductor biosensor according to an embodiment of the present invention. Referring to the 2A φ diagram, a substrate 20 is provided, and the substrate 20 is doped with a first type impurity, such as a p-type impurity. Next, a plurality of Complementary Metal-Oxide-Semiconductor Devices (CMOS) elements 21, that is, complementary and symmetric ones of the first and second types of elements, such as n-type and p-type metal oxide semiconductors Metal oxide semiconductor field effect transistors (MOSFETs) may be formed on the substrate 20. In an embodiment, the CMOS device 21 may include a pair of first and second types of MOSFETs 21-1 that are operable at a higher operating voltage, such as a 12 volt (v) operation 201201292 voltage, and another For the first and second types of MOSFETs 21-2 '. , , : The general operating voltage, for example, the operating voltage of 5 volts (v) can be: and decoupled with a pair of first type and second type tM 〇 SFETs2i_3,. For lower operating voltages, such as 3, the operating voltages of FETs 2Μ, 21-2, and 21_3 volts (V) can be operated. In addition, a plurality of peripheral elements 22 can be switching elements. Next to component 21. In one embodiment, the peripheral elements:; 20 20 JM0S and resistor 22-2. The capacitor 22-1 may include a capacitor 22-1, and a dielectric layer 220, and the dielectric layer 22 is located between the first and second poles 222. Capacitor 22 is cut to detect the force applied above 1 and thus can be used as a sound sensor. /, the upper part can have a variable resistance and can be used as a thermopile. The temperature can be detected by 22-2. change. CM0S yuan ‘^. The stack sensing can be formed in the first region of the substrate 2 in the C0MS process. Please refer to FIG. 2B. The deposition step can form the 23rd C-clamp element 21 and the peripheral component L. And the substrate 2; 1 consistently, the 'first dielectric layer 23' may include undoped dioxide: ^^(USOOX), 900 „(Λ) ~π〇〇! The electrical layer can serve as an interface layer. Next, the 'patterned first-conducting layer 24^ deposition step and the subsequent lithography, (4) process 'beside the second element 22 of the substrate 2'. In the embodiment, the patterning The first conductive household = in the range including the thickness from 500 A to 700 A of the bulk material. In another embodiment, the patterned first conductive layer 24 may include polycrystalline (10) y-SiGe). In another embodiment, the 'patterned first conductive layer % 201201292 may include single crystal germanium or nano germanium. The patterned first conductive layer is the sensing resistance of the biosensor. As the n2c image, the patterned first conductive Layer 24 can then be implanted with a first type impurity or a second type impurity. In particular, the first portion f24-1 of an embodiment 24 2 can be implanted in small amounts. Concentration: a first type impurity in the range of about 2.5 x 10 cm to 5 x 10 cm -2. The light implanted portion 24 of the patterned first conductive layer 24 can serve as an impedance region for providing the impedance required for the sense resistor. In addition, in the patterned first conductive layer 2, the second portion 24_2 is sandwiched between the first portion 24-1 and the second portion 24-2, and the second portion 24-2 can be implanted in a large amount at a concentration of about 3 χΐ〇]5 cm_2. Impurity. The re-implanted portion 24_2 of the patterned first conductive layer 24 can sense the electrical contact area of the resistor. ... In another embodiment, the first portion 24 of the patterned first conductive layer 24 can be implanted in small amounts. Type II impurity, implanted in the second type impurity concentration range from 2.5 X! 014 cm-2 to 5 χ i 〇丨4 cm_2, the resistance zone, (4) the second part of the conductive layer 24 _2 can be used to implant a second type of miscellaneous shell with a concentration range of approximately 3χ1〇15 cm·2 to form the electrical contact area of the sensing resistor of the biosensor. Part 24] is implanted prior to the second portion 24_2, however, 'in the present invention (4) belongs to the technical field, the general knowledge of the implant is known. The order can be exchanged. The second dielectric layer 26 can be formed by the deposition step on the first dielectric layer 23, the patterned first conductive layer 24, and the substrate 2A. The dielectric layer 26 may desirably be attached to the patterned first electrical layer 24° in the embodiment, and the second dielectric layer 26 may include two** 9 201201292 •, '....... 'Thin thickness cerium oxide has a thickness ranging from about 40 to ^^. In another embodiment, the second dielectric layer 26 can comprise a mouse emulsified stone (SiON). The second dielectric layer 26 can serve as a first insulation that provides the desired adhesion when attached to the sense resistor.

Further, a third dielectric layer 27 can be formed on the second dielectric layer 26 by a deposition step. In one embodiment, the third dielectric layer 27 may comprise hafnium nitride (Si3N4) having a thinner thickness ranging from about 130 A to about MO A. In another embodiment, the third dielectric layer 27 may comprise aluminum nitride (AlN). The third dielectric layer 27 can serve as a second insulation for providing electrical isolation between the layers formed thereon and the sense resistor. In a further embodiment, a third insulation (not chlorotic) of nitrous oxide (Si0N) may be selectively formed on the first insulation (ie, the second dielectric layer, the second insulation (ie, the second dielectric) Between layers 27).

Next, a fourth dielectric layer 28 can be formed over the third dielectric layer 27 by a deposition step and a subsequent planarization step, such as a chemical mechanical polishing (CMP) step. In an embodiment, the fourth dielectric layer μ may: include a first sub-layer of undoped oxidized oxidized glass (USG0X) (not dried and a second sub-layer of borophosphoquinone glass (BPSG) (not drawn The first sublayer has a thickness in the range of about 900 A to iiooa, and the first layer has a thickness of about 7000 A. The fourth dielectric layer 28 can function as an Inter-Layer Dielectric (ILD). Referring to FIG. 2E, a first photomask layer 29 can be formed on the fourth dielectric layer 28 by a coating step. In the embodiment: the first photomask layer 29 can include a photoresist. Using the patterned first light 29 as a mask, the non-isotropic etching mask f 10 201201292 \wjy &lt;^yrf\ is formed, for example, by a dry etching step to form through the first to fourth dielectric layers 23, 2 cmos ^21w42^^ Some of the first via-holes 3 (M can expose the regions of the respective m〇SfeTs 2 and 21d and the source 21s. In addition, the other first vias expose the resistor 22-2 and the capacitor 22_ The _electrode 22 ι 盘 = electrode 222. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The cover layer 31 is on the fourth dielectric layer 28: = the patterned second shirt layer 31 is used as a mask, and the first cavity 32 is formed in the fourth dielectric layer 28 by, for example, isotropic (4) of thirsty silver. Above the electrical contact region 24-2 of the sensing resistor. Referring to FIG. 2G, the second through hole % of the first hole 32 may be patterned to etch the second mask layer 31 as a masking step. , the third, and the fourth dielectric layer == and forming a second in the embodiment - the anisotropic etching step may have a ratio of fossils to the polycrystalline joy. For example, two The igniting rate of oxidized stone is about 5G angstroms per second (Hungarian to angstroms per second (10)) and the rate of crystal money is about 5^ to 85^. Therefore, cerium oxide and The selection ratio of the polysilicon is between about 5 88 and η. Thus, when the portion of the second dielectric layer 26 which may include the cerium dioxide is fully etched, the electrical contact region 24_2 including the polycrystalline stone may be in the non- The isotropic etching process is slightly entrapped. The second via 33 may thus expose the electrical contact region 24-2. Although in this embodiment, the first via 3 The formation is earlier than the formation of the second through hole 33. However, it is known in the technical field of the present invention that the order of forming the first through hole 30 and the second through hole 33 can be exchanged. Referring to FIG. 2H, the patterned second mask layer 3] can then be removed, and a second conductive layer can be formed on the fourth dielectric layer 28 by, for example, a sputtering step. The second conductive layer 37 is filled with the first layer. The via hole 3 is formed with the second via hole 33, and a first contact % is formed in the first region of the substrate 20, and a second contact % and the succeeding 36 are formed over the contact region 24_2 of the second region of the substrate 20. In an embodiment, the second conductive layer 37 may comprise a copper alloy (AlCu). Further, the second conductive layer 37 has a thickness of about 7 Å. Referring to Fig. 21, the patterned third mask layer 38 is formed over the second conductive layer 37. Using the patterned third mask layer 38 as a mask, the first conductive layer 37 can be left to form the patterned second conductive layer 37". The patterned second conductive layer 37-1 can be electrically connected to the first contact 34 and the pad 36 as an interconnect layer. In particular, the gate contact 21d of each of the MOSFETs 21 and the source 21s, the peripheral element 22, and the electrical contact region 24_2 of the sense resistor can be electrically coupled by the interconnect layer (ie, the patterned second conductive layer 37). ^ To an external circuit. Referring to FIG. 2J, the patterned third mask layer 38 can then be removed, and a fifth dielectric layer 39 is formed on the fourth dielectric layer 28 and the patterned second conductive layer 37] by a deposition step. In an embodiment, the fifth dielectric layer 39 may comprise a dioxide dioxide and has a thickness of about 2 intrusions. Further, the sixth dielectric layer 4 can be formed on the fifth dielectric layer by a deposition step. In the embodiment, the sixth dielectric layer 4A may include Nitrogen Oxide (SiW4) and has a thickness of about 7 Å. The fifth dielectric layer 39 and 12 201201292 VYjyoyrn The sixth dielectric layer 40 can be used together as a protective layer to pattern the second conductive layer. In addition, the sixth dielectric insulation provides rigidity to provide physical protection to the patterned second conductive sound = 4 to be damaged by subsequent processes. e, free, then a patterned fourth mask layer 41 is formed on the first. The opening 42 is formed by using the patterned fourth mask layer 41 as a masking layer (IV), and the opening 42 penetrates the fifth to the second = 39, and 40 and enters the fourth dielectric layer 28 to expose the electrical layer. Four dielectric layers 28. The opening 42 can be referred to as the 2K @, and the fourth mask layer 41 is made to ^ ' and the anisotropic step is engraved from the first opening 42 to the fourth = electricity: 3. In particular, the 'on the etch step can have a ratio of choice for cerium oxide over the nitrogen ray = insect. For example, the carbon dioxide engraving rate may range from about m a/s and from 矽 A 10 A/s to 1 WWA/S. Therefore, the selectivity ratio of dioxin H to nitrogen cut is approximately in the range of 64.7 _114. After the isotropic step, the second dielectric layer 39', which may include the dioxo prior, and the fourth dielectric layer 28, which may be between the pads 36 and may include usG〇x and BPSG, may be heavily engraved. And the sixth dielectric layer 40 surrounding the periphery of the first opening 42 and including the nitrite and the third dielectric layer 27 including the gasification stone (ie, the second insulation) may be slightly surnamed and thus exposed A portion 27" of the third dielectric layer 27 is formed, and a portion 27-1 of the third dielectric layer 27 is located above the first portion 24_1. The chamber 43 can serve as a passage area for the biosensor. This portion will be described later in the paragraph of Fig. 13 201201292 3 . Referring to Figure 2L, the patterned fourth mask sheet 4 can then be removed and a patterned fifth mask layer can be formed on the sixth dielectric layer core. By patterning the fifth mask layer 44 as a mask and by dry+, a second opening 45 and a third opening 46 may be formed through the sixth dielectric layer 4G and into the fifth dielectric layer 39. In particular, the second opening 45 substantially exposes the plurality of portions 37 of the patterned second conductive layer 37-1, and the plurality of portions 37 of the second conductive layer 37-1 are located above the plurality of first contacts 34. And several first-contact systems are associated with the source 21s and the bungee 21d of m〇sfeTs. The exposed portions 371a can have a plurality of pads of the MOSFETs component 21. These pads are operable at 5 V and 3 V operating voltages. In addition, the second opening 45 actually violently exits the plurality of portions 37·^ of the patterned second conductive layer 37], and the plurality of portions 37_lb of the gold 37-1 are located above the 周边 of the peripheral component. In addition, the third opening 46 may substantially expose a plurality of portions 37 of the second conductive layer, such as a patterned second conductive ^

St娄=分37七系 is located in the contact sense resistor read. &quot; Several second contacts above 35. The exposed portions of the 37-lc can be used as pads for the sensing resistors of the biosensor. Referring to the M2M mesh, the patterned fifth reticle external connection 47 can then be removed to the patterned portions of the second spurs 37-la, 37-lb, and 37_lc. The semiconductor element including the #CM〇s element 21, the edge element 22, and the biosensing II 25 is assembled by a plurality of connecting wires 47 to perform specialization or customization 201201292 I w jyoyv t\ Fig. 3 The cross-sectional view of the operation mode of the semiconductor device 2 in the 2M drawing is not shown. Referring to Fig. 3, a voltage % can be applied to the sense resistor 25 during operation so that a current Is is generated, and the current flows through the conductive layer - 丨, the junction 36, the second contact 35, and the sense resistor 25. The chamber 43 as the passage region of the biosensor can receive the electrolyte 48 generated by sampling the organism at the time of detection (not shown). The sense resistor 25 can then sense the ions 49 in the electrolyte 48. In particular, some of the ions 49 in the electrolyte 48 may contact the upper surface of the second insulation (i.e., the third dielectric layer 27). Contacting the second insulation (the third dielectric layer 27^~ the upper surface of the ion 49 after passing through the thinner first insulation (second dielectric layer 26) and the second insulation (third dielectric layer 27) The ions 50 of opposite polarity are sensed in the sense resistor 25. The ions 5 牵引 pulled in the sense resistor 25 affect and change the doping concentration in which the implant is implanted in a small amount, and thus the sense resistor 25 can be changed. The sheet resistance. Therefore, the magnitude of the induced current is flowing through the sense resistor 25 can be changed by giving a fixed applied voltage Vs. The amount of change in the induced current Is can then be measured, and thus can be called by biological sensing. The ion 49 in the electrolyte 48 is measured. When the abnormally functioning organism is detected, the abnormal ion 49 = concentration which deviates from the standard value is caused, causing the deviation of the ion 50 in the sensing resistor 25, thereby causing the resistance value therein. Therefore, the biosensor can detect the abnormality of the function of the birthed object. Further, in the semiconductor element 2〇0, the capacitor can function as a sound sensor, and the resistor 22-2 can be used as a thermopile sensing. In summary, although The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. It is to be understood that the present invention can be used in various forms without departing from the spirit and scope of the invention. ---.

Λ· V is more moving and retouching. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are schematic cross-sectional views showing a manufacturing method of a semiconductor biosensor in the prior art. 2A to 2D are schematic cross-sectional views showing a method of fabricating a semiconductor biosensor according to an embodiment of the present invention. Figure 3 is a schematic cross-sectional view showing the operation of the semiconductor biosensor in Figure 2M. [Description of main component symbols] 20: Substrate 21: Complementary metal oxide semiconductor device 21d: Deuterium 21s: Source 22: Peripheral element 22-1: Capacitor 22-2: Resistor 23: First dielectric layer 24: Patterning A conductive layer 24-1: first portion 24-2: second portion 25: sense resistor 201201292 1 w jy〇yr/-\ 26: second dielectric layer 27: third dielectric layer 28: fourth dielectric Layer 29: Patterning the first mask layer 30-1, 30-2: first via 31: patterning the second mask layer 32: first aperture • 33: second via 34: first contact 35: Second contact 36: pad 37: second conductive layer 37-1: patterned second conductive layer 38: patterned third mask layer 39: fifth dielectric layer 40: sixth dielectric layer 41: pattern Fourth photomask layer 42: first opening 43: chamber 44: patterned fifth mask layer 45: second opening 46: third opening 17 201201292 47: external connecting wire 48: electrolyte 49, 50: ion 220: dielectric layer 221: first electrode 222: second electrode

Claims (1)

201201292 VII. The scope of the patent application: 1. A method for manufacturing a semiconductor biosensor, the method comprising: providing a substrate; forming a first dielectric layer on the substrate; forming a patterned first conductive layer On the second dielectric layer, the pattern-V electrical layer includes a first portion and a pair of second portions, the first portion of the pair sandwiching the first portion in the form of a sandwich; a second dielectric layer on the patterned first conductive layer, the second dielectric layer having a _ rate greater than a ratio of the patterned first conductive layer; forming a third dielectric layer on the second dielectric layer Forming a fourth dielectric layer on the third dielectric layer, the fourth dielectric layer having a higher engraving ratio than the third dielectric layer; and forming by isotropic etching a plurality of holes are formed in the fourth dielectric layer; forming a plurality of through holes extending through the holes 2 by an anisotropic etching to expose the second portions of the patterned first conductive layer; Forming a second conductive layer on the fourth dielectric layer, the patterned first conductive layer filling the holes And forming a plurality of interfaces over the first portion of the patterned first conductive layer; forming a protective layer on the patterned second conductive layer; forming an opening by anisotropic contact The opening exposes a portion of the fourth dielectric layer over the first portion of the patterned first conductive layer; and a cavity is formed between the pads via the opening by the specific characterization. The method of claim 1, wherein the forming of the first dielectric layer further comprises forming a plurality of complementary metal oxide (CMOS) A-pieces and a plurality of peripheral components. One of the first regions of the substrate. 3. The method of claim 2, wherein forming the patterned first conductive layer further comprises: implanting a first type impurity into the first portion to a small amount of the first type impurity; The first type impurity and the second type impurity are implanted in a large amount to the second portions. 4. The method of claim 1, wherein the second dielectric layer comprises a material selected from the group consisting of cerium oxide and cerium oxynitride. 5. The method of claim 1, wherein the second dielectric layer comprises a material selected from the group consisting of tantalum nitride and aluminum nitride. 8. The method of claim 1, wherein the fourth dielectric layer comprises one of undoped yttrium oxide glass (USG〇x) and one of borophosphorus ruthenium (BPSG). Two sub-layers. The method of claim 7, wherein the forming the protective layer further comprises: forming a fifth dielectric layer on the patterned second conductive layer; and forming a sixth dielectric layer thereon On the fifth dielectric layer. 8. The method of claim 7, wherein the dielectric layer comprises ruthenium oxide and the sixth dielectric layer comprises tantalum nitride. 9. A method of fabricating a semiconductor biosensor, the method comprising: providing a substrate; 20 201201292 1 yy jy〇yrt\ forming a first dielectric layer on the substrate; forming a patterned first conductive layer The first conductive layer includes a first portion and a pair of second portions on the first dielectric layer. The first conductive layer and the third dielectric layer are sequentially arranged above the patterned first conductive layer. An electrical layer and a fourth dielectric layer; forming a plurality of holes in the fourth dielectric layer; forming a plurality of through holes penetrating the holes to expose the second portions of the conductive layer; Forming a patterned second conductive layer on the fourth dielectric layer; forming a protective layer on the patterned second conductive layer; forming an opening to expose a portion of the patterned θ-conductive layer a portion of the fourth dielectric layer above; and a chamber is formed through the opening. 10. The method of claim 9, wherein the second electrical layer has a method with a residual ratio greater than that of the patterned first conductive layer, and the method of claim 9, wherein the fourth The 曰-etching rate is greater than the residual ratio of the third dielectric layer.丨2. The through holes penetrating the holes as described in claim 9 further include: 31 H, forming a shell, forming a patterned mask on the fourth dielectric layer; And the isoelectricity of the fourth electrical layer of the f4, forming a plurality of holes f3 by: anisotropically forming the through holes penetrating the holes. The method of claim 9, wherein the forming the 21 201201292 chamber further comprises forming a patterned mask on the protective layer; the fourth dielectric layer is engraved by an anisotropic The protective layer is engraved to form the opening; and the chamber is formed through the opening by an isotropic etching. 14. A semiconductor biosensor, comprising: a substrate; a first dielectric layer 'on which is formed on the substrate; a patterned first conductive layer is formed on the first dielectric layer, and the patterned first conductive layer includes a first portion and a sandwich portion of the first portion to the second portion; An electric layer formed on the patterned first conductive layer, the second dielectric layer having an etch rate greater than an etch rate of the patterned first conductive layer; x a third dielectric layer formed on the second dielectric layer On the electrical layer; a fourth dielectric layer is formed on the third dielectric layer, the fourth dielectric layer has an etch rate higher than that of the third dielectric layer; and a pair of pads are formed over the second portions. The mating pad is electrically connected to the second portions; the patterned second conductive layer is formed on the pads; and a channel region is located between the pads and exposing the third dielectric layer . The semiconductor biosensor of claim 14, wherein the first portion of the patterned first conductive layer comprises a lightly doped impurity and the second portions comprise a heavily doped impurity. 22 201201292 It is difficult to (4) 14 rhyme semiconductor biosensing The second dielectric layer of Yi', 5hai includes one of one selected from the group consisting of cerium oxide and cerium oxynitride. 〇 σ 17. The semiconductor biosensor as described in claim 14 of the patent application. The second dielectric layer includes one material selected from the group consisting of nitride nitride and nitride. Cry 8 · The semiconductor biosensing as described in claim 14 of the patent range ° wherein the 5th fourth dielectric layer comprises one of the undoped yttrium oxide glass (USGOX) and the borophosphon glass (BPSG) ) one of the second sub-layers. 19. The semiconductor biosensing of claim 14, further comprising a protective layer on the fourth dielectric layer to expose the pass region, wherein the protective layer comprises a fifth dielectric layer And a sixth dielectric layer on the fifth electrical layer. The semiconductor biosensing L匕矽 described in claim 19: the fifth dielectric layer includes yttrium oxide, and the sixth The electrical layer includes 23