CN104051512B - The back side sensing biological field effect transistor of performance enhancement - Google Patents

Abstract

The present invention provides a kind of biological field effect transistor（BioFET）With the method for manufacture BioFET device.This method includes：Using with complementary metal oxide semiconductor（CMOS）Process compatible or the distinctive one or more processing steps of CMOS technology form BioFET.BioFET device includes the dielectric layer in the opening of substrate, the transistor arrangement with the process layer adjacent to channel region, separation layer and the separation layer in process layer.Dielectric layer and process layer are arranged on the side relative with grid structure of transistor.Process layer can be the channel layer or depletion layer being lightly doped.Biological field effect transistor is sensed present invention also offers a kind of back side of performance enhancement.

Description

The back side sensing biological field effect transistor of performance enhancement

Related application

This application claims entitled " the Backside Sensing BioFET with submitted on March 14th, 2013 The priority of Enhanced Performance " the 61/785th, No. 055 U.S. Provisional Patent Application, entire contents are combined Reference is used as in this.

Technical field

Method the present invention relates to biology sensor and for forming biochip.The invention particularly relates to biology biography Biochip of sensor and fluidic hardware and forming method thereof.

Background technology

Biology sensor be for sense and detectable biomolecule device, and based on electronics, electrochemistry, optics and Mechanical detection principle is operated.Biology sensor including transistor is electrical sensing electric charge, photon and biological entities or life The sensor of the mechanical property of thing molecule.Can be by detecting biological entities or biomolecule in itself, or via specified anti- Interaction and reaction between thing and biological entities/biomolecule is answered to perform detection.Semiconductor technology can be used to make Such biology sensor is made, the biology sensor can rapidly converted electrical number, and being readily applied to integrated Circuit（IC）And MEMS（MEMS）.

Biochip is substantially that can perform the small-size laboratory of hundreds and thousands of simultaneous biochemical reactions. Biochip can detect specific biological molecules, the characteristic for measuring them, process signal and even can be with Direct Analysis data. Biochip enables researcher rapidly to shoot a large amount of biological analytes of negligible amounts, for from medical diagnosis on disease to biology A variety of purposes of the detection of terrified agent.Advanced biochip uses multiple biology sensors together with micro jetting technology, with integrated Reaction, sensing and sampling management.BioFET（Biological field effect transistor or biological organic field-effect transistor）It is a species The biology sensor of type, including for electrical sensing biomolecule or the transistor of biological entities.Although BioFET is at many aspects All it is favourable, but for example due to the compatibility issue between semiconductor fabrication process, biologic applications, to semiconductor manufacturing work The constraint and/or limitation of skill, the sensitivity of electric signal and biologic applications and resolution ratio and/or by realizing large-scale integrated（LSI） Other challenges that processing is produced, cause to produce challenge in their manufacture and/or operation.

The content of the invention

In order to solve the defect in the presence of prior art, there is provided a kind of biological field according to an aspect of the present invention Answer transistor（BioFET）Device, including：Substrate；Transistor arrangement, in the substrate have positioned at source area, drain region with And the grid structure of active region, the active area include channel region and process layer；Separation layer, positioned at the substrate and institute State on the relative side of grid structure, the separation layer has opening at the active area of the transistor arrangement；And Dielectric layer, in the opening.

In the BioFET device, the process layer is lightly-doped layer.

In the BioFET device, the process layer includes that doping type is opposite with the dopant in the channel region mixes Debris.

In the BioFET device, the process layer includes hydrogen.

The BioFET device further comprises：Metal crown structure, covers above the separation layer and at least in part Build the side wall of the opening.

In the BioFET device, the dielectric layer include aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, tin oxide or it Combination.

The BioFET device further comprises：It is arranged on the jet raceway groove on the separation layer.

The BioFET device further comprises：Multilayer interconnection part（MLI）, be arranged in the substrate substrate with On the grid structure identical side.

In the BioFET device, via the passivation layer above the MLI, carrier substrates are bonded on the substrate.

According to another aspect of the present invention there is provided a kind of method for manufacturing BioFET device, including：In Semiconductor substrate Upper formation transistor, wherein, the transistor include the grid structure that is formed in the first side of the Semiconductor substrate and Active area between source area and drain region；Lost in the separation layer being arranged in the second side of the Semiconductor substrate Carve opening, the active area of the opening exposure transistor；By the bottom of the opening, dopant is embedded in the crystal To form process layer in the active area of pipe；And in the process layer dielectric layer.

In the method, the embedded dopant includes：Inject electric conductivity opposite with the dopant in the active area Dopant.

In the method, the embedded dopant further comprises：Form injecting mask；Activate the dopant；And Remove the injecting mask.

In the method, the embedded dopant includes：When the transistor is n-type transistor, injection hydrogen or deuterium.

In the method, the embedded dopant includes：The sacrificial dielectric of heavy doping is formed in said opening；Make to mix Debris diffuses to the active area from the sacrificial dielectric；And remove the sacrificial dielectric.

This method further comprises：The Semiconductor substrate is annealed in oxygen or hydrogen/deuterium environment.

This method further comprises：The Semiconductor substrate is thinned；And in the second side of the Semiconductor substrate Layer deposited isolating.

In the method, the Semiconductor substrate is SOI substrate, and described be thinned removes burial oxidation at least in part Nitride layer.

This method further comprises：In dielectric layer formation metal crown structure, one of the metal crown structure Divide a part for the covering separation layer；And engage acceptor in the metal crown structure, wherein, the acceptor be selected from by The group that enzyme, antibody, part, acceptor, peptide, nucleotides, organ cell, organism and tissue fragment are constituted.

According to another aspect of the invention there is provided a kind of device, including：Multiple first BioFET, each described first BioFET includes：Active area, between source area and drain region and below grid structure, the active area includes raceway groove Area and the first process layer, and the channel region abuts the grid structure；And dielectric layer, it is arranged on first process layer On the side relative with the channel region；Wherein, first process layer includes the first dopant of the first concentration；And it is multiple 2nd BioFET, each 2nd BioFET includes：Active area, between source area and drain region and grid structure Lower section, the active area includes channel region and second processing layer, and the channel region abuts the grid structure；And dielectric On layer, the side relative with the channel region for being arranged on the second processing layer；Wherein, the second processing layer includes second Second dopant of concentration.

In the device, the first BioFET is n-type transistor, and second dopant is hydrogen, and described 2nd BioFET is p-type transistor, and second dopant is boron.

Brief description of the drawings

When being read out with reference to accompanying drawing, many aspects of the present invention are best understood by described further below.Should This is, it is emphasized that standard practices in industry, a variety of parts are not necessarily to scale.In fact, clear for discussion For the sake of, the size of a variety of parts can be increasedd or decreased arbitrarily.

Fig. 1 is the sectional view of the embodiment of the BioFET device of the one or more aspects according to the present invention.

Fig. 2A and Fig. 2 B are a variety of implementations of the method for the one or more aspects manufacture BioFET device according to the present invention The flow chart of example.

Fig. 3 to Figure 14 is the sectional view of the various embodiments of the BioFET device constructed according to the present invention.

Embodiment

It should be understood that the following content of the invention provides the multiple not be the same as Examples or reality of the different characteristic for realizing the present invention Example.The particular instance of part and arrangement is described below, to simplify the present invention.Certainly, these are only example and are not used in progress Limit.Moreover, the first component formation in description below above second component or on can include side directly to contact The first component of formula formation and the embodiment of second component, and can also include being formed between first component and second Additional component between part so that the embodiment that first component and second component can be not directly contacted with.Moreover, mentioned is all Relational terms such as " top ", " above ", " bottom " and " back side " are used to provide the relativeness between element and be not intended to Imply any absolute direction.For brevity and clarity, a variety of parts can be arbitrarily drawn according to different proportion.

In BioFET, by the biology or biochemistry compatible layer of the probe molecule of the fixation as surface receptor or Biological function layer replaces MOSFET（Mos field effect transistor）Grid, so as to control its source contact The electric conductivity of semiconductor between part and drain contacts.Substantially, BioFET is the field-effect life with semiconductor transducer Thing sensor.BioFET advantage is with unmarked operation（label-free operation）Prospect.BioFET's makes With costly and time-consuming marking operation is avoided, such as, pass through fluorescence or radioactive probe labelled analyte.

Target biological molecules or biological entities engage to adjust with grid or the acceptor molecule being fixed on BioFET grid Save BioFET electric conductivity.When target biological molecules or biological entities are engaged on grid or sessile receptor, pass through grid Potential changes BioFET leakage current, and it depends on the type and quantity of engaged target.The change of leakage current can be carried out The engagement for measuring and being used between determining acceptor and target biological molecules or biomolecule in itself（bonding）Type sum Amount.A variety of acceptors can be used for functionalization（functionalize）BioFET grid, such as ion, enzyme, antibody, part, by Body, peptide, oligonucleotides, organ cell, organism and tissue fragment.For example, in order to detect ssDNA（Single-stranded deoxyribose Nucleic acid）, can be by fixed complementation ssDNA chains come functionalization BioFET grid.Moreover, in order to detect such as tumor markers Multiple proteins, can be by monoclonal antibody come functionalization BioFET grid.

One example of biology sensor has the sensing surface at the top of the floating boom as the grid for being connected to BioFET. Floating boom passes through metal interconnecting wires and through hole（Or multilayer interconnection part, MLI）Lamination be connected to BioFET grid structure.Gate electrode The various metals layer of top also can result in being damaged by antenna effect during MLI formation process.In such BioFET, Finally（Top）Current potential regulation reaction occurs at the outer surface of metal level or the dielectric surface formed on MLI top, and And sense current potential regulation reaction indirectly by BioFET.Because the parasitic capacitance related to MLI, the sensitivity of device is low In other biological sensor.As a result, sensing board size is generally designated so that can occur sufficient detectable quantity on sensing plate Current potential regulation reaction.Minimum sensing board size correspondingly limits BioFET density.

In another example, biomolecule is bonded to BioFET grid or gate-dielectric directly or through acceptor On.These " directly sense " BioFET and target biological molecules are directly sensed in the case of parasitic capacitance not related to MLI. Its detailing requiments removes the MLI materials above BioFET to form sensing trap, and is exposed to gate electrode or gate-dielectric In the jet environment for occurring current potential regulation surface reaction.These BioFET are more sensitive than floating gate type, but are due to a variety of originals Cause, constructs these BioFET challenging.The sensing trap being etched has high aspect ratio, for example, more than 30, so generally logical Excess energy plasma etching performs the etching.The high aspect ratio of sensing trap also limits the profile for the sensing trap being etched. Due to the infringement produced by electric charge, high energy plasma etching may damage gate electrode.Attempt to reduce the height for sensing trap in length and breadth Than so that etching is more prone to cause that the quantity of metal level is restricted into one or two metal levels.The reduction of metal level limits device The interconnection wiring of part and integrated option, for example, the number amount and type of the circuit for controlling BioFET.Because misalignment may be sudden and violent Reveal metals of the MLI around sensing trap, or cause to sense the area that surface area is less than design, technique is also very quick to being aligned Sense.

In another example, biomolecule is placed close to the grid on the back side of substrate.In this example, by that will serve as a contrast The back side at bottom forms grid and sensing surface as jet grid on the back side of channel region.The example avoids having to etching The difficult higher sensitive to have than floating boom biology sensor of biomolecule is placed through multilayer interconnection part and close to grid Degree.The BioFET of the type is referred to as back side sensing（BSS）BioFET.The various embodiments of the present invention are related to BSS BioFET, It includes doping concentration gradient in the active area below the grid between source electrode and drain electrode and/or close to jet grid The surface treatment of surfaces of active regions.Such doping concentration gradient allows BSS BioFET electrical characteristics to adjust.Active area includes Close to the process layer and channel region of jet grid.Doping concentration gradient can be by by the dopant of different conduction-types from ditch The remainder in road area is added to the process layer of channel region or by deactivating the dopant in the thin process layer in channel region Lightly-doped layer or depletion layer that property is formed.Surface treatment, which is additionally included under oxygen or hydrogen environment, is annealed.

Fig. 1 is back side sensing（BSS）BioFET100 schematic diagram.Semiconductor devices 100 includes being formed on substrate 114 Grid structure 102.Grid structure 102 is the backgate for BSS BioFET.Substrate 114 further comprises source area 104, leakage Polar region 106 and the active area 108 between source area 104 and drain region 106（E.g., including channel region）.It can use Suitable CMOS process technologies formation grid structure 102, source area 104, drain region 106 and active area 108.Grid structure 102, Source area 104, drain region 106 and the formation of active area 108 FET.Active area 108 close to the part at the back side be process layer 107, So as to being the channel layer or depletion layer being lightly doped.Process layer 107 can be included in the remainder of active area 108 not The dopant found.For example, for n-MOS, arsenic or phosphorus doping process layer 107 can be used.For p-MOS, it can be adulterated with boron Process layer 107.Process layer 107 can include tending to make the neutralize material of dopant deactivation, for example, making boron deactivation Hydrogen.Dangling bonds can be repaired by annealing or are reduced and introduce the plasma of defect to form process layer 107.In oxygen or ozone Oxygen atmosphere in annealing can repair dangling bonds.Annealing in the nitrogen atmosphere of hydrogen or deuterium can reduce removable ion and interface trap To prevent infringement caused by plasma.

Compared with grid structure 102, separation layer 110 is arranged on the opposite side of substrate 114.Separation layer 110 can be exhausted Silicon on edge body（SOI）The buried oxide of substrate（BOX）Layer.Opening in separation layer 110 is aligned substantially with active area 108. The back side upper dielectric layer 124 of active area 108 is arranged on the bottom of opening.Dielectric layer 124 is used as the grid for jet grid Dielectric, and surface and source electrode and the drain electrode of covering treatment layer 107（106/104）Any of the covering of layer 110 is not isolated Part.

In certain embodiments, metal crown structure 126 is arranged on the top of dielectric layer 124 and covering isolation at least in part The side wall of layer 110.When using metal crown structure 126, the metal crown structure 126 is to be used for detectable biomolecule or biological entities Sensing surface.The area of metal crown structure 126 is more than dielectric layer 124, and it is possible thereby to accommodates more potential regulating reactions. In certain embodiments, metal crown structure 126 is extended to above the top corner of the opening in separation layer 110, and part Ground covers separation layer 110.In a particular embodiment, engaged in metal crown structure 126 or amplify multiple acceptors, be used for providing The position of detectable biomolecule or biological entities.In other embodiments, the surface of metal crown structure 126 is used for having specific parent Metal material is joined to the biomolecule or biological entities 128 of power.Metal-containing material for metal crown structure 126 includes Tantalum, tantalum nitride, niobium, tungsten nitride, ruthenium-oxide or combinations thereof.Other metals including gold and platinum can also be used.According to one A little embodiments, the material for metal crown structure 126 is ohmic metal（ohmic metal）.Semiconductor devices 100 include via Metal crown structure 126 and the electric contact piece of source area 106, drain region, grid structure 102 and grid（It is not shown）.If no Using metal crown structure 126, then dielectric layer 124 is to provide the boundary layer of the junction of acceptor.

Therefore, although sensor FET controls the semiconductor between source electrode and drain electrode using gate contact（For example, ditch Road）Electric conductivity, but semiconductor devices 100 allows to be formed the acceptor control electric conductivity on the back side of FET device, and grid Structure 102（For example, polysilicon）As backgate（For example, source-substrate or body node in tradition FET）.Backgate can not have Channel electrons distribution is controlled in the case of bulk substrate effect.Therefore, if acceptor on attaching molecules to jet grid, change Become the impedance of field-effect transistor channel region.It can also make grid that there is bias.On close to metal crown structure or on boundary layer Sensing surface position positive wall jet gate electrode.Therefore, semiconductor devices 100 can be used for detection included in fluidic architecture The one or more specific biological molecules or biological entities analyzed in substance environment 130 in 132.

By the way that dopant is added in the process layer 107 of the lower section of dielectric layer 124, BioFET100 performance can be adjusted. According to multiple embodiments, when process layer 107 is lightly-doped layer or depletion layer, can make BioFET100 to be joined to acceptor or The molecule of grid is more sensitive.In other words, on the BioFET without process layer 107, it can increase for grid voltage Leakage current.In certain embodiments, process layer 107, which is provided, can avoid or reduce the bigger band gap of current leakage.

Semiconductor devices 100 can include additional passive component, such as, resistor, capacitor, inductor and/or fuse； And other active parts, including P-channel field-effect transistor (PEFT) transistor（pFET）, N-channel field-effect transistor（nFET）, metal oxidation Thing semiconductor field effect transistor（MOSFET）, complementary metal oxide semiconductor（CMOS）Transistor, high voltage transistor and/or High frequency transistor.It will be further understood that additional component can be added in semiconductor device 100, and for semiconductor device The additional embodiment of part 100, some parts described below can be replaced or delete.

Fig. 2A is to be used to manufacture BSS biological field effect transistors（BioFET）Method 200 flow process chart.Method 200 include：Using with complementary metal oxide semiconductor（CMOS）Process compatible or complementary metal oxide semiconductor are peculiar One or more technological operations form BioFET.It should be understood that before and after, during method 200, can provide attached Plus step, and in different embodiments of the invention, some steps described below can be replaced or deleted.Moreover, should The understanding, the step of method 200 includes the feature with typical CMOS technology work flow, and only those steps are entered herein Row is briefly described.

Method 200 starts from operation 202, wherein there is provided substrate.Substrate is Semiconductor substrate.Semiconductor substrate can be Silicon substrate.Alternatively, substrate can include another elemental semiconductor, such as, germanium；Compound semiconductor, including carborundum, arsenic Change gallium, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide；Alloy semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP；Or combinations thereof.In various embodiments, substrate is semiconductor-on-insulator （SOI）Substrate.SOI substrate can include isolating by such as note oxygen（SIMOX）Technique and/or other appropriate process formed Buried oxide（BOX）Layer.Such as, substrate can be doped to p-type and n-type.As used herein, workpiece refers to lining Bottom and combination or any material being deposited thereon.Semiconductor substrate（Or device substrate）Refer in thereon and wherein composer The stock of part, and do not include the material of any deposition or engagement.Fig. 3 is what the part with substrate 302 was manufactured BioFET300 sectional view.In the example of fig. 3, substrate 302 is to include block silicon layer 304, oxide skin(coating) 306 and active The SOI substrate of layer 308.Oxide skin(coating) 306 can be buried oxide（BOX）Layer.In one embodiment, BOX layer is dioxy SiClx（SiO₂）.Active layer 308 can include silicon.Can suitably be adulterated active layer 308 with n-type and/or p-type dopant.

With reference to Fig. 2A, method 200 then advancees to operation 204, wherein, field-effect transistor is formed on substrate（FET）. FET can be n-type FET（nFET）Or p-type FET（pFET）.FET includes grid structure, source area, drain region and between source Channel region between polar region and drain region.For example, according to FET type, source/drain regions can include n-type dopant or p-type Dopant.Grid structure includes gate dielectric, gate electrode layer and/or other suitable layers.In certain embodiments, gate electrode is Polysilicon.Other gate electrodes include metal gate electrode, and the metal gate electrode includes such as Cu, W, Ti, Ta, Cr, Pt, Ag, Au The combination of material, similar TiN, TaN, NiSi, CoSi suitable metal compound or these conductive materials.In various embodiments In, gate-dielectric is silica.Other gate-dielectrics include silicon nitride, silicon oxynitride, with high-k（High k）'s Dielectric and/or combinations thereof.The example of high-g value includes hafnium silicate, hafnium oxide, zirconium oxide, aluminum oxide, five oxidations two Tantalum, hafnium oxide-aluminum oxide（HfO₂-Al₂O₃）Alloy or combinations thereof.Typical CMOS processes can be used to form FET, it is all Such as, photoetching；Ion implanting；Diffusion；Deposition, including PVD（PVD）, metal evaporation or sputtering, chemical vapor deposition （CVD）, plasma enhanced chemical vapor deposition（PECVD）, atmospheric pressure chemical vapor deposition（APCVD）, low pressure chemical vapor deposition（LPCVD）、 High-density plasma CVD（HDPCVD）, atomic layer CVD（ALCVD）, spin coating；Etching, including wet etching, dry ecthing and wait Plasma；And/or other suitable CMOS technologies.

Fig. 3 is the BioFET300 with substrate 302 of part manufacture sectional view.The BioFET300 of part manufacture includes Gate-dielectric 312, gate electrode 314, source/drain regions 316 and active area 319.Source/drain regions 316 and active area 319 Opposite types can be included（For example, n-type/p-type）Dopant.Gate electrode 314 is polysilicon gate or metal gates.Grid Dielectric 312 is gate oxide level（For example, SiO₂、HfO₂Or other high k metal oxides）.

Formed on substrate after FET, multilayer interconnection is formed on substrate（MLI）Structure.MLI structure can include leading Line, conductive through hole and/or intermediate dielectric layer（For example, interlayer dielectric（ILD））.MLI structure can be provided to the thing of transistor Reason and electrical connection.Wire can include copper, aluminium, tungsten, tantalum, titanium, nickel, cobalt, metal silicide, metal nitride, polysilicon, they Combination and/or potentially include one or more layers or lining（lining）Other materials.Middle or interlayer dielectric layer（Example Such as, ILD layer）Silica, fluorine doped silica glass can be included（FGS）、SILK（From Dow Chemical of Michigan's Product）、BLACK DIAMOND（By Applied Materials of Santa Clara, what California was provided）And/or Other insulating materials.Distinctive appropriate process in being manufactured by CMOS（Such as, CVD, PVD, ALD, plating, spin coating）With/ Or other techniques form MLI.

With reference to Fig. 3 example, MLI structure 318 is set on substrate 302.MLI structure 318 include by conductive through hole or The a plurality of wire 320 that connector 322 is connected.In one embodiment, wire 320 includes aluminium and/or copper.In one embodiment, Through hole 322 includes tungsten.In another embodiment, through hole 322 includes copper.Dielectric layer 324 is arranged on substrate 302, with including The conductive component of intervenient MLI structure 318.Dielectric layer 324 can be interlayer dielectric（ILD layer）Or inter-metal dielectric （IMD）Layer and/or be made up of multiple ILD or IMD sublayers.In one embodiment, dielectric layer 324 includes silica.MLI structure 318 provide the electrical connection to grid 314 and/or source/drain 316.

Referring again to Fig. 2A, in operation 206, opening is formed at the back side of substrate.Opening is to be arranged on the back of the body of substrate One on face or the groove formed in multilayer.Opening exposure substrate is positioned at grid grid and neighbouring FET channel region Region.The suitable photoetching process that pattern is provided on substrate can be used and material is removed until exposure FET device from the back side The etch process of body structure form opening.Suitable etch technique include wet etching, dry ecthing, plasma etching and/or Other appropriate process.

In certain embodiments, forming the details of opening manipulation includes Fig. 2 B flow chart and Fig. 4 to Figure 10 sectional view Shown multiple steps.In Fig. 2 B operation 252, carrier substrates are attached.As shown in figure 4, carrier substrates 402 are attached（Example Such as, engage）To device substrate 302.The front for the device substrate 302 carrier substrates 402 being attached to above MLI.In a reality Apply in example, carrier substrates are bonded to the passivation layer 404 formed on the ILD layer of MLI and/or substrate.Can use welding, Carrier substrates are attached to device substrate by diffusion, congruent melting, anode, polymer and/or other suitable method of attachment.Exemplary carrier Substrate includes silicon, glass and quartz.Carrier substrates 402 can include other functors, such as, interconnecting member, wafer engagement Position, the cavity being defined and/or other suitable components.With post-processing（For example, after thinning）Period, load can be removed Body substrate.

In Fig. 2 B operation 254, Semiconductor substrate is thinned.Use wet etching process, dry etching process, plasma Etch process, chemically mechanical polishing（CMP）Technique and/or other appropriate process for removing part semiconductor substrate, upset And device substrate is thinned.Suitable for making the exemplary etchant of substrate thinning include HNA（Hydrogen fluoride, nitrogen and acetic acid）, tetramethyl Base ammonium hydroxide（TMAH）, KOH, buffer oxide etch agent（BOE）And/or other suitable erosions with CMOS technology technical compatibility Carve agent.

In Figure 5, it is thinned device substrate so as to remove block silicon layer.In other embodiments, remove block silicon layer and Buried insulator layer.In multiple processing steps device substrate can be thinned, for example, the block silicon layer of SOI wafer is removed first, Then the buried insulator layer of SOI wafer is removed.In one embodiment, the first reduction process including the use of such as grinding, CMP, HNA, and/or TMAH etchings remove bulk silicon, and it stops at buried oxide layer.It can be carried out after first reduction process all Such as the second reduction process of BOE wet etchings, so as to remove buried oxide and stop at the silicon of active layer.Reduction process can To expose the active area of substrate.In one embodiment, exposure channel region（For example, the active area between source/drain regions With following grid structure）.After the thinning process, the thickness of substrate can be about 500 angstromsExtremelyFor example, In one embodiment, the thickness of the active layer of SOI substrate is between aboutWithBetween.

In other embodiments, as shown in figure 5, device substrate is thinned so that remove block silicon layer, and buried insulation At least a portion of layer retains on substrate.Such as CMP, HNA and/or TMAH etching can be used to perform the removal of bulk silicon, its Stop at buried insulator layer.After the thinning process, the thickness of substrate can be between about 500 angstromsExtremelyIt Between.For example, in one embodiment, the thickness of the active area of SOI substrate is between aboutWithBetween.Bury exhausted Edge layer（It there is presently provided the surface of substrate）Can be separation layer, and between aboutThickness between to several microns.

In Fig. 2 B operation 256, groove is formed on substrate, to expose and provide one or many with MLI structure The contact of individual conductive trace.Can by the photoetching process of patterned trench opening, then by it is suitable wet, dry or wait from Daughter etch process forms groove.In one embodiment, groove exposure MLI（For example, after formation of the gate structure, The first metal layer formed in MLI structure）Metal one（Metal 1）A part for layer.With reference to Fig. 6 example, especially through Active layer 308 etches groove 602, the bonding land on wire 320 to expose MLI structure 318.It is alternatively possible to pass through isolation Area 306（For example, oxide）Etch groove.

In Fig. 2 B operation 258, separation layer is formed on substrate.Separation layer can include dielectric material（Such as, aoxidize Thing or nitride）.In one embodiment, separation layer is silica.With reference to Fig. 7 A example, separation layer 702 is arranged on groove In the 602 and top of insulating barrier 306.In one embodiment, separation layer 702 is silica.As described above, in some implementations It is not square into separation layer on the insulating layer if removing the insulating barrier of SOI substrate during substrate thinning technique in example.Figure 7B includes forming the separation layer 702 in groove 602 and above the active layer 308 of SOI substrate.Such as, figure 8 below is to Figure 14 Show to remove the embodiment of BOX layer 306 as shown in Figure 7 B in substrate thinning technique.However, the teaching on these figures can To be equally applicable to all or part of BOX306（Hereinafter referred to as insulating barrier 306）Retain（As shown in Figure 7 A）Embodiment.

In Fig. 2 B operation 260, formed on separation layer 702 and pattern interconnection layer.The pattern in separation layer 702 Change and etch one or more openings, with the following metal of exposure or conductive region.Interconnection layer can be provided to the connection of MLI structure （For example, I/O connections）.Interconnection layer can provide the connection with transistor（For example, I/O connections）.Interconnection layer can include conduction Material, such as, copper, aluminium, combinations thereof and/or other suitable conductive materials.Interconnection layer can be provided as redistribution layer （RDL）Functor.It is patterned using metal deposit or coating technology formation interconnection layer and then.With reference to Fig. 8's Example, sets interconnection layer 802 on the insulating layer 702.Interconnection layer 802 can provide BioFET signal input/output and lead to Cross the connection of groove 602 and MLI.In one embodiment, interconnection layer 802 includes aluminium copper.

In Fig. 2 B operation 262, passivation layer is formed on the device substrate.Passivation layer can be with covering part interconnection layer.It is blunt Changing layer can include that fastener can be formed（For example, I/O）Opening.In one embodiment, passivation layer includes silica, However, other compositions are possible.Passivation layer goes for providing device（For example, interconnection layer）Include moisture protection.Ginseng Fig. 9 example is examined, on substrate（It is included on interconnection layer 802）Form passivation layer 902.Passivation layer 902 includes opening 904, its In, fastener（For example, bonding wire, projection）Connection with device 300 can be provided（For example, I/O connections）.In other words, Opening 904 can expose conductive I/O pads.

In Fig. 2 B operation 264, opening is formed on the back side of substrate.Form opening so that expose the active of substrate Area is located at transistor arrangement（For example, channel region）A part for lower section.Opening is aligned substantially with the active area of transistor, and can To be aligned with back gate structure 312/314.Can by suitable photoetching process, then by dry ecthing, wet etching, etc. Plasma and/or the etch process of combinations thereof form opening.In certain embodiments, formed and opened in the isolation layer Mouthful.In other embodiments, exist（SOI substrate）Opening is formed in buried insulator layer.With reference to Fig. 9, provided in separation layer 702 Opening 906.Opening 906 exposes a part for active layer 308.Specifically, active area 319 and part source/drain can be exposed Area 316.

Referring again to Fig. 2A, in operation 207, the exposure substrate area in processing opening.Processing includes injection technology, expansion At least one in day labor skill and annealing process.Dopant is embedded in the surface of substrate by injection technology.Pass through injection technology Energy come control injection depth.The concentration of dopant in substrate depends on the dosage of injection.With reference to Figure 10, injection technology Process layer 1002 is produced at the bottom surface of opening 906, it is located at the remainder of the subjacent of opening 906 than active area 319 With overall lower net doping thing concentration.In order to realize overall lower concentration of dopant, inject opposite with active area 319 The dopant of conduction type.For n-type MOS, injection arsenic or phosphorus.For p-type MOS, boron is injected.Because these dopants have with The opposite conduction type of active area 319, so overall net doping thing concentration is reduced at the surface of active area 319.Then, with having The remainder of source region is compared, and process layer is the channel layer being lightly doped.If the enough dopants of injection, process layer is to exhaust Layer.Relatively low energy injection technique can be used for dopant being limited in superficial layer.For example, Implantation Energy can be less than about 10keV or less than about 15keV.If active area 319 is sufficiently thick and manufactures larger process layer, higher energy can be used Amount.According to various embodiments, process layer has about 5 angstroms or hundreds of angstroms of peak concentration since surface.The thickness of process layer can With between about 10 nanometers to hundreds of nanometers.

Directly injection technology can be implemented to substrate or by mask.Can first by deposit sacrificial oxides layer come Injecting mask is formed, then, the opening for injection is patterned to form to sacrificial oxide layer.It can be opened by being formed The operation 206 of mouth 906 performs mask generation.In certain embodiments, opening 906 is more than injection opening.For example, process layer 1002 Extend to a part for source/drain regions 316 or be limited to the surface of active area 319.

In certain embodiments, insulating barrier 306 and passivation layer 902 are enough the other parts that block dopant is embedded in BioFET In.In one embodiment, Fig. 2 B operation 262 is performed in the case where not forming opening 904, to prevent from being injected into interconnection layer In 802.In these embodiments, after injection it, the opening 904,906 formed in passivation layer 902.

After injection it, substrate is annealed, to activate dopant.Same amount does not anneal to swash for different dopant requirements It is living.The rate activation that lower temperature is annealed to reduce.Because after MLI318 and interconnection layer 802 is formed, occurring activation annealing, So the stability and pollution and activation rate holding balance of the metal material in device.In certain embodiments, forming mutual Even before layer 802, injection and activation annealing are performed.Activation can be performed under conditions of about 400 degrees Celsius, about 450 degrees Celsius Annealing, and 500 degrees Celsius can be less than about.In certain embodiments, dopant is activated using laser.Because laser energy Amount can be focused at the surface of substrate, and the duration of laser explosure is very short, is usually shorter than 1 microsecond, can not have In the case of having the obvious adverse effect to deeper MLI318, laser active is performed.In one embodiment, laser beam flying Tube core.In another embodiment, laser beam is adjusted to the size with the dopant for being enough once to activate a tube core.

It is alternatively possible to tend to make the dopant of the main dopant deactivation of active area 319 by addition to be formed Process layer 1002.In nMOS examples, because hydrogen can make boron deactivation, it is possible to add hydrogen, to produce process layer 1002. Hydrogen can be injected as arsenic, phosphorus and boron.Hydrogen can also be added by diffusion technique.A kind of diffusion technique is related under hydrogen environment Annealed（Hydrogen/deuterium forms gas）Or apply hydrogen plasma to surface.Another diffusion technique is related to The dielectric layer of deposition of heavily doped in the opening 906 of the top of active area 319, and then the hydrogen of doping is annealed to be diffused into In silicon.The dielectric layer of heavy doping can be silica or silicon nitride film.After diffusion annealing, dielectric layer is removed.

, can be by being moved back in oxygen or ozone environment in addition to the injection for forming process layer 1002 and method of diffusion Fire forms process layer 1002.Annealing is repaired as the dangling bonds produced by plasma process.In the oxygen environment of oxygen or ozone Dangling bonds are repaired in annealing.Process layer 1002 can also be formed by being annealed in hydrogen environment.In the hydrogen environment of hydrogen or deuterium Annealing removable ion is reduced to prevent the infringement produced by plasma.For reducing the annealing of removable ion than above-mentioned Diffusion annealing has lower temperature, and the annealing and diffusion annealing for reducing removable ion can be combined into a step Suddenly.

Process layer 1002 allows BSS BioFET electrical property to adjust.When process layer 1002 is lightly-doped layer or depletion layer When, BSS BioFET can be more sensitive to being bonded to the molecule of acceptor, to improve BSS BioFET mutual conductance.In other words, On the BioFET without process layer 1002, the leakage current for grid voltage can increase.In certain embodiments, process layer 1002 offers can avoid or reduce the larger band gap of current leakage.In certain embodiments, process layer 1002 is included than not locating The less defect of layer is managed, and can be reduced as the device noise caused by removable ion and interface charge.By changing shape Into the technique of process layer, multiple BioFET on identity unit can be adjusted to have not for identical or different biological entities Same sensitivity.For example, some BioFET can have the process layer that the first dopant is the first concentration, and other BioFET There can be the process layer that the second dopant is the second concentration.Different disposal layer allows BioFET differently to detect target.Pass through Using different masks and independent lithography step, the process layer of more than one type can be formed on a device.

Referring again to Fig. 2A, in operation 208, dielectric layer is formed in the opening.Grid structure of the dielectric layer formation in FET On the exposure substrate of top, and the whole bottom of the opening 906 of the top of covering treatment layer 1002.Exemplary dielectric materials include Height-k dielectric film, metal oxide and/or other suitable materials.The instantiation of dielectric material includes HfO₂、Ta₂O₅、 Au₂O₃、WO₃, Pt oxide, Ti oxide, Al oxide and Cu oxide and such as SiO₂、Si₃O₄、Al₂O₃、 TiO₂、TiN、SnO、SnO₂Other dielectrics etc..Such as chemical vapor deposition can be used（CVD）, plasma enhancing Chemical vapor deposition（PECVD）, atmospheric pressure chemical vapor deposition（APCVD）, low pressure chemical vapor deposition（LPCVD）, high-density plasma CVD （HDPCVD）Or atomic layer CVD（ALCVD）To form dielectric layer.In certain embodiments, dielectric layer includes multilayer.For example, being situated between Electric layer can be included in the hafnium oxide layer above aluminum oxide or titanium oxide layer.In Figure 11 example, in active layer 319 and portion Divide source electrode and the top of drain electrode 316 that dielectric layers 1102 are set.Dielectric layer 1102 can be patterned to be aligned with grid structure （For example, being configured and patterning to be only remained in opening 906 to it）.

Referring again to Fig. 2A, can be in selection operation 210, deposited metal layer.Metal level can be metal element, metal alloy Or conductive metallic compound.Suitable element metal include tantalum, niobium, tungsten, ruthenium, aluminium, zirconium, vanadium, titanium, cobalt, molybdenum, osmium, chromium, rhodium, gold, Palladium, rhenium, nickel or other transition metal generally used in semiconductor processes.Metallic compound includes these transition metal member Conductive nitride, silicide and the oxide of element, for example, tungsten nitride, tantalum nitride and ruthenium-oxide.Metal level can be two layers or The composite bed of more layers.For example, metal level can include nitride and ruthenium-oxide.

Metal level be conformally deposited above substrate and be open in cover boundary layer.PVD can be used（Sputtering）、 Metallochemistry gas deposition（MCVD）, atomic layer CVD（ALCVD）, consistent with crystal seed layer electrochemical deposition or electroless deposition Carry out deposited metal layer.In certain embodiments, ion beam depositing can be used, is optionally sunk in the opening and around opening Product metal level.

Metal crown structure can be patterned to form to metal level in selection operation 212.In certain embodiments, scheme Case is related to by etching to remove the unnecessary portion of the metal level deposited in operation 210.Deposition etch mask first And be patterned.Etching mask can be the photoresist or hard mask patterned by photoetching process.At other In embodiment, Other substrate materials are first deposited upon on substrate and are patterned, and are removed after deposited metal layer Other substrate materials.Stripping photolithography glue material also removes any upper metal layer.When the plasma for being related to removal metal pattern When dry ecthing will cause plasma to the undesirable amount of infringement on other exposing metal surfaces, lift-off technology is probably useful 's.Because the photoresist in stripping technology, institute can be removed only by wet etching or including low-power plasma etching Metal pattern technology is better than with stripping technology sometimes.However, stripping technology has the possibility for producing more multi-pollutant, and institute The shape of obtained metal crown structure potentially includes jagged edges.

In Figure 12 example, the upper metal of dielectric layer 1102 hat structure 1202 is arranged on opening and neutralized around opening.Such as Shown in figure, metal crown structure 1202 includes the lip overlapping with part separation layer 702.In certain embodiments, all metals Structure 1202 is preced with all in Figure 11 opening 906.In other embodiments, as shown in figure 12, dielectric layer 1102 and metal crown knot Structure 1202 takes（consume）The volume of opening.

Referring again to Fig. 2A, in operation 214, microjet raceway groove or trap are set on the device substrate.Jet raceway groove is limited The region for the metal crown superstructure that analyte flows through.Can be by using SU-8（Epoxy bears photoresist）Photoetching, wafer connects Conjunction method and/or other appropriate methods form jet raceway groove.With reference to Figure 13 example, jet raceway groove is set on substrate 1302.Jet raceway groove 1302 provides the trap 1304 of the top of metal crown structure 1202.

Referring again to Fig. 2A, in operation 216, acceptor or processing film are set in metal crown structure.Acceptor can be wrapped Include enzyme, antibody, part（ligand）, protein, peptide, nucleotides and their part.Acceptor can be disposed on The native protein or enzyme of modification on one end are to detect specific analyte.The other end of acceptor is configured to be bonded to gold Category hat structure or another molecule/processing film for being bonded to metal crown structure.As shown in figure 14, in metal crown structure 1202 Multiple acceptors 1402 are set.By using metal crown structure, larger surface region can be used for the acceptor of engagement, and therefore more Position can be used for biomolecule or biological entities to detect.If without using metal crown structure, acceptor can be directly or through Another molecule/processing film is arranged on dielectric layer 1102.In certain embodiments, before operation 214, behaviour can be performed Make 216.

Fig. 2 B embodiment is related to many aspects of the present invention, wherein, on the identical side that substrate is connected with jet Make the electrical connection of BioFET device.The invention further relates to be connected on relative side to make BioFET device with jet in substrate Electrical connection embodiment.In those embodiments, before engagement carrier substrates and thinned device substrate, in substrate just The electrode and pad being connected with MLI are formed on face.The back side does not form groove 602.

During the operation of BioFET device, the solution for including target molecule is provided in jet raceway groove.BioFET device The different zones for being used for handling target molecule can be included.The dissolving of some biological material cells, separation, dyeing can be made, and Using chemistry, electrically or optically device is otherwise tested or analyzed.For example, drop of blood can be added in entrance simultaneously And initially-separate is carried out by plasma and cell type.Some of drop of blood cell can be dissolved by cell.Lysate In some macromoleculars can further be destroyed, for the downstream analysis thing in flow path.Can be by enzyme reaction, to target The limitation or trimming of chain makes DNA（DNA）Molecule fragment.

It is processed into by biomaterial after target, mesh is detected by flowing through the microjet raceway groove and trap that include BioFET Mark.If using dielectric layer 1102 or metal crown structure 1202, dielectric layer 1102 or metal crown structure 1202 are BioFET Sense surface.Can be with controlling stream so that compared with the reaction time, when there is sensing surface, target has long residence time. In some embodiments, while BioFET electric current is flowed through in collection, change one or more gate bias.Collect and analyze and come from BioFET power information.

In various embodiments, CMOS manufactures instrument（For example, casting）Implementing according to multiple for related device can be processed The method of example is until forming jet raceway groove.In one embodiment, subsequent user can to provide Surface-micromachining process, ion molten Liquid, acceptor etc..

In a word, method disclosed herein and device provide what is manufactured using CMOS and/or CMOS compatible technologies BioFET.Disclosed BioFET some embodiments can be used in biological and/or medical application, including be related to liquid, life One line application of thing entity and/or reactant.A kind of detection mechanism of some embodiments specifically described herein includes：Due to target Biomolecule or biological entities are bonded to jet grid structure or setting（For example, fixed）In the jet grid structure of device On the BioFET FET electric conductivity adjustment that is carried out of acceptor molecule.

BioFET some embodiments are arranged in the form of an array.Can silicon on insulator（SOI）Grid is constructed on substrate Structure.This can provide the advantage of high speed operation and/or less power consumption in certain embodiments.Setting is provided on soi substrates Inverted transistor can realize improved manufacture uniformity, with improved technology controlling and process, and increase BioFET density. For example due to the formation in SOI substrate, some embodiments can be provided for improved short-channel effect.Miscellaneous part include compared with Low current leakage, lower power consumption and the relatively low device noise from irradiation process.

It should therefore be understood that in one embodiment, describing a kind of BioFET, it includes substrate；Transistor arrangement, Include the process layer in active area close to channel region in the substrate；Separation layer is relative with the grid structure of transistor in substrate Side on have opening；And dielectric layer, in opening.Transistor arrangement have source area, drain region and including The grid structure of the active region of channel region and process layer.

An aspect of of the present present invention, which is related to, provides a kind of semiconductor devices of the array including BioFET device.In array More than one BioFET and more than second BioFET are included between source area and drain region and below grid structure Active area.Active area includes the channel region and process layer of adjacent gate structures.Process layer tool in more than first BioFET device There is the first dopant of the first concentration.Process layer in more than second BioFET device has the second dopant of the second concentration. More than first BioFET device and more than second BioFET device also include the side for being arranged on the process layer relative with channel region On dielectric layer.

Another aspect of the present invention is related to a kind of method for manufacturing BioFET device, including：Formed on a semiconductor substrate Transistor；Opening is etched in the separation layer being arranged in the second side of Semiconductor substrate, wherein, opening exposed transistor Active area；By the bottom of opening, in the active area that dopant is embedded in transistor, to form process layer；And in process layer Upper dielectric layer.Hydrogen can be injected by injecting the dopant with the electric conductivity opposite with the dopant in channel region, and And carry out the one or more dopants of annealing diffusion to realize insertion by the sacrifice layer to heavy doping.This method can also include Semiconductor substrate is annealed under oxygen or hydrogen environment.

When describing one or more of these embodiments, the present invention can provide multiple excellent better than existing device Point.During advantages below or benefit is discussed, it should be noted that there may be these benefits and/or result in certain embodiments, It is not required that these benefits and/or result.The advantage of some embodiments of the present invention includes providing user customizable product Ability.For example, jet raceway groove is formed, acceptor is introduced etc. can be performed by user.It is used as one or more realities described herein Another example of the advantage of example is applied, in traditional devices, usually requires that high aspect ratio technique to form bio-compatible interface（Example Such as, it is desirable to from the front-side etch of substrate to grid structure）.Because this method provides being processed to the back side of thinned wafer, So aspect ratio can be reduced.

Claims (19)

1. a kind of biological field effect transistor BioFET device, including：

Substrate；

Transistor arrangement, has the grid structure positioned at source area, drain region and active region in the substrate, described Active area includes channel region and process layer, and the process layer includes that doping type is opposite with the dopant in the channel region mixes Debris；

Separation layer, on the side relative with the grid structure of the substrate, the separation layer is in the transistor junction There is opening at the active area of structure；And

Dielectric layer, in the opening.

2. BioFET device according to claim 1, wherein, the process layer is lightly-doped layer.

3. BioFET device according to claim 1, wherein, the process layer includes hydrogen.

4. BioFET device according to claim 1, further comprises：Metal crown structure, above the separation layer And the side wall of the opening is covered at least in part.

5. BioFET device according to claim 1, wherein, the dielectric layer include aluminum oxide, titanium oxide, hafnium oxide, Tantalum oxide, tin oxide or combinations thereof.

6. BioFET device according to claim 1, further comprises：

It is arranged on the jet raceway groove on the separation layer.

7. BioFET device according to claim 1, further comprises：

Multilayer interconnection part MLI, be arranged in the substrate substrate with the grid structure identical side.

8. BioFET device according to claim 7, wherein, via the passivation layer above the MLI, carrier substrates are connect It is bonded on the substrate.

9. a kind of method for manufacturing BioFET device, including：

Transistor is formed on a semiconductor substrate, wherein, the transistor includes being formed in the first side of the Semiconductor substrate Grid structure on face and the active area between source area and drain region；

Opening, the opening exposure crystal are etched in the separation layer being arranged in the second side of the Semiconductor substrate The active area of pipe；

By the bottom of the opening, dopant is embedded in the active area of the transistor to form process layer, the processing Layer includes the doping type dopant opposite with the dopant in the active area；And

The dielectric layer in the process layer.

10. method according to claim 9, wherein, the embedded dopant includes：

Inject the electric conductivity dopant opposite with the dopant in the active area.

11. method according to claim 10, wherein, the embedded dopant further comprises：

Form injecting mask；

Activate the dopant；And

Remove the injecting mask.

12. method according to claim 9, wherein, the embedded dopant includes：

When the transistor is n-type transistor, injection hydrogen or deuterium.

13. method according to claim 9, wherein, the embedded dopant includes：

The sacrificial dielectric of heavy doping is formed in said opening；

Dopant is set to diffuse to the active area from the sacrificial dielectric；And

Remove the sacrificial dielectric.

14. method according to claim 10, further comprises：

The Semiconductor substrate is annealed in oxygen environment, or to the Semiconductor substrate in the hydrogen environment of hydrogen/deuterium Annealed.

15. method according to claim 9, further comprises：

The Semiconductor substrate is thinned；And

The layer deposited isolating in the second side of the Semiconductor substrate.

16. method according to claim 15, wherein, the Semiconductor substrate is SOI substrate, and described is thinned at least Partly remove buried oxide layer.

17. method according to claim 9, further comprises：

In dielectric layer formation metal crown structure, a part for the metal crown structure covers one of the separation layer Point；And

Engage acceptor in the metal crown structure, wherein, the acceptor be selected from by enzyme, antibody, part, peptide, nucleotides, The group that organ cell, organism and tissue fragment are constituted.

18. a kind of biological field field effect transistor devices, including：

Multiple first BioFET, each first BioFET includes：

First active area, between the first source area and the first drain region and below first grid structure, described first has Source region includes the first channel region and the first process layer, and first channel region abuts the first grid structure；With

First dielectric layer, is arranged on the side relative with first channel region of first process layer；

Wherein, first process layer includes doping type first concentration opposite with the dopant in first channel region First dopant；And

Multiple 2nd BioFET, each 2nd BioFET includes：

Second active area, between the second source area and the second drain region and below second grid structure, described second has Source region includes the second channel region and second processing layer, and second channel region abuts the second grid structure；With

On second dielectric layer, the side relative with second channel region for being arranged on the second processing layer；

Wherein, the second processing layer includes doping type second concentration opposite with the dopant in second channel region Second dopant.

19. device according to claim 18, wherein, the first BioFET is n-type transistor, and described first mixes Debris is hydrogen, and the 2nd BioFET is p-type transistor, and second dopant is boron.