CN104051512A - Backside sensing biofet with enhanced performance - Google Patents

Abstract

The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a substrate, a transistor structure having a treated layer adjacent to the channel region, an isolation layer, and a dielectric layer in an opening of the isolation layer on the treated layer. The dielectric layer and the treated layer are disposed on opposite side of the transistor from a gate structure. The treated layer may be a lightly doped channel layer or a depleted layer. The invention also provides a backside sensing BioFET with an enhanced performance.

Description

The back side sensing biological field effect transistor that performance strengthens

Related application

The priority of the 61/785th, No. 055 U.S. Provisional Patent Application that it is " Backside Sensing BioFET with Enhanced Performance " that the application requires in the title of submission on March 14th, 2013, its full content is hereby expressly incorporated by reference.

Technical field

The present invention relates to biology sensor and the method that is used to form biochip.The invention particularly relates to biochip having by biology sensor and fluidic hardware and forming method thereof.

Background technology

Biology sensor is the device for sensing and detectable biomolecule, and operates based on electronics, electrochemistry, optics and mechanical detection principle.Comprise that transistorized biology sensor is the transducer of the mechanical property of electric sense charge, photon and biological entities or biomolecule.Can pass through to survey biological entities or biomolecule itself, or carry out detection via the interaction between reactant and the biological entities/biomolecule of specifying and reaction.Can manufacture such biology sensor by semiconductor technology, this biology sensor switching electrical signals rapidly, and can easily be applied to integrated circuit (IC) and MEMS (micro electro mechanical system) (MEMS).

Biochip is in fact the small-size laboratory that can carry out hundreds and thousands of simultaneous biochemical reactions.Biochip can be surveyed specific biological molecules, measures their characteristic, processing signals and even can Direct Analysis data.Biochip makes researcher can take rapidly the large number of biological analyte of negligible amounts, for the multiple object of the detection from medical diagnosis on disease to bio-terrorism agent.Advanced biochip uses multiple biology sensors together with micro jetting technology, with integrated reaction, sensing and sampling management.BioFET(biological field effect transistor or biological organic field effect tube) be the biology sensor of a type, comprise the transistor of surveying biomolecule or biological entities for inductance.Although BioFET is favourable aspect a lot, but for example due to sensitivity and the resolution of the compatibility issue between semiconductor fabrication process, biologic applications, constraint to semiconductor fabrication process and/or restriction, the signal of telecommunication and biologic applications and/or process by realizing large-scale integrated (LSI) other challenges that produce, cause they manufacture and/or operation in produce challenge.

Summary of the invention

In order to solve existing defect in prior art, according to an aspect of the present invention, provide a kind of biological field effect transistor (BioFET) device, comprising: substrate; Transistor arrangement has the grid structure being positioned at above source area, drain region and active area in described substrate, and described active area comprises channel region and processing layer; Separator, is positioned on the side relative with described grid structure of described substrate, and described separator has opening at the described active area place of described transistor arrangement; And dielectric layer, be arranged in described opening.

In this BioFET device, described processing layer is lightly-doped layer.

In this BioFET device, described processing layer comprises the alloy that doping type is contrary with alloy in described channel region.

In this BioFET device, described processing layer comprises hydrogen.

This BioFET device further comprises: metal crown structure, is positioned at described separator top and covers at least in part the sidewall of described opening.

In this BioFET device, described dielectric layer comprises aluminium oxide, titanium oxide, hafnium oxide, tantalum oxide, tin oxide or their combination.

This BioFET device further comprises: be arranged on the jet raceway groove on described separator.

This BioFET device further comprises: multilayer interconnection part (MLI) is arranged on the side identical with described grid structure of described substrate in described substrate.

In this BioFET device, via the passivation layer of described MLI top, carrier substrates is engaged on described substrate.

According to a further aspect in the invention, a kind of method of the BioFET of manufacture device is provided, comprise: in Semiconductor substrate, form transistor, wherein, described transistor comprises grid structure on the first side that is formed on described Semiconductor substrate and the active area between source area and drain region; Etching openings in separator on the second side that is arranged on described Semiconductor substrate, described opening exposes described transistorized active area; By the bottom of described opening, alloy is embedded in described transistorized active area with formation processing layer; And on described processing layer dielectric layer.

In the method, embedding described alloy comprises: inject the conductivity alloy contrary with the alloy of described active area.

In the method, embedding described alloy further comprises: form injecting mask; Activate described alloy; And remove described injecting mask.

In the method, embed described alloy and comprise: in the time that described transistor is N-shaped transistor, hydrogen injecting or deuterium.

In the method, embedding described alloy comprises: in described opening, form heavily doped sacrificial dielectric; Make alloy diffuse to described active area from described sacrificial dielectric; And remove described sacrificial dielectric.

The method further comprises: in oxygen or hydrogen/deuterium environment, described Semiconductor substrate is annealed.

The method further comprises: Semiconductor substrate described in attenuate; And on the second side of described Semiconductor substrate layer deposited isolating.

In the method, described Semiconductor substrate is SOI substrate, and described attenuate is removed buried oxide layer at least in part.

The method further comprises: above described dielectric layer, form metal crown structure, a part for described metal crown structure covers a part for described separator; And engage acceptor in described metal crown structure, and wherein, the group that described acceptor selects free enzyme, antibody, part, acceptor, peptide, nucleotides, organ cell, organism and tissue fragment to form.

According to another aspect of the invention, a kind of device is provided, comprise: multiple BioFET, each described BioFET comprises: active area, between source area and drain region and below grid structure, described active area comprises channel region and the first processing layer, and described channel region is in abutting connection with described grid structure; And dielectric layer, be arranged on the side relative with described channel region of described the first processing layer; Wherein, described the first processing layer comprises the first alloy of the first concentration; And multiple the 2nd BioFET, each described the 2nd BioFET comprises: active area, and between source area and drain region and below grid structure, described active area comprises channel region and the second processing layer, and described channel region is in abutting connection with described grid structure; And dielectric layer, be arranged on the side relative with described channel region of described the second processing layer; Wherein, described the second processing layer comprises the second alloy of the second concentration.

In this device, a described BioFET is N-shaped transistor, and described the second alloy is hydrogen, and described the 2nd BioFET is p-type transistor, and described the second alloy is boron.

Brief description of the drawings

In the time reading by reference to the accompanying drawings, understand best many aspects of the present invention by following detailed description.Should be emphasized that, according to the standard practices in industry, multiple parts are not drawn in proportion.In fact, for discuss clear for the purpose of, the size of multiple parts can increase arbitrarily or reduce.

Fig. 1 is according to the sectional view of the embodiment of the BioFET device of one or more aspects of the present invention.

Fig. 2 A and Fig. 2 B are the flow charts that the various embodiments of the method for BioFET device is manufactured in one or more aspects according to the present invention.

Fig. 3 to Figure 14 is the sectional view of the various embodiments of the BioFET device of constructing according to the present invention.

Embodiment

Should be appreciated that, below summary of the invention be provided for realizing multiple different embodiment or the example of different characteristic of the present invention.The particular instance of parts and layout is below described, to simplify the present invention.Certainly, these are only that example and being not used in limits.And, first component in following specification be formed on second component top or on the first component that forms of the mode that can comprise directly contacting and the embodiment of second component, and can comprise the optional feature that can form between first component and second component, the embodiment that first component can directly not contacted with second component.And the mentioned relational terms such as " top ", " above ", " bottom " and " back side " is for providing the relativeness between element and not being intended to imply any absolute direction.For simple and clear for the purpose of, multiple parts can be drawn arbitrarily according to different proportion.

In BioFET, replace MOSFET(mos field effect transistor by the biology as the fixing probe molecule of surface receptor or biochemistry compatible layer or biological function layer) grid, thereby control the semi-conductive conductivity between its source electrode contact and drain contacts.In essence, BioFET is the Field effect transistor based Biosensor with semiconductor transducer.The advantage of BioFET is the prospect with unmarked operation (label-free operation).Expensive and marking operation consuming time have been avoided in the use of BioFET, such as, by fluorescence or radioactive probe labelled analyte.

Target biological molecules or biological entities and grid or be fixed on acceptor molecule on the grid of BioFET and engage to regulate the conductivity of BioFET.In the time that target biological molecules or biological entities are engaged on grid or sessile receptor, change the leakage current of BioFET by grid potential, it depends on the type and the quantity that are engaged target.The change of leakage current can be measured and for determining type and the quantity of the joint (bonding) between acceptor and target biological molecules or biomolecule itself.Multiple acceptor can be for the grid of functionalization (functionalize) BioFET, such as ion, enzyme, antibody, part, acceptor, peptide, oligonucleotides, organ cell, organism and tissue fragment.For example,, in order to survey ssDNA(single stranded deoxyribonucleic acid), can carry out by fixing complementary ssDNA chain the grid of functionalization BioFET.And, in order to survey the multiple proteins such as tumor markers, can carry out by monoclonal antibody the grid of functionalization BioFET.

An example of biology sensor has as the sensitive surface at top of floating boom of grid that is connected to BioFET.Floating boom is connected to the grid structure of BioFET by the lamination of metal interconnecting wires and through hole (or multilayer interconnection part, MLI).The various metals layer of gate electrode top also may cause being damaged by antenna effect during MLI forms technique.In such BioFET, there is current potential and regulate reaction in the outer surface of (top) metal level or the dielectric surface place that forms on the top of MLI in the end, and by BioFET indirectly this current potential of sensing regulate reaction.Because the parasitic capacitance relevant to MLI, so the sensitivity of device is lower than other biological transducer.As a result, generally designate sensory panel size, make the current potential that sufficient detectable quantity can occur on sensory panel regulate reaction.Minimum sensory panel size correspondingly limits BioFET density.

In another example, biomolecule directly or be engaged to by acceptor on the grid or gate-dielectric of BioFET.These " direct sensing " BioFET is not in the case of there is no direct sensing target biological molecules the parasitic capacitance relevant to MLI.Its structure requires MLI material of removing BioFET top to form sensing trap, and gate electrode or gate-dielectric is exposed to occur in jet environment that current potential regulates surface reaction.These BioFET are more responsive than floating boom type, but due to many reasons, construct these BioFET challenging.Etched sensing trap has high aspect ratio, for example, and more than 30, so conventionally carry out this etching by the etching of high-energy plasma body.The high aspect ratio of sensing trap also limits the profile of etched sensing trap.Due to the infringement that electric charge produces, the etching of high-energy plasma body may damage gate electrode.Trial reduce sensing trap high aspect ratio so that etching be more prone to cause by the restricted number of metal level to one or two metal levels.The minimizing of metal level has limited interconnection wiring and the integrated option of device, for example, and for controlling quantity and the type of circuit of BioFET.Because misalignment may expose the metal of MLI around sensing trap, or cause sensitive surface area to be less than the area of design, technique is also very responsive to aiming at.

In another example, the grid approaching on the back side of substrate is placed biomolecule.In this example, by using the back side of substrate as jet grid, on the back side of channel region, form grid and sensitive surface.This example has avoided necessary etching to place the difficulty of biomolecule to have higher sensitivity than floating boom biology sensor through multilayer interconnection part and next-door neighbour's grid.The BioFET of the type is called as back side sensing (BSS) BioFET.Various embodiments of the present invention relates to BSS BioFET, the surface treatment that it comprises the doping content gradient in the active area below the grid between source electrode and drain electrode and/or is close to the surfaces of active regions of jet grid.Such doping content gradient allows the electrical characteristics of BSS BioFET to regulate.Active area comprises processing layer and the channel region of next-door neighbour's jet grid.Doping content gradient can be lightly-doped layer or the depletion layer by the alloy of different conduction-types is added to the processing layer of channel region or forms by the alloy deactivation making in the thin processing layer channel region from the remainder of channel region.Surface treatment is also included under oxygen or hydrogen environment and anneals.

Fig. 1 is the schematic diagram of back side sensing (BSS) BioFET100.Semiconductor device 100 comprises the grid structure 102 being formed on substrate 114.Grid structure 102 is the back of the body grid for BSS BioFET.Substrate 114 for example further comprises source area 104, drain region 106 and the active area 108(between source area 104 and drain region 106, comprises channel region).Can use suitable CMOS process technology to form grid structure 102, source area 104, drain region 106 and active area 108.Grid structure 102, source area 104, drain region 106 and active area 108 form FET.The part that active area 108 is close to the back side is processing layer 107, thereby can be lightly doped channel layer or depletion layer.Processing layer 107 can be included in the alloy not finding in the remainder of active area 108.For example, for n-MOS, can be with arsenic or phosphorus doping processing layer 107.For p-MOS, can use boron doping treatment layer 107.Processing layer 107 can comprise tend to make alloy deactivation in and material, for example, make the hydrogen of boron deactivation.The plasma that can introduce by annealing defect to repair dangling bonds or minimizing carrys out formation processing layer 107.Annealing in the oxygen atmosphere of oxygen or ozone can be repaired dangling bonds.Annealing in the nitrogen atmosphere of hydrogen or deuterium can reduce removable ion and the infringement of interface trap to prevent that plasma from causing.

Compared with grid structure 102, separator 110 is arranged on the opposite side of substrate 114.Separator 110 can be buried oxide (BOX) layer of silicon-on-insulator (SOI) substrate.Opening in separator 110 is aimed at substantially with active area 108.Be arranged on the bottom of opening at the back side of active area 108 upper dielectric layer 124.Dielectric layer 124 use act on the gate-dielectric of jet grid, and cover the surface of processing layer 107 and source electrode and drain electrode (106/104) and be not isolated any parts that layer 110 covers.

In certain embodiments, metal crown structure 126 is arranged on dielectric layer 124 tops and covers at least in part the sidewall of separator 110.In the time using metal crown structure 126, this metal crown structure 126 is the sensitive surface for detectable biomolecule or biological entities.The area of metal crown structure 126 is greater than dielectric layer 124, and can hold thus more potential regulating reactions.In certain embodiments, metal crown structure 126 extends to above the top corner of the opening in separator 110, and partly covers separator 110.In a particular embodiment, in metal crown structure 126, engage or amplify multiple acceptors, to be provided for the position of detectable biomolecule or biological entities.In other embodiments, metal crown structure 126 surfaces are for joining biomolecule or the biological entities 128 with specific affinity to metal material.Metal-containing material for metal crown structure 126 comprises tantalum, tantalum nitride, niobium, tungsten nitride, ruthenium-oxide or their combination.Can also use other metals that comprise gold and platinum.According to some embodiment, are ohmic metal (ohmic metal) for the material of metal crown structure 126.Semiconductor device 100 comprises the electric contact piece (not shown) with source area 106, drain region, grid structure 102 and grid via metal crown structure 126.If do not use metal crown structure 126, dielectric layer 124 is to provide the boundary layer of the junction of acceptor.

Therefore, although transducer FET with gate contact part control source electrode and drain electrode between semiconductor (for example, raceway groove) conductivity, but semiconductor device 100 allows to be formed on the acceptor control conductivity on the back side of FET device, and grid structure 102(for example, polysilicon) for example, as back of the body grid (, source-substrate or the body node in traditional F ET).Back of the body grid can be controlled channel electrons and distribute in the situation that there is no bulk substrate effect.Therefore,, if molecule is attached to the acceptor on jet grid, change the impedance in fieldistor channel district.Can also make grid there is bias voltage.Sensitive surface in next-door neighbour's metal crown structure or on boundary layer is located positive wall jet gate electrode.Therefore, semiconductor device 100 can be contained in one or more specific biological molecules or the biological entities in the analyte environment 130 in fluidic architecture 132 for detection packet.

By alloy being added in the processing layer 107 of dielectric layer 124 belows, can regulate the performance of BioFET100.According to multiple embodiment, in the time that processing layer 107 is lightly-doped layer or depletion layer, can make BioFET100 more responsive to joining the molecule of acceptor or grid to.In other words,, about the BioFET that there is no processing layer 107, can increase the leakage current for grid voltage.In certain embodiments, processing layer 107 provides the more large band gap that can avoid or reduce current leakage.

Semiconductor device 100 can comprise additional passive parts, such as, resistor, capacitor, inductor and/or fuse; And other active parts, comprise P-channel field-effect transistor (PEFT) transistor (pFET), N slot field-effect transistor (nFET), mos field effect transistor (MOSFET), complementary metal oxide semiconductors (CMOS) (CMOS) transistor, high voltage transistor and/or high frequency transistor.Will be further understood that and can in semiconductor device 100, add optional feature, and for the additional embodiment of semiconductor device 100, parts more described below can be replaced or delete.

Fig. 2 A is the flow process chart for the manufacture of the method 200 of BSS biological field effect transistor (BioFET).Method 200 comprises: use with complementary metal oxide semiconductors (CMOS) (CMOS) process compatible or the distinctive one or more technological operations of complementary metal oxide semiconductors (CMOS) and form BioFET.Should be appreciated that, before and after, during method 200, can provide additional step, and in different embodiments of the invention, steps more described below can be replaced or be deleted.And, should be appreciated that, method 200 comprises the step of the feature with typical CMOS technology work flow, and herein only those steps be briefly described.

Method 200 starts from operating 202, wherein, provides substrate.Substrate is Semiconductor substrate.Semiconductor substrate can be silicon substrate.Alternatively, substrate can comprise another kind of elemental semiconductor, such as, germanium; Compound semiconductor, comprises carborundum, GaAs, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; Alloy semiconductor, comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; Or their combination.In various embodiments, substrate is semiconductor-on-insulator (SOI) substrate.SOI substrate can comprise by the technique such as note oxygen isolation (SIMOX) and/or buried oxide (BOX) layer that other appropriate process form.Such as, substrate can be doped to p-type and N-shaped.As used herein, workpiece refer to substrate and in conjunction with or any material of being deposited thereon.Semiconductor substrate (or device substrate) refers to the stock that and wherein builds device thereon, and does not comprise the material of any deposition or joint.Fig. 3 is the sectional view with the BioFET300 of the part manufacture of substrate 302.In the example of Fig. 3, substrate 302 is the SOI substrates that comprise block silicon layer 304, oxide skin(coating) 306 and active layer 308.Oxide skin(coating) 306 can be buried oxide (BOX) layer.In one embodiment, BOX layer is silicon dioxide (SiO ₂).Active layer 308 can comprise silicon.Can be with N-shaped and/or the p-type alloy active layer 308 that suitably adulterates.

With reference to figure 2A, then method 200 proceeds to operation 204, wherein, forms field-effect transistor (FET) on substrate.FET can be N-shaped FET(nFET) or p-type FET(pFET).FET comprises grid structure, source area, drain region and the channel region between source area and drain region.For example, according to the type of FET, source/drain regions can comprise N-shaped alloy or p-type alloy.Grid structure comprises gate dielectric, gate electrode layer and/or other suitable layers.In certain embodiments, gate electrode is polysilicon.Other gate electrodes comprise metal gate electrode, and this metal gate electrode comprises such as the suitable metal compound of the material of Cu, W, Ti, Ta, Cr, Pt, Ag, Au, similar TiN, TaN, NiSi, CoSi or the combination of these electric conducting materials.In various embodiments, gate-dielectric is silica.Other gate-dielectrics comprise silicon nitride, silicon oxynitride, have high-k (high dielectric k) and/or their combination.The example of high k material comprises hafnium silicate, hafnium oxide, zirconia, aluminium oxide, tantalum pentoxide, hafnium oxide-aluminium oxide (HfO ₂-Al ₂o ₃) alloy or their combination.Can use typical CMOS technique to form FET, such as, photoetching; Implantation; Diffusion; Deposition, comprise physical vapor deposition (PVD), metal evaporation or sputter, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high-density plasma CVD (HDPCVD), atomic layer CVD(ALCVD), spin coating; Etching, comprises wet etching, dry ecthing and plasma etching; And/or other suitable CMOS techniques.

Fig. 3 is the sectional view of the BioFET300 with substrate 302 of part manufacture.The BioFET300 that part is manufactured comprises gate-dielectric 312, gate electrode 314, source/drain regions 316 and active area 319.Source/drain regions 316 and active area 319 can comprise the alloy of opposite types (for example, N-shaped/p-type).Gate electrode 314 is polysilicon gate or metal gates.Gate-dielectric 312 is gate oxide level (for example, SiO ₂, HfO ₂or other high k metal oxides).

Form FET on substrate after, on substrate, form multilayer interconnection (MLI) structure.MLI structure can comprise wire, conductive through hole and/or intermediate dielectric layer (for example, interlayer dielectric (ILD)).MLI structure can be provided to transistorized physics and electrical connection.Wire can comprise copper, aluminium, tungsten, tantalum, titanium, nickel, cobalt, metal silicide, metal nitride, polysilicon, they combination and/or may comprise one or more layers or the other materials of lining (lining).Centre or interlayer dielectric layer are (for example, ILD layer) can comprise silicon dioxide, mix fluorine silex glass (FGS), SILK(is from the product of Dow Chemical of Michigan), BLACK DIAMOND(is by Applied Materials of Santa Clara, California provides) and/or other insulating material.Distinctive appropriate process in can manufacturing by CMOS (such as, CVD, PVD, ALD, plating, spin coating) and/or other techniques form MLI.

With reference to the example of figure 3, MLI structure 318 is set on substrate 302.MLI structure 318 comprises the many wires 320 that connect by conductive through hole or connector 322.In one embodiment, wire 320 comprises aluminium and/or copper.In one embodiment, through hole 322 comprises tungsten.In another embodiment, through hole 322 comprises copper.Dielectric layer 324 is arranged on substrate 302, to comprise the conductive component of intervenient MLI structure 318.Dielectric layer 324 can be interlayer dielectric (ILD layer) or intermetallic dielectric (IMD) layer and/or be made up of multiple ILD or IMD sublayer.In one embodiment, dielectric layer 324 comprises silica.MLI structure 318 is provided to the electrical connection of grid 314 and/or source/drain 316.

Refer again to Fig. 2 A, in operation 206, form opening at the back side of substrate.Opening is the groove forming on the back side that is arranged on substrate or multilayer.Opening expose substrate be positioned at grid grid and contiguous FET channel region region.Can form opening until expose the etch process of the body structure of FET device with the appropriate light carving technology of pattern being provided on substrate and removing material from the back side.Suitable etch technique comprises wet etching, dry ecthing, plasma etching and/or other appropriate process.

In certain embodiments, the details of formation opening operation comprises the multiple steps shown in the flow chart of Fig. 2 B and the sectional view of Fig. 4 to Figure 10.In the operation 252 of Fig. 2 B, attached carrier substrates.As shown in Figure 4, for example, by attached carrier substrates 402 (, engage) to device substrate 302.Carrier substrates 402 is attached to the front of the device substrate 302 of MLI top.In one embodiment, carrier substrates is engaged to the passivation layer 404 forming on the ILD of MLI and/or substrate layer.Can use welding, diffusion, congruent melting, anode, polymer and/or other proper engagement methods that carrier substrates is attached to device substrate.Exemplary carrier substrate comprises silicon, glass and quartz.Carrier substrates 402 can comprise other functors, such as, interconnecting member, wafer junction, limited cavity and/or other suitable components.For example, during processing (, after attenuate) subsequently, can remove carrier substrates.

In the operation 254 of Fig. 2 B, make Semiconductor substrate attenuate.Use wet etching process, dry etching process, plasma etch process, chemico-mechanical polishing (CMP) technique and/or for removing other appropriate process of part semiconductor substrate, upset and attenuate device substrate.Be applicable to make the exemplary etchant of substrate thinning comprise HNA(hydrogen fluoride, nitrogen and acetic acid), Tetramethylammonium hydroxide (TMAH), KOH, buffer oxide etch agent (BOE) and/or with other suitable etch agent of CMOS technology compatibility.

In Fig. 5, make device substrate attenuate, make to remove block silicon layer.In other embodiments, remove block silicon layer and buried insulator layer.In multiple processing steps, can make device substrate attenuate, for example, first remove the block silicon layer of SOI wafer, then remove the buried insulator layer of SOI wafer.In one embodiment, the first reduction process comprises for example grinding of use, CMP, HNA and/or TMAH etching removal bulk silicon, and it stops at buried oxide layer place.After the first reduction process, can carry out the second reduction process such as BOE wet etching, thereby remove buried oxide and stop at the silicon place of active layer.Reduction process can expose the active area of substrate.In one embodiment, expose channel region (for example, the active area between source/drain regions and below grid structure).After reduction process, the thickness of substrate can be approximately 500 dusts extremely for example, in one embodiment, the thickness of the active layer of SOI substrate is between approximately with between.

In other embodiments, as shown in Figure 5, make device substrate attenuate, make to remove block silicon layer, and at least a portion of buried insulator layer retains on substrate.Can use for example CMP, HNA and/or TMAH etching to carry out the removal of bulk silicon, it stops at buried insulator layer place.After reduction process, the thickness of substrate can be between approximately 500 dusts extremely between.For example, in one embodiment, the thickness of the active area of SOI substrate is between approximately with between.Buried insulator layer (surface of substrate is provided now) can be separator, and has between approximately the extremely thickness between several microns.

In the operation 256 of Fig. 2 B, on substrate, form groove, to expose and to provide and the contact of one or more conductive traces of MLI structure.Can pass through the photoetching process of patterning groove opening, then form groove by suitable wet, dry or plasma etch process.In one embodiment, groove for example exposes MLI(, forming after grid structure, the first metal layer forming in MLI structure) the part of metal one (metal 1) layer.With reference to the example of figure 6, particularly through active layer 308 etched trench 602, to expose the bonding land on the wire 320 of MLI structure 318.Alternatively, can be through isolated area 306(for example, oxide) etched trench.

In the operation 258 of Fig. 2 B, on substrate, form separator.Separator can comprise dielectric material (such as, oxide or nitride).In one embodiment, separator is silica.With reference to the example of figure 7A, separator 702 is arranged in groove 602 and insulating barrier 306 tops.In one embodiment, separator 702 is silicon dioxide.As mentioned above, in certain embodiments, if remove the insulating barrier of SOI substrate during substrate thinning technique, above insulating barrier, do not form separator.Fig. 7 B comprises and is formed in groove 602 and the separator 702 of active layer 308 tops of SOI substrate.Such as, below Fig. 8 to Figure 14 be illustrated in substrate thinning technique the embodiment that removes BOX layer 306 as shown in Figure 7 B.But, can similarly be applied to all or part of BOX306(about the instruction of these figure and after this be called insulating barrier 306) reservation (as shown in Figure 7 A) embodiment.

In the operation 260 of Fig. 2 B, on separator 702, form and patterning interconnection layer.The one or more openings of patterning and etching in separator 702, to expose metal or conductive region below.Interconnection layer can be provided to the connection (for example, I/O connects) of MLI structure.Interconnection layer can provide and transistorized connection (for example, I/O connects).Interconnection layer can comprise electric conducting material, such as, copper, aluminium, their combination and/or other suitable conductive material.Interconnection layer can be provided as the functor of redistribution layer (RDL).Use metal deposition or coating technology form interconnection layer and are then patterned.With reference to the example of figure 8, interconnection layer 802 is set on insulating barrier 702.Interconnection layer 802 can provide the signal I/O of BioFET and being connected by groove 602 and MLI.In one embodiment, interconnection layer 802 comprises aluminium copper.

In the operation 262 of Fig. 2 B, in device substrate, form passivation layer.Passivation layer can cover part interconnection layer.Passivation layer can comprise the opening that can form fastener (for example, I/O).In one embodiment, passivation layer comprises silicon dioxide, but other compositions are possible.Passivation layer goes for providing the moisture protection that comprises of device (for example, interconnection layer).With reference to the example of figure 9, on substrate, (be included on interconnection layer 802) and form passivation layer 902.Passivation layer 902 comprises opening 904, and wherein, fastener (for example, bonding wire, projection) can provide be connected (for example, I/O connects) with device 300.In other words, opening 904 can expose conduction I/O pad.

In the operation 264 of Fig. 2 B, on the back side of substrate, form opening.Form opening, the active area that makes to expose substrate is positioned at a part for transistor arrangement (for example, channel region) below.Opening is aimed at substantially with transistorized active area, and can aim at back gate structure 312/314.Can pass through appropriate light carving technology, then by forming opening such as the etch process of dry ecthing, wet etching, plasma etching and/or their combination.In certain embodiments, in separator, form opening.In other embodiments, in (SOI substrate) buried insulator layer, form opening.With reference to figure 9, in separator 702, provide opening 906.Opening 906 exposes a part for active layer 308.Particularly, can expose active area 319 and part source/drain regions 316.

Refer again to Fig. 2 A, in operation 207, process the exposure substrate region in opening.Pack processing includes at least one in technique, diffusion technology and annealing process.Injection technology embeds alloy in the surface of substrate.Control the degree of depth of injection by the energy of injection technology.The concentration of the alloy in substrate depends on the dosage of injection.With reference to Figure 10, injection technology produces processing layer 1002 at the bottom surface place of opening 906, and its remainder that is positioned at the below, bottom surface of opening 906 than active area 319 has overall lower net doping substrate concentration.In order to realize overall lower concentration of dopant, inject the alloy of the conduction type contrary with active area 319.For N-shaped MOS, inject arsenic or phosphorus.For p-type MOS, B Implanted.Because these alloys have the conduction type contrary with active area 319, so overall net doping substrate concentration reduces in the surface of active area 319.Then,, compared with the remainder of active area, processing layer is lightly doped channel layer.If inject enough alloys, processing layer is depletion layer.Relatively low-yield injection technology can be for being limited in alloy in superficial layer.For example, Implantation Energy can be less than about 10keV or be less than about 15keV.If active area 319 is the thick and larger processing layer of manufacture enough, can use higher-energy.According to various embodiments, processing layer starts to have the peak concentration of approximately 5 dusts or hundreds of dust from surface.The thickness of processing layer can be between approximately 10 nanometers between hundreds of nanometer.

Can directly implement injection technology to substrate or by mask.Can first form injecting mask by deposit sacrificial oxides layer, then, sacrificial oxide layer be carried out to the opening of patterning to be formed for injecting.Can carry out mask generation by forming the operation 206 of opening 906.In certain embodiments, opening 906 is greater than injection opening.For example, processing layer 1002 can extend to a part for source/drain regions 316 or be limited to the surface of active area 319.

In certain embodiments, insulating barrier 306 and passivation layer 902 are enough in other parts of block dopant embedding BioFET.In one embodiment, the operation 262 of execution graph 2B in the situation that not forming opening 904, is injected in interconnection layer 802 preventing.In these embodiments, after injecting, form the opening 904,906 in passivation layer 902.

After injecting, substrate is annealed, to activate alloy.Different alloys require different amount annealing to activate.The speed that lower temperature anneals to reduce activates.Because after forming MLI318 and interconnection layer 802, occur to activate annealing, so the stability of the metal material in device and pollution and activation rate keep balance.In certain embodiments, before forming interconnection layer 802, carry out and inject and activate and anneal.Can under the condition of approximately 400 degrees Celsius, approximately 450 degrees Celsius, carry out and activate annealing, and can be less than approximately 500 degrees Celsius.In certain embodiments, activate alloy with laser.Because laser energy can focus on the surface of substrate, and the duration of laser explosure is very short, is conventionally shorter than 1 microsecond, can, in the case of not to the obvious adverse effect of darker MLI318, carry out laser active.In one embodiment, laser beam flying tube core.In another embodiment, laser beam is adjusted to and has the size that is enough to the alloy that once activates a tube core.

The alloy that alternatively, can tend to the main alloy deactivation that makes active area 319 by interpolation carrys out formation processing layer 1002.In nMOS example, because hydrogen can make boron deactivation, thus can add hydrogen, to produce processing layer 1002.Can be as arsenic, phosphorus and boron hydrogen injecting.Can also add hydrogen by diffusion technology.A kind of diffusion technology relates under hydrogen environment anneals (hydrogen/deuterium gas or formation gas) or hydrogen plasma is applied to surface.Another kind of diffusion technology relates to the dielectric layer of deposition of heavily doped in the opening 906 above active area 319, and then the hydrogen of doping is annealed to be diffused in silicon.Heavily doped dielectric layer can be silica or silicon nitride film.After diffusion annealing, remove dielectric layer.

Except the injection and method of diffusion of formation processing layer 1002, can be by the formation processing layer 1002 of annealing in oxygen or ozone environment.The dangling bonds that annealing reparation is produced by plasma process.Dangling bonds are repaired in annealing in the oxygen environment of oxygen or ozone.Can also be by the formation processing layer 1002 of annealing in hydrogen environment.Annealing in the hydrogen environment of hydrogen or deuterium reduces the infringement of removable ion to prevent that plasma from being produced.There is lower temperature for the annealing that reduces removable ion than above-mentioned diffusion annealing, and the annealing and the diffusion annealing that reduce removable ion can be combined into a step.

Processing layer 1002 allows the electrical property of BSS BioFET to regulate.In the time that processing layer 1002 is lightly-doped layer or depletion layer, BSS BioFET can be more responsive to being engaged to the molecule of acceptor, to improve the mutual conductance of BSS BioFET.In other words,, about the BioFET that there is no processing layer 1002, can increase for the leakage current of grid voltage.In certain embodiments, processing layer 1002 provide can avoid or reduce current leakage compared with large band gap.In certain embodiments, processing layer 1002 comprises than untreated layer defect still less, and can reduce by removable ion and the caused device noise of interface charge.By changing the technique of formation processing layer, the multiple BioFET on identity unit can be adjusted to for identical or different biological entities has different sensitivity.For example, some BioFET can have the first alloy be the first concentration processing layer, and other BioFET can have the processing layer that the second alloy is the second concentration.Different disposal layer allows the differently detection of a target of BioFET.By using different masks and independent lithography step, can on a device, form the processing layer more than a type.

Refer again to Fig. 2 A, in operation 208, in opening, form dielectric layer.Dielectric layer is formed on the exposure substrate of grid structure top of FET, and covers the whole bottom of the opening 906 of processing layer 1002 tops.Exemplary dielectric materials comprises height-k dielectric film, metal oxide and/or other suitable materials.The instantiation of dielectric material comprises HfO ₂, Ta ₂o ₅, Au ₂o ₃, WO ₃, Pt oxide, Ti oxide, the oxide of Al and the oxide of Cu and such as SiO ₂, Si ₃o ₄, Al ₂o ₃, TiO ₂, TiN, SnO, SnO ₂other dielectrics etc.Can use such as for example chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high-density plasma CVD (HDPCVD) or atomic layer CVD(ALCVD) form dielectric layer.In certain embodiments, dielectric layer comprises multilayer.For example, dielectric layer can be included in the hafnium oxide layer of aluminium oxide or titanium oxide layer top.In the example of Figure 11, above active layer 319 and part source electrode and drain electrode 316, dielectric layer 1102 is set.Can for example carry out patterning, to aim at (, it being arranged with patterning to be only retained in opening 906) with grid structure to dielectric layer 1102.

Refer again to Fig. 2 A, in can selection operation 210, depositing metal layers.Metal level can be metal element, metal alloy or conductive metallic compound.Suitable element metal comprises tantalum, niobium, tungsten, ruthenium, aluminium, zirconium, vanadium, titanium, cobalt, molybdenum, osmium, chromium, rhodium, gold, palladium, rhenium, nickel or other transition metal that conventionally use in semiconductor processes.Metallic compound comprises conductive nitride, silicide and the oxide of these transition metals, for example, and tungsten nitride, tantalum nitride and ruthenium-oxide.Metal level can be two-layer or more multi-layered composite bed.For example, metal level can comprise nitride and ruthenium-oxide.

Metal level is conformally deposited in substrate top and opening to cover boundary layer.Can use PVD(sputter), metallochemistry gas deposition (MCVD), atomic layer CVD(ALCVD), electrochemical deposition or the electroless deposition consistent with crystal seed layer carry out depositing metal layers.In certain embodiments, can use ion beam depositing, in opening and optionally depositing metal layers of around openings.

In can selection operation 212, metal level be carried out to patterning to form metal crown structure.In certain embodiments, patterning relate to remove by etching the metal level that deposits in 210 in operation do not need part.First deposition etch mask being patterned.Etching mask can be photoresist or the hard mask that carries out patterning by photoetching process.In other embodiments, first photoresist material is deposited on substrate and is patterned, and after depositing metal layers, removes photoresist material.Stripping photolithography glue material is also removed any upper metal layer.When the dry ecthing that relates to the plasma of removing metal pattern is during by the infringement of the not desired amount that causes plasma to other exposing metal surfaces, lift-off technology may be useful.Because can be only by wet etching or comprise that low-power plasma etching removes the photoresist in stripping technology, so stripping technology is better than metal pattern technology sometimes.But stripping technology has and produces the more possibility of multi-pollutant, and the shape of the metal crown structure obtaining may comprise jagged edges.

In the example of Figure 12, dielectric layer 1102 upper metal hat structures 1202 are arranged in opening and around openings.As shown in the figure, metal crown structure 1202 comprises the lip shape part overlapping with part separator 702.In certain embodiments, all metal crown structures 1202 are all in the opening 906 of Figure 11.In other embodiments, as shown in figure 12, dielectric layer 1102 and metal crown structure 1202 take the volume of (consume) opening.

Refer again to Fig. 2 A, in operation 214, microjet raceway groove or trap are set in device substrate.The region of the metal crown superstructure of jet raceway groove limiting analysis logistics.Can be by utilizing SU-8(epoxy to bear photoresist) photoetching, wafer joint method and/or other appropriate method form jet raceway groove.With reference to the example of Figure 13, jet raceway groove 1302 is set on substrate.Jet raceway groove 1302 provides the trap 1304 of metal crown structure 1202 tops.

Refer again to Fig. 2 A, in operation 216, acceptor is set in metal crown structure or processes film.Acceptor can comprise enzyme, antibody, part (ligand), protein, peptide, nucleotides and their part.Acceptor can be to be configured in the native protein of the modification on one end or enzyme to survey specific analyte.The other end of acceptor is configured to be engaged to metal crown structure or is engaged to another molecule/processing film of metal crown structure.As shown in figure 14, multiple acceptors 1402 are set in metal crown structure 1202.By using metal crown structure, larger surf zone can be used for the acceptor engaging, and therefore more multiple location can be used for biomolecule or biological entities is surveyed.If do not use metal crown structure, acceptor can directly or by another molecule/processing film be arranged on dielectric layer 1102.In certain embodiments, before operation 214, can executable operations 216.

The embodiment of Fig. 2 B relates to many aspects of the present invention, wherein, makes the electrical connection of BioFET device at substrate with jet on the identical side connecting.The invention still further relates at substrate and jet and connect the embodiment that makes the electrical connection of BioFET device on relative side.In those embodiment, before engaging carrier substrates and attenuate device substrate, on the front of substrate, form the electrode and the pad that are connected with MLI.The back side does not form groove 602.

In the operating period of BioFET device, in jet raceway groove, provide the solution that comprises target molecule.BioFET device can comprise the zones of different for the treatment of target molecule.Can make some biomaterial cytolysises, separation, dyeing, and use chemistry, electricity or Optical devices otherwise test or analyze.For example, drop of blood can be joined in entrance and by plasma and cell type and carry out initially-separate.Some cell in drop of blood can be by cytolysis.Some large molecules in lysate can be further destroyed, for the downstream analysis thing of flow path.Can or prune by enzyme reaction, restriction to object chain and make DNA (deoxyribonucleic acid) (DNA) molecule fragment.

After biomaterial is processed into target, by flowing through the microjet raceway groove and the trap detection of a target that comprise BioFET.If use dielectric layer 1102 or metal crown structure 1202, dielectric layer 1102 or metal crown structure 1202 are sensitive surface of BioFET.Can control stream, make compared with the reaction time, in the time there is sensitive surface, target has long residence time.In certain embodiments, when the electric current of BioFET is flow through in collection, change one or more gate bias.Collect and analyze the telecommunications breath from BioFET.

In multiple embodiment, CMOS fabrication tool (for example, casting) can process related device according to the method for multiple embodiment until form jet raceway groove.In one embodiment, user can provide Surface-micromachining process, solion, acceptor etc. subsequently.

In a word, method disclosed herein and device provide the BioFET that uses CMOS and/or CMOS compatible technology to manufacture.Some embodiment of disclosed BioFET can be in biology and/or medical application, comprises a line application that relates to liquid, biological entities and/or reactant.The one detection mechanism of some described embodiment comprises herein: for example, because target biological molecules or biological entities are engaged to jet grid structure or the conductivity adjustment of the FET of the BioFET that (, fixing) acceptor molecule on the jet grid structure of device carries out is set.

Arrange some embodiment of BioFET with array format.Can on silicon-on-insulator (SOI) substrate, construct grid structure.This can provide the advantage of high speed operation and/or less power consumption in certain embodiments.The inverted transistor providing on SOI substrate is provided and can realizes improved manufacture uniformity, there is improved technology controlling and process, and increase BioFET density.For example, due to the formation at SOI substrate, some embodiment can be provided for improved short-channel effect.Miscellaneous part comprises reduced-current leakage, lower power consumption and the lower device noise from irradiation process.

Therefore, should be appreciated that, in one embodiment, described a kind of BioFET, it comprises substrate; Transistor arrangement includes the processing layer that is close to channel region in source region in substrate; Separator has opening on the side relative with transistorized grid structure of substrate; And dielectric layer, be arranged in opening.Transistor arrangement have source area, drain region and comprise channel region and the active area of processing layer above grid structure.

An aspect of of the present present invention relates to the semiconductor device of the array that a kind of BioFET of comprising device is provided.More than first BioFET in array and more than second BioFET comprise between source area and drain region and are positioned at the active area of grid structure below.Active area comprises channel region and the processing layer of adjacent gate structures.Processing layer in more than first BioFET device has the first alloy of the first concentration.Processing layer in more than second BioFET device has the second alloy of the second concentration.More than first BioFET device also comprises the dielectric layer on the side that is arranged on the processing layer relative with channel region with more than second BioFET device.

Another aspect of the present invention relates to a kind of method of the BioFET of manufacture device, comprising: in Semiconductor substrate, form transistor; Etching openings in separator on the second side that is arranged on Semiconductor substrate, wherein, the active area of opening exposed transistor; By the bottom of opening, alloy is embedded in transistorized active area, with formation processing layer; And on processing layer dielectric layer.Can there is by injection the alloy of the conductivity contrary with the alloy of channel region, hydrogen injecting, and realize embedding by one or more alloys of diffusion that heavily doped sacrifice layer is annealed.The method can also be included under oxygen or hydrogen environment Semiconductor substrate is annealed.

In the time describing one or more in these embodiment, the present invention can provide the multiple advantages that are better than existing device.During discussing following advantage or benefit, should be noted that and can have in certain embodiments these benefits and/or result, but do not require these benefits and/or result.The advantage of some embodiments of the present invention comprises the ability that user customizable product is provided.For example, can carry out that jet raceway groove forms by user, acceptor introducing etc.As another example of the advantage of one or more embodiment described herein, in traditional devices, conventionally require high aspect ratio technique for example, to form bio-compatible interface (, requiring from the front-side etch of substrate to grid structure).Because this method provides processing of the back side to attenuate wafer, so can reduce aspect ratio.

Claims (10)

1. biological field effect transistor (BioFET) device, comprising:

Substrate;

Transistor arrangement has the grid structure being positioned at above source area, drain region and active area in described substrate, and described active area comprises channel region and processing layer;

Separator, is positioned on the side relative with described grid structure of described substrate, and described separator has opening at the described active area place of described transistor arrangement; And

Dielectric layer, is arranged in described opening.

2. BioFET device according to claim 1, wherein, described processing layer is lightly-doped layer.

3. BioFET device according to claim 1, wherein, described processing layer comprises the alloy that doping type is contrary with alloy in described channel region.

4. BioFET device according to claim 1, wherein, described processing layer comprises hydrogen.

5. BioFET device according to claim 1, further comprises: metal crown structure, is positioned at described separator top and covers at least in part the sidewall of described opening.

6. BioFET device according to claim 1, wherein, described dielectric layer comprises aluminium oxide, titanium oxide, hafnium oxide, tantalum oxide, tin oxide or their combination.

7. BioFET device according to claim 1, further comprises:

Be arranged on the jet raceway groove on described separator.

8. BioFET device according to claim 1, further comprises:

Multilayer interconnection part (MLI) is arranged on the side identical with described grid structure of described substrate in described substrate.

9. a method of manufacturing BioFET device, comprising:

In Semiconductor substrate, form transistor, wherein, described transistor comprises grid structure on the first side that is formed on described Semiconductor substrate and the active area between source area and drain region;

Etching openings in separator on the second side that is arranged on described Semiconductor substrate, described opening exposes described transistorized active area;

By the bottom of described opening, alloy is embedded in described transistorized active area with formation processing layer; And

Dielectric layer on described processing layer.

10. a device, comprising:

Multiple BioFET, each described BioFET comprises:

Active area, between source area and drain region and below grid structure, described active area comprises channel region and the first processing layer, and described channel region is in abutting connection with described grid structure; With

Dielectric layer, is arranged on the side relative with described channel region of described the first processing layer;

Wherein, described the first processing layer comprises the first alloy of the first concentration; And multiple the 2nd BioFET, each described the 2nd BioFET comprises:

Active area, between source area and drain region and below grid structure, described active area comprises channel region and the second processing layer, and described channel region is in abutting connection with described grid structure; With

Dielectric layer, is arranged on the side relative with described channel region of described the second processing layer;

Wherein, described the second processing layer comprises the second alloy of the second concentration.