201141031 六、發明說明： 【發明所屬之技術領域】 本發明係與諧波抑制技術有關，特別是指一種換流器 之噪音抑制方法。 【先前技術】 電子產品中’許多負載的驅動均需要先利用換流器或 籲 變頻器將-般頻率為60Hz的市電轉變為負载所需的頻 率’常見需使用換流器驅動的產品如馬達、太陽能板、冷 陰極管或冷光板等等；換流器原理係經由開關電晶體之切 換導通達成改變頻率之目的，不過以開關電晶體之邏輯運 作方式，使輸出之驅動電源為數位邏輯形式之交流方波， 而方波訊號本身則會在基本波以外形成多數奇次譜波不 但高次諸波成分形成電路雜訊，低次譜波成分更產生音頻 噪音’造成人耳在聽覺上感到尖銳、刺耳。 # …當然、，負載操作頻率以外頻段的雜訊部分皆可設計滤 ^二加以;慮除’且-般開關電晶體後級亦會設計有渡波器 :關切換所產生的喊雜訊濾除，同時也可濾除相同頻 从圍内由方波訊號夾帶的高次譜波成分；然’濾波所用 的ί感元件佔有相當的電路空間，如此若需過濾所有諧波 及间頻雜訊’所设計之滤波器則需使用大量的電感元件， 2增加整體電路嶋。再者，基本波以外的譜波組成 =、，越低切波雜量鲜敍1但驗膽大電感 付以濾除’且為了將較高功率的低次諧波滤除 ，勢必會 201141031 對基本波的功率造成干擾，因而降低電路驅動效率。 我國專利公告第1309910號及第456104號皆有針對換 流器之輸崎波錯提㈣應之魏雜方式，本發明人 亦致力於提出可以簡單的電路設計有效濾除負载操作頻率 、卜的雜Λ ’同日^•滿足小體積、高效率的換流器驅動電 需求。 【發明内容】 本發明之主要目的在於提供一種換流器之噪音抑制方 法’可有效降低甚至;肖除因為關_造成人耳在聽覺上 感到尖銳、刺耳的聲音，滿足電子產品中需要達到低噪音 的需求。 為達成上述目的，本發明所提供一種換流器之噪音抑 制方法係以具有正半週波之三週期方波訊縣基礎，利用 選擇性諧波抑制脈波寬度調變（sdective harm〇nic elimination pulse width m〇dulati〇n，SHE p丽）技術產生 之二脈波寬度調變職，分別於每半職交錯輸入上述換 流器之上、下臂邏輯電晶體；各該脈波寬度調變訊號於單 -週期中N個相位角度的振幅為零，該些相位角度係以冗 /2為中心於相反相位方向兩兩對稱。該二脈波寬度調變訊 號用以消除無H之輸出波料自低次諧波起之多個奇次 諧波’因此㈣柄具有音_音；舰波寬度調變訊號 於四分广厂週波之内的相位角度具有以下關係： /(«) = — ΐ](-1广1 c〇s«,·% = 〇 ηίπ Κ=ι . , ^ _ ’ ι=1，2,3··.μ 201141031 其中M=N/2，ni = 2i+l，為各該相位角度。 【實施方式】 為了詳細說明本發明之結構、特徵及功效所在，茲舉 以下較佳實施例並配合圖式說明如後，其中： 第一圖為本發明第一較佳實施例所提供之電路功能示 trS*! · 園， 第二圖為上述第一較佳實施例所提供之電路結構示意 rag · 圖， 第三圖為上述第一較佳實施例所提供諧波抑制技術之 基礎週期方波之波形示意圖； 第四圖為上述第一較佳實施例所提供諧波抑制技術之 脈波寬度調變訊號之波形示意圖，表示對第三圖之波形凹 陷所對應之凹陷自由度相位關係； 第五圖為上述第一較佳實施例所提供換流器之輸出波 形示意圖； 第六圖A為上述第一較佳實施例所提供換流器以基礎 週期方波輸入所得之輸出電壓波形，表示於頻域之諧波分 佈示意圖； 第六圖B為上述第一較佳實施例所提供換流器以脈波 寬度調變訊號輸入所得之輸出電壓波形，表示於頻域之諧 波分佈示意圖； 第七圖本發明第二較佳實施例所提供之電路結構示意 201141031 請參閱如第一及第二圖所示， =-__音抑.二::= 換"IL器10係對一可程式化s Η 的料㈣、⑽㈣狀魏抑制技術 I I流電源3G轉換為交流訊號輸出至一 :頻通噪慮音皮器^處理，可使輸出至—負載5fl的訊號不具有 可你2流電源3G為提供該換流^ 1G之直流操作為主， 等將市用錢電源經龍轉換，在此僅為 舉例說明，並非做為限制要件。 β 有多數贿輯電路12、多數個輸入端 互^及-輸出端組16 ;該些邏輯電路12主要以兩兩相 之第-、第二邏輯電晶體Q1、Q2及第三、第四 輯電晶體Q3、Q4相互並接形叙橋式電路，其 第四^電晶體Q1、Q4為上臂，第二、第三邏輯電晶體 邏輯nr;各該輸入端組14分別對應電性連接各該 本__提供由金屬氧化物半導體製成 :^^之賴電晶體㈣冬㈣例各 it 用以接收可程式化晶片2G所輪出之脈波寬 調變訊號以輸入各該邏輯電晶體32閘極使 止運作；上述脈波寬度調變訊號係以同步控制該第一3'第 ，輯電晶體φ、Q4之運作，以及以同步控^、 ==輯電晶體Q2、Q3之運作。為使該第—與第四邏輯 曰曰體Ql、Q4或該第二與第三邏輯電晶體切、Q4接收 201141031 同步之脈波寬度調變訊號，可將該些輸入端組14之一第一 及一第四輸入端組142、148電性連接該可程式化晶片20 之一第一接腳22，該些輸入端組14之一第二及一第三輸 入端組144、146電性連接該可程式化晶片2〇之一第二接 腳24;因此該可程式化晶片20可利用兩組脈波寬度調變 訊號，分別自該第一接腳22控制該第一、第四邏輯電晶體 Q卜Q4觸發導通以及自該第二接腳24控制該第二、第三 邏輯電晶體Q2、Q3觸發導通。 該可程式化晶片20係以如第三圖所示具有正半週波 之二週期方波SQ1、SQ2訊號為基礎，利用選擇性譜波抑 制脈波寬度調變（selective harmonic elimination pulse width modulation ’ SHE-PWM)技術產生如第四圖所示之二脈波 寬度調變訊號PWM1、PWM2，控制換流器各邏輯電路12 關’使上臂φ、Q4、下臂Q2、Q3交替切換達成換流且 抑制諧波之目的；請配合以下推論方程式參照，本發明所 提供換流器之噪音抑制方法係由可程式化晶片2〇以諧波 抑制技術規劃換流器1〇之輸出波形，將自低次諧波起之多 個奇數次諧波消除，因此使該直流電源3〇經換流器1〇之 邏輯轉換為如第五圖所示之以四分之一週期對稱之方波交 流訊號’並由該換流器10之輸出端組16輸出。 由於任一非弦波之週期性波形f(t)皆可由傅立葉級 數分析表示為： J 〇〇 ’ f{t) = — «〇 + ^] {α„ sin(nfi>/) + b„ cos(«e>/)} "=， ……式⑴， 201141031 其中η為f(t)的諧波次數， ΐΓ/(〇·)……式⑵， f(i)sin(n&t)d(at) "^ ……式（3)， 6"= : ί /(〇cos(⑽加(如） 务 π .·.···式⑷； .f式（4)等於零，剩下式（3)，則該波形稱為偶函數對 稱^式（3)等於零’剩下式⑷’則該波形稱為奇函數對 稱’右式（3)與式⑷對偶數n等於零且僅剩下奇數n 該波形稱為半波函數對稱。 因此’該可程式化晶片2〇之諧波規劃消除原理是以如 第二圖所示正半週波之週期方波_、SQ2作為基礎對方 波作凹陷’亦即抑制該週期方波sQ卜柳之每—正週波 中多個相位角度的振幅，成為如第四圖所示之二脈波寬度 調變訊號PWM1、PWM2為四分之一週期對稱之奇函 形’藉由凹陷所帶來的自由度可控制換流器1()所輸出電壓 之基本钱諧波成分大小。請錢如第五圖所示，由換流 器Η)欲規狀輸出電壓絲，即對應可得雜式化晶片 對週期方波之規劃，使該些受抑制的相位角度以Μ為 、於相反相位方向兩兩對稱；故於四分之—週期内 ^固自由度變數αι、α2·..α«為欲規劃之自由度的相位角 ^當波形規劃為Μ個角度，就會㈣個欲控制的既定條 1、〜···〜’規劃之波形可以寫為非線性聯立方程式如下 式： 201141031 式⑸； 規畫波形的傅立葉分析與推導如下，進而求解規劃之 自由度變數αι、α2···αΜ: f{t) = -α〇 + Υ [α„ sin(«fi)/) + b„ cos(no〇] 2 台 ……式（6); 使a〇=0及bn=0，則 λ η201141031 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a harmonic suppression technique, and more particularly to a noise suppression method for an inverter. [Prior Art] In the electronic products, the drive of many loads requires the use of an inverter or a frequency converter to convert the mains frequency of 60 Hz into the frequency required by the load. Commonly, inverter-driven products such as motors are required. , solar panels, cold cathode tubes or cold plates, etc.; the converter principle is switched through the switching transistor to achieve the purpose of changing the frequency, but in the logic mode of the switching transistor, the output driving power supply is digital logic form The alternating square wave, and the square wave signal itself will form most odd-order spectral waves outside the fundamental wave. Not only the high-order wave components form circuit noise, but the low-order spectral components produce more audio noise, causing the human ear to feel the hearing. Sharp and harsh. # ... Of course, the noise part of the frequency band other than the load operating frequency can be designed and filtered; the "after-switching transistor" stage will also be designed with a waver: the noise filtering generated by the switching At the same time, it can also filter out the high-order spectral components entrained by the square wave signal from the same frequency; however, the 'mechanical components used for filtering occupy a considerable circuit space, so if you need to filter all harmonics and inter-frequency noise' The designed filter requires a large number of inductive components, 2 to increase the overall circuit. Furthermore, the spectral wave composition other than the fundamental wave =, the lower the chopping noise, the lesser, but the larger the inductance, the lower the harmonics are filtered out, and it is bound to be 201141031. The power of the fundamental wave causes interference, thereby reducing circuit drive efficiency. China Patent Announcement No. 1309910 and No. 456104 have the Wei Miscellaneous Method for the Inverter of the Inverter (4), and the inventors are also working to propose a simple circuit design to effectively filter the load operation frequency, Chowder 'on the same day ^• Meet the small-volume, high-efficiency inverter drive power requirements. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for suppressing noise of an inverter, which can effectively reduce even the sharpness and harshness of the human ear, which is required to achieve low requirements in electronic products. The need for noise. In order to achieve the above object, the noise suppression method for an inverter provided by the present invention is based on a three-cycle square wave county having a positive half-cycle, and uses selective harmonic suppression to suppress pulse width modulation. Width m〇dulati〇n, SHE p Li) The two-pulse width modulation function generated by the technology is input to the upper and lower arm logic transistors of each of the above-mentioned inverters in each half job; each of the pulse width modulation signals The amplitudes of the N phase angles in the single-period are zero, and the phase angles are symmetric with respect to the opposite phase directions centered on the redundancy/2. The two-pulse width modulation signal is used to eliminate multiple odd-order harmonics of the output wave without H from the low-order harmonics. Therefore, the (four) handle has a sound_sound; the ship-wave width modulation signal is at the Sifenguang factory. The phase angle within the cycle has the following relationship: /(«) = — ΐ](-1广1 c〇s«,·%= 〇ηίπ Κ=ι . , ^ _ ' ι=1,2,3·· .μ 201141031 where M=N/2, ni = 2i+l, for each of the phase angles. [Embodiment] In order to explain in detail the structure, features and effects of the present invention, the following preferred embodiments are combined with the drawings. The following is a schematic diagram of the circuit function provided by the first preferred embodiment of the present invention, and the second diagram is a schematic diagram of the circuit structure provided by the first preferred embodiment of the present invention. The third figure is a schematic diagram of the waveform of the fundamental periodic square wave of the harmonic suppression technique provided by the first preferred embodiment; the fourth figure is the pulse width modulation of the harmonic suppression technique provided by the first preferred embodiment. The waveform diagram of the signal indicates the phase relationship of the depression degree corresponding to the waveform depression of the third figure; The output waveform of the converter provided by the first preferred embodiment is shown in FIG. 6 is a schematic diagram of the output voltage waveform obtained by the inverter according to the first preferred embodiment. FIG. 6 is a schematic diagram of the output voltage waveform obtained by inputting the pulse width modulation signal of the inverter provided by the first preferred embodiment, and the harmonic distribution diagram in the frequency domain is shown; The circuit structure shown in the second preferred embodiment of the present invention is shown in 201141031. Please refer to the first and second figures, as shown in the first and second figures, =-__sound suppression. 2::= for "IL device 10 is a programmatic s Η material (four), (10) (four) Wei suppression technology II flow power 3G conversion to AC signal output to a: frequency noise noise sensor ^ processing, can output to - load 5fl signal does not have you 2 stream power 3G In order to provide the DC operation of the commutation ^ 1G, etc., the city will use the money to convert the power supply through the dragon, which is only for illustrative purposes, not as a limitation. β has a majority bribe circuit 12, most inputs are mutual ^ And - output group 16; these logic circuits 12 are mainly The first and second logic transistors Q1 and Q2 and the third and fourth series of transistors Q3 and Q4 are connected to each other in a bridge circuit, and the fourth transistor Q1 and Q4 are upper arms and second. The third logic transistor logic nr; each of the input terminal groups 14 respectively corresponding to the electrical connection of the respective __ provided by the metal oxide semiconductor: ^ ^ 赖 电 ( (4) winter (four) each it is used to receive The pulse width modulation signal rotated by the stylized chip 2G is input to the gate of each of the logic transistors 32 to operate; the pulse width modulation signal is synchronously controlled to control the first 3', the transistor φ The operation of Q4, as well as the operation of synchronous control ^, == series of transistors Q2, Q3. In order to make the first-to-fourth logical body Q1, Q4 or the second and third logical transistors cut, and Q4 receive the 201141031 synchronous pulse width modulation signal, one of the input end groups 14 may be The first and fourth input groups 142 and 148 are electrically connected to one of the first pins 22 of the programmable chip 20, and the second and third input groups 144 and 146 of the input terminal group 14 are electrically connected. Connecting the second pin 24 of the programmable chip 2; thus, the programmable chip 20 can control the first and fourth logics from the first pin 22 by using two sets of pulse width modulation signals respectively. The transistor Q Q4 triggers conduction and controls the second and third logic transistors Q2, Q3 to initiate conduction from the second pin 24. The programmable wafer 20 is based on a two-period square wave SQ1 and SQ2 signal having a positive half cycle as shown in the third figure, and uses selective spectral suppression pulse width modulation ( SHE). -PWM) technology generates two pulse width modulation signals PWM1, PWM2 as shown in the fourth figure, and controls each logic circuit 12 of the inverter to turn off the upper arms φ, Q4, and the lower arms Q2 and Q3 to achieve commutation. For the purpose of suppressing harmonics, please refer to the following inference equation reference. The noise suppression method of the converter provided by the present invention is to prepare the output waveform of the converter 1 by the programmable suppression chip 2 by the harmonic suppression technology, which will be low. The subharmonics are eliminated by a plurality of odd harmonics, so that the logic of the DC power source 3 is converted to a square wave AC signal symmetrical with a quarter cycle as shown in FIG. And output by the output terminal group 16 of the inverter 10. Since the periodic waveform f(t) of any non-chord wave can be expressed by Fourier series analysis: J 〇〇' f{t) = — «〇+ ^] {α„ sin(nfi>/) + b„ Cos(«e>/)} "=, ...... (1), 201141031 where η is the harmonic order of f(t), ΐΓ/(〇·)... (2), f(i)sin(n&t )d(at) "^ ......(3), 6"= : ί /(〇cos((10)加(如) π .······(4); .f (4) is equal to zero, left The following equation (3), the waveform is called even function symmetry ^ (3) is equal to zero 'remaining equation (4)' then the waveform is called odd function symmetry 'right equation (3) and equation (4) even number n is equal to zero and only left The odd-numbered n is called the half-wave function symmetry. Therefore, the harmonic programming elimination principle of the programmable wafer 2〇 is based on the periodic square wave _ and SQ2 of the positive half-cycle as shown in the second figure. The depression 'is suppresses the amplitude of the plurality of phase angles in the positive square wave of each of the periodic square waves sQ, and becomes a quarter-cycle symmetry of the two-pulse width modulation signals PWM1 and PWM2 as shown in the fourth figure. The odd form 'the freedom brought by the depression The basic harmonic component of the output voltage of the inverter 1() can be controlled. Please refer to the output of the voltage wire as shown in the fifth figure. The planning of the periodic square wave makes the suppressed phase angles Μ 、 、 、 、 、 、 、 、 、 ; ; ; ; ; ; 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 相反 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四The phase angle of the degree of freedom ^When the waveform is planned as an angle, the (four) predetermined bars to be controlled 1, ~···~ 'planned waveforms can be written as nonlinear simultaneous equations as follows: 201141031 Equation (5); The Fourier analysis and derivation of the planned waveform are as follows, and then the degree of freedom of the solution is calculated αι, α2···αΜ: f{t) = -α〇+ Υ [α„ sin(«fi)/) + b„ cos( No〇] 2 sets... (6); Let a〇=0 and bn=0, then λ η
αη = — ^ /{ί)ύη(ηωί)ά{ωί) 根據第五圖所不’對於奇數η，使 〇n £48ίη(«ω〇ί/(ωί)...+ £，+1sin(«6)〇i/(iy〇] 式（8) -M- J, ^<a^<a2...<au <~ 其中 2 : M個自由角度代入式（8)必須要等於零才能消除規劃 之諧波’其方μ程式可表示為：Ηη = — ^ /{ί)ύη(ηωί)ά{ωί) According to the fifth figure, for the odd number η, 〇n £48ίη(«ω〇ί/(ωί)...+ £,+1sin( «6)〇i/(iy〇) Equation (8) -M- J, ^<a^<a2...<au <~ where 2: M free angle substitutions (8) must be Equal to zero to eliminate the harmonics of the plan. The other μ program can be expressed as:
fx{a\,al..xxM) _Γ1 f2ia\,a2..xxM) = Γ2 fM(al,a2..xxM) .ΓΜ. 式⑺； 义⑷=5 § (一1广丨咖=0 ' * i=l, 2, *··Μ ......式（9)， 其中ni = 2i+l，ακ為各該相位角度； a以圖不波形而言，欲規劃消除3次、5次、7次、9次、 13人15次、17次及19次諧波，故自由度變數有 ^制之狀條件 M#r3、r5、r7、r9、rU、ri3、ri5、 U二9得數與既定條件代入職^ 聯立方非 絲組如下式，求解其非線性 聯立方程組可得到α1、α2、α3、α4、α5、α6、α7、 201141031 α8、《9九個自由度變數解： F(a) = 'cos3a, -cos3a2 +cos3a3 -cos3a4 +cos3as cos 5a, -cos5a2 +cos5a3 -cos5a4 +cos5ar5 cos 7a, - cos 7a2 + cos 7a3 - cos 7at + cos 7as cos 9a, - cos 9a2 + cos 9a3 - cos 9a4 + cos 9a5 cos 1 la, - cos 1 la2 + cos 1 la} - cos 1 la4 + cos 1 la5 cos 13ar, - cos 13a2 + cos 13a3 - cos 13a4 + cos 13as cos 15a, - cos 15a2 + cos 15a2 - cos 15a4 + cos 15as cos 17a, -cosl7a2 +cosl7a3 -cosl7a4 +cosl7as cos 19a, - cos 19a2 + cos 19a3 - cos 19a4 + cos 19a5 -cos 3a6 + cos 3a7 - cos 3ag + cos 3a9 '3^3 -cos 5a6 + cos 5αΊ - cos 5ag + cos 5a9 5r5 -cos 7a6 + cos 7a7 - cos 7as + cos 7a9 7r7 -cos9a6 + cos9a7 - cos9a8 + cos9a9 π =— 4 9r9 -cos 1 la6 + cos 1 la7 - cos 1 la8 + cos 1 la9 1卜" -cos 1+ cos 13ar7 - cos 13a8 + cos 1 ：3a9 13r13 -cos 15a6 + cos 15a·, - cos 15ag + cos 15ag 15r15 -cos 17a6 + cos 17αη - cos 17at + cos 17a9 17rl7 -cos 19a6 + cos 19a7 - cos 19as + cos 19a9 _19r19_ 式（10) 〇 因此若以消除19次諧波以前的低次諧波設計，該可程 式化晶片20之則規劃產生如第四圖所示之二脈波寬度調 變訊號PWM1、PWM2，將各週期方波SQ卜SQ2於各相 位角度 al、〇；2、a3、a4、a5、a6、a7、a8 及 〇:9 凹陷’藉由凹陷所帶來的自由度即可抑制換流器10所輸出 電壓之基本波以外低次諧波成分。請參閱如第六圖所示， 當可程式化晶片以如第三圖之週期方波SQ1、SQ2控制該 換流器10 ’則得該換流器10之輸出電壓波形於頻域之言皆 波分佈如第六圖A所示，除了基本波更有明顯的低次諧波 成分；相較於以如第四圖之脈波寬度調變訊號PW]yQ、 PWM2控制該換流器10，則得該換流器10之輸出電壓波 形於頻域之諧波分佈如第六圖B所示’明顯可見，基本波 201141031 以外的低次諧波成分皆有效被抑制。 該滤波器40電性連接該換流器10之輸出端組16，.係 以多個滤波元件42、44將換流器1〇輸出之方波交流訊號 轉換為正弦波訊號提供負載50所需，本實施例所提供者為 以低通濾波器濾除換流器1〇所輸出的高頻諧波，同時可濾 除換流器10開關電路12所產生的高頻切換雜訊；由於換 流器10低次諧波成分已被抑制，因此以小於該換流器1〇 • 輸出之譜波頻率即可作為該濾波器40之低通濾波截止頻 率。該些濾波元件42、44具有特定之電感、電容條件，設 計之前，首先了解負載50之元件特性，例如使用RLC測 量儀等，測量負載50在不同操作頻率下之對應特性阻抗； 對於有特定操作頻率需求之負載5〇而言，越高特性阻抗之 負載50則該滤波器4〇需設計有越高電感值的等效電感元 件，當然，在負載50操作頻率可調整之彈性範圍内，可提 冑操作解韓持負載5G之雜阻抗。經由上述脈波寬度 f變訊號PWM卜PWM2 _低:欠舰所產生之音頻噪音 部分’使該換流器10輸出方波交流訊號之基頻僅夾帶高次 諧波部分，因此由電感公式XL = 27rfL可知，對於後級之 該濾波器40而言，當遽波頻段越高，濾波所需要的等效電 f之電感值就可如此—來，低電感即可針滤掉高 - 人諧波成分或電晶體開關切換產生的高頻雜訊干擾且低 電感元件可使5亥濾波器40所佔用之電路空間體積大幅縮 /J、0 因此本發明所提供換流器10之噪音抑制方法，可使最 201141031 後輸出至負载5〇之工作波形為無諧波成分之正弦波；至於 因應不同負載50元件特性時，僅需改變基本波的操作頻率 3”器4〇的截止頻率，同樣可在有效節省電路 體積下’抑制電路之音頻噪音或高頻雜訊干擾。 值得一提的是’本發明所提供換流器之噪音抑制方法 上述實施例所例舉之全橋式電路所構成的換流 換气器I七圖所示本發明第二較佳實施例所提供一 之電路結構而言，明於第一圖所示之電路功能 右蓉教雜電晶體仏如所串接之半橋式電路具 之，、用。差別僅在於，在相同直流電源3〇 =下’全橋柄最大輸出電壓為半橋式的兩倍，對於同功 下’全橋式的輸出電流與開關通過之電流只要一 :;當：’全橋式之邏輯電晶體之耐壓、耐流值都可以比 晶體開關的體積也會較小，對於電子產品小 曰體門’不過因半橋式f路成本較低，故雖單顆電 ;=耐[耐流雖稍高，但可適用於中低功率需求之 露的構成元 ，其他等效 圍所涵蓋。 4上所陳’本發明於前述實施例中所揭 件，僅為舉例說明，並非用來限制本案 之範圍 替代或變化，亦應為本案之f請專利範 201141031 【圖式簡單說明】 第一圖為本發明第一較佳實施例所提供之電路功能示 意圖； 第二圖為上述第一較佳實施例所提供之電路結構示意 圖； 第三圖為上述第一較佳實施例所提供諧波抑制技術之 基礎週期方波之波形示意圖； 第四圖為上述第一較佳實施例所提供諧波抑制技術之 脈波寬度調變訊號之波形示意圖，表示對第三圖之波形凹 陷所對應之凹陷自由度相位關係； 第五圖為上述第一較佳實施例所提供換流器之輸出波 形示意圖； 第六圖A為上述第一較佳實施例所提供換流器以基礎 週期方波輸入所得之輸出電壓波形，表示於頻域之諧波分 佈示意圖； 第六圖B為上述第一較佳實施例所提供換流器以脈波 寬度調變訊錄人所得之輸出電紐形，表*於頻域之譜 波分佈示意圖； 第七圖本發明第二較佳實施例所提供之電路結構示意 圖。 【主要元件符號說明】 10、60換流器 12邏輯電路 W、Q2、Q3、Q4、q5、Q6 邏輯電晶體 13 201141031 14輸入端組 144第二輸入端組 148第四輸入端組 20可程式化晶片 24第二接腳 142第一輸入端組 146第三輸入端組 16輸出端組 22第一接腳 30直流電源 SQ卜SQ2週期方波 PWM1、PWM2脈波寬度調變訊號 0； 1、CK 2··· (3： Μ自由度變數Fx{a\,al..xxM) _Γ1 f2ia\,a2..xxM) = Γ2 fM(al,a2..xxM) .ΓΜ. Equation (7); Meaning (4)=5 § (一一广丨咖=0' * i = l, 2, *··Μ 式 (9), where ni = 2i + l, α κ is the phase angle; a in the case of the waveform, to plan to eliminate 3 times, 5 times, 7 times, 9 times, 13 people, 15 times, 17 times and 19th harmonics, so the degree of freedom variable has the conditions of the system M#r3, r5, r7, r9, rU, ri3, ri5, U 9 number and the established conditions are substituted into the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Variable solution: F(a) = 'cos3a, -cos3a2 +cos3a3 -cos3a4 +cos3as cos 5a, -cos5a2 +cos5a3 -cos5a4 +cos5ar5 cos 7a, - cos 7a2 + cos 7a3 - cos 7at + cos 7as cos 9a, - cos 9a2 + cos 9a3 - cos 9a4 + cos 9a5 cos 1 la, - cos 1 la2 + cos 1 la} - cos 1 la4 + cos 1 la5 cos 13ar, - cos 13a2 + cos 13a3 - cos 13a4 + cos 13as cos 15a, - Cos 15a2 + cos 15a2 - cos 15a4 + cos 15as cos 17a, -cosl7a2 +cosl7a3 -cosl7a4 +cosl7as cos 19a, - cos 19a2 + cos 19a3 - cos 19a4 + cos 19a5 -cos 3a6 + cos 3a7 - cos 3ag + cos 3a9 '3^3 -cos 5a6 + cos 5αΊ - cos 5ag + cos 5a9 5r5 -cos 7a6 + cos 7a7 - cos 7as + cos 7a9 7r7 -cos9a6 + cos9a7 - cos9a8 + cos9a9 π =— 4 9r9 -cos 1 la6 + cos 1 la7 - cos 1 la8 + cos 1 la9 1 b" -cos 1+ cos 13ar7 - cos 13a8 + cos 1 :3a9 13r13 -cos 15a6 + Cos 15a·, - cos 15ag + cos 15ag 15r15 -cos 17a6 + cos 17αη - cos 17at + cos 17a9 17rl7 -cos 19a6 + cos 19a7 - cos 19as + cos 19a9 _19r19_ (10) 〇 Therefore, to eliminate the 19th harmonic In the previous low-order harmonic design, the programmable chip 20 is planned to generate the two-pulse width modulation signals PWM1 and PWM2 as shown in the fourth figure, and the periodic square waves SQ and SQ2 are at the respective phase angles a1. 〇; 2, a3, a4, a5, a6, a7, a8, and 〇: 9 The depression's degree of freedom by the depression can suppress the low-order harmonic components other than the fundamental wave of the output voltage of the inverter 10. Referring to FIG. 6 , when the programmable chip controls the inverter 10 ' with the periodic square waves SQ1 and SQ2 as shown in the third figure, the output voltage waveform of the converter 10 is in the frequency domain. The wave distribution is as shown in FIG. 6A, except that the fundamental wave has a more obvious low-order harmonic component; compared to the pulse-wave width modulation signal PW]yQ, PWM2 as shown in FIG. 4, the inverter 10 is controlled. Then, the harmonic distribution of the output voltage waveform of the inverter 10 in the frequency domain is clearly visible as shown in FIG. 6B, and the low-order harmonic components other than the fundamental wave 201141031 are effectively suppressed. The filter 40 is electrically connected to the output terminal group 16 of the inverter 10, and the square wave AC signal outputted by the inverter 1〇 is converted into a sine wave signal by the plurality of filter components 42 and 44 to provide a load 50. In this embodiment, the high-frequency harmonic outputted by the inverter 1〇 is filtered by the low-pass filter, and the high-frequency switching noise generated by the switching circuit 12 of the inverter 10 can be filtered out; The low-order harmonic component of the streamer 10 has been suppressed, so that the spectral frequency of the output of the converter 40 can be used as the low-pass filter cutoff frequency of the filter 40. The filter elements 42, 44 have specific inductance and capacitance conditions. Before designing, first understand the component characteristics of the load 50, for example, using an RLC meter, etc., to measure the corresponding characteristic impedance of the load 50 at different operating frequencies; For the load of the frequency requirement 5〇, the higher the characteristic impedance of the load 50, the filter 4 needs to design an equivalent inductance component with a higher inductance value, and of course, within the elastic range in which the operating frequency of the load 50 can be adjusted, The operation of the solution is to solve the hybrid impedance of 5G load. Through the above pulse width f variable signal PWM Bu PWM2 _ low: the audio noise portion generated by the yoke makes the fundamental frequency of the output of the square wave AC signal of the converter 10 only entrain the higher harmonic part, so the inductance formula XL = 27rfL, for the filter 40 of the latter stage, when the chopping frequency band is higher, the inductance value of the equivalent electric f required for filtering can be so--the low inductance can filter the high-human harmonic The high-frequency noise interference generated by the switching of the wave component or the transistor switch and the low-inductance component can greatly reduce the circuit space volume occupied by the 5H filter 40/J, 0. Therefore, the noise suppression method of the inverter 10 provided by the present invention is provided. The working waveform that can be output to the load 5〇 after 201141031 is a sine wave with no harmonic component; as for the 50 component characteristics of different loads, it is only necessary to change the cutoff frequency of the operating frequency of the fundamental wave 4′′, 4 It can suppress the audio noise or high-frequency noise interference of the circuit under the effective saving of the circuit volume. It is worth mentioning that the noise suppression method of the converter provided by the present invention is composed of the full bridge circuit exemplified in the above embodiment. of The circuit configuration of the second preferred embodiment of the present invention shown in the seventh embodiment of the present invention is as shown in the first embodiment of the present invention, and the function of the circuit shown in the first figure is the half bridge of the cluster. The circuit is used, and the difference is only that the maximum output voltage of the full bridge shank is twice that of the half bridge type under the same DC power supply 3〇=, for the same function, the full-bridge output current and the switch pass. The current is only one: when: 'The full-bridge logic transistor's withstand voltage and current resistance can be smaller than the crystal switch's volume, for the electronic product small body door' but due to the half-bridge f-cost It is lower, so although it is single electric; = resistant [slightly high, but it can be applied to the constituent elements of the medium and low power demand, and other equivalent enclosures are covered. 4上上陈' The invention is in the foregoing embodiment The above description is for illustrative purposes only and is not intended to limit the scope of the present invention. It is also intended to limit the scope of the present application. Patent application 201141031 [Simplified illustration of the drawings] The first figure is the first preferred embodiment of the present invention. A schematic diagram of the circuit function provided; the second figure is the first preferred embodiment The schematic diagram of the circuit structure provided by the example; the third figure is a schematic diagram of the waveform of the fundamental periodic square wave of the harmonic suppression technique provided by the first preferred embodiment; and the fourth figure is the harmonic suppression provided by the first preferred embodiment. The schematic diagram of the waveform of the pulse width modulation signal of the technology, showing the phase relationship of the depression degree corresponding to the waveform depression of the third figure; FIG. 5 is a schematic diagram of the output waveform of the converter provided by the first preferred embodiment; FIG. 6 is a schematic diagram showing the output voltage waveform obtained by the inverter according to the first preferred embodiment in the basic period square wave input, showing the harmonic distribution in the frequency domain; FIG. 6B is the first preferred embodiment described above. For example, the output current of the inverter is modulated by the pulse width modulation, and the distribution of the spectral wave in the frequency domain is shown in FIG. 7 . FIG. 7 is a schematic diagram of the circuit structure provided by the second preferred embodiment of the present invention. . [Main component symbol description] 10, 60 inverter 12 logic circuit W, Q2, Q3, Q4, q5, Q6 logic transistor 13 201141031 14 input terminal group 144 second input terminal group 148 fourth input terminal group 20 programmable Wafer 24 second pin 142 first input end group 146 third input end group 16 output end group 22 first pin 30 DC power supply SQ Bu SQ2 period square wave PWM1, PWM2 pulse width modulation signal 0; CK 2··· (3: Μdegree of freedom variable
40低通濾波器 42、44濾波元件 50負載40 low pass filter 42, 44 filter component 50 load