六、發明說明： 【發明所屬之技術領域】 本發明係與諧波抑制技術有關，特別是指一種換流器 之噪音抑制方法。 【先前技術】 電子產品中’許多負載的驅動均需要先利用換流器或 變頻器將一般頻率為60Hz的市電轉變為負載所需的頻 率’常見需使用換流器驅動的產品如馬達、太陽能板、冷 陰極管或冷光板等等；換流器原理係經由開關電晶體之切 換導通達成改變頻率之目的’不過以開關電晶體之邏輯運 作方式，使輸出之驅動電源為數位邏輯形式之交流方波， 而方波訊號本身則會在基本波以外形成多數奇次諧波，不 但高次諳波成分形成電路雜訊，低次諧波成分更產生音頻 噪音’造成人耳在聽覺上感到尖銳、刺耳。 當然’負載操作頻率以外頻段的雜訊部分皆可設計濾 波器加以;慮除，且一般開關電晶體後級亦會設計有渡波器 將開關切換所產生的高頻雜訊濾除’同時也可濾除相同頻 段範圍内由方波訊號夾帶的高次諧波成分；然，濾波所用 的電感元件佔有相當的電路空間，如此若需過濾所有諧波 及高頻雜訊’所設計之濾波器則需使用大量的電感元件， 無疑增加整體電路的體積。再者，基本波以外的諧波組成 當中’越低次諧波的能量功率越大，不但須使用較大電感 才得以濾除’且為了將較高功率的低次諧波濾除，勢必會 1351805 對基本波的功率造成干擾，因而降低電路驅動效率。 我國專利公告第1309910號及第456104號皆有針對換 流器之輸出諧波成分提出對應之諧波消除方式，本發明人 亦致力於提出可以簡單的電路設計有效濾除負載操作頻率 以外的雜訊，同時滿足小體積、高效率的換流器驅動電路 需求。 【發明内容】 本發明之主要目的在於提供一種換流器之噪音抑制方 法，可有效降低甚至消除因為開關切換造成人耳在聽覺上 镳 感到尖銳、刺耳的聲音，滿足電子產品中需要達到低噪音 的需求。 為達成上述目的，本發明所提供一種換流器之噪音抑 制方法係以具有正半週波之二週期方波訊號為基礎，利用 選擇性諧波抑制脈波寬度調變（sdective harm〇nic elimination pulse width m〇dulati〇n，SHE_pwM)技術產生 之二脈波寬度調變訊號’分別於每半週期交錯輸入上述換 流器之上、下臂邏輯電晶體；各該脈波寬度調變訊號於單· -週期中N個相位角度的振幅為零，該些相位角度係以τ /2為中。於相反相位方向兩兩對稱。該二脈波寬度調變訊 號用以消除換流器之輸出波形中自低次諧波起之多個奇次 諧波目此操作時不具有音頻噪音；該脈波寬度調變訊號 於四分之厂週波之内的相位角度具有以下關係： * ’ 1=1，2,3···μ (S) 4 其申M=N/2，ni = 2i+l，ακ為各該相位角度。 【實施方式】 為了詳細說明本發明之結構、特徵及功效所在，茲舉 以下較佳實施例並配合圖式說明如後，其中·· 第一圖為本發明第一較佳實施例所提供之電路功能示 意圖； 第二圖為上述第一較佳實施例所提供之電路結構示意 圖， 第三圖為上述第一較佳實施例所提供諧波抑制技術之 基礎週期方波之波形示意圖； 第四圖為上述第一較佳實施例所提供諧波抑制技術之 脈波寬度調變訊號之波形示意圖，表示對第三圖之波形凹 陷所對應之凹陷自由度相位關係； 第五圖為上述第一較佳實施例所提供換流器之輸出波 第六圖A為上述第一較佳實施例所提供換流器以基礎 週期方波輸入所得之輪出電壓波形，表示於頻域之 佈示意圖； 73 第六圖B為上述第一較佳實施例所提供換流器以脈 寬度調變減輸人所得之輸出t壓波形，表示於 ^ 波分佈示意圖； ％ 第七圖本發明第二較佳實施顺提供之電 圖。 '、攝不思 閱如第-及第二圖所示，為本發明第一較佳實施 例所提供-換流器1G之噪音抑制方法之電路功能結構，該 換流器10係對一可程式化晶片20經過特定譜波抑制技術 的設計規劃，以將-直流電源3G轉換為交流訊號輸出至一 低通滤波H 4G處理，可使輸出至1載5"訊號不具有 音頻嗓音，其中： 該直流電源30為提供該換流器10之直流操作為主， 可使用如整流器等將市用交流電源經變壓轉換，在此僅為 舉例說明，並非做為限制要件。 該換流器H)具有多數個邏輯電路12、多數個輸入端 』M以及—輸出端組16 ;該些邏輯電路12主要以兩兩相VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to harmonic suppression technology, and more particularly to a noise suppression method for an inverter. [Prior Art] In many electronic products, the drive of many loads requires the use of an inverter or a frequency converter to convert the mains frequency of 60 Hz into the frequency required by the load. Commonly, inverter-driven products such as motors and solar energy are required. Plate, cold cathode tube or cold plate, etc.; the converter principle is switched through the switching transistor to achieve the purpose of changing the frequency 'but the logic operation of the switching transistor, so that the output driving power supply is a digital logic form of communication Square wave, and the square wave signal itself will form most odd harmonics outside the fundamental wave. Not only the high-order chopping component forms circuit noise, but the low-order harmonic component produces audio noise, which causes the human ear to feel sharp in the sense of hearing. , harsh. Of course, the noise part of the frequency band other than the load operation frequency can be designed by the filter; in addition, the general stage of the switching transistor will also be designed with a wave filter to filter the high frequency noise generated by the switch switching. Filter out the higher harmonic components entrained by the square wave signal in the same frequency range; however, the inductive components used for filtering occupy a considerable circuit space, so if you want to filter all harmonics and high frequency noise, the filter is designed. A large number of inductive components are required, which undoubtedly increases the overall circuit size. Furthermore, among the harmonic components other than the fundamental wave, the higher the energy power of the lower harmonic, the larger the power must be filtered out, and in order to filter out the higher power lower harmonics, it is bound to 1351805 interferes with the power of the fundamental wave, thus reducing circuit drive efficiency. China Patent Publication No. 1309910 and No. 456104 have corresponding harmonic elimination methods for the output harmonic components of the inverter, and the inventors have also proposed to simplify the circuit design to effectively filter out the mismatch of the load operation frequency. At the same time, it meets the needs of small-volume, high-efficiency inverter drive circuits. SUMMARY OF THE INVENTION The main object of the present invention is to provide a noise suppression method for an inverter, which can effectively reduce or even eliminate the sharp and harsh sound of the human ear due to switch switching, and meet the need for low noise in electronic products. Demand. In order to achieve the above object, the noise suppression method for an inverter according to the present invention is based on a two-period square wave signal having a positive half cycle, and uses selective harmonic suppression to suppress pulse width modulation. Width m〇dulati〇n, SHE_pwM) The two-pulse width modulation signal generated by the technology is interleaved into the above-mentioned inverter upper and lower arm logic transistors in each half cycle; each of the pulse width modulation signals is in a single • The amplitude of the N phase angles in the period is zero, and the phase angles are centered on τ /2. Symmetrical in the opposite phase direction. The two-pulse width modulation signal is used to eliminate multiple odd harmonics from the lower harmonics in the output waveform of the converter. The operation does not have audio noise; the pulse width modulation signal is in four points. The phase angle within the plant cycle has the following relationship: * ' 1 = 1, 2, 3 · · · μ (S) 4 Its M = N/2, ni = 2i + l, α κ is the phase angle. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the structure, features, and advantages of the present invention in detail, the following preferred embodiments are illustrated in the accompanying drawings, wherein the first figure is provided by the first preferred embodiment of the present invention 2 is a schematic diagram of a circuit structure provided by the first preferred embodiment, and FIG. 3 is a schematic diagram of a waveform of a fundamental periodic square wave of the harmonic suppression technique provided by the first preferred embodiment; The figure shows the waveform of the pulse width modulation signal of the harmonic suppression technology provided by the first preferred embodiment, and shows the phase relationship of the depression degree corresponding to the waveform depression of the third figure; The output waveform of the converter provided in the preferred embodiment is a schematic diagram of the distribution of the wheel voltage waveform obtained by the inverter according to the first preferred embodiment in the basic period square wave input, which is shown in the frequency domain; 73 is a schematic diagram of the output t-voltage waveform obtained by the inverter according to the first preferred embodiment provided by the pulse width modulation and reduction input, which is shown in the waveform distribution; The second preferred embodiment of FIG out electrical cis provided. As shown in the first and second figures, the circuit function structure of the noise suppression method of the inverter 1G is provided for the first preferred embodiment of the present invention, and the inverter 10 is one-to-one. The programmed wafer 20 is designed by a specific spectral suppression technique to convert the -DC power supply 3G into an AC signal output to a low-pass filtering H 4G process, so that the output to the 1 carrier 5" signal does not have an audio voice, wherein: The DC power supply 30 is mainly for the DC operation of the inverter 10, and the commercial AC power supply can be converted and transformed by using a rectifier, etc., which is merely an example and is not a limitation. The converter H) has a plurality of logic circuits 12, a plurality of input terminals 』M and an output terminal group 16; the logic circuits 12 are mainly two-two phases
St第03一二邏輯電晶體Q1、Q2及第三、第四邏 =電曰曰體Q3、Q4相互並接形成之橋式電路，其中第一、 第2四^體Q1、Q4為上臂，第二、第三邏輯電晶體 邏下#，各該輸入端組14分別對應電性連接各該 該暹錄路12 ’ M本實關所提供由金屬氧化物半導體製成 二：路12之邏輯電晶體Φ、Q2、Q3、Q4為例，各 ΐ調3=4^1接收可程式化晶片2Q所輸出之脈波寬 止=輪人各該邏輯電晶體32閘極使之導通或戴 四邏:電皮寬度調變訊號係以同步控制該第一、第 第：、。Q、Q4之運作，以及以同步控制該第二、 電曰^輯電日日體Q2、Q3之運作。紋該第—與第四邏輯 a Q1、Q4或該第二與第三邏輯電晶體Q3、Q4接收 (S) 6 1351805St 03th logic transistor Q1, Q2 and third and fourth logic = electric body Q3, Q4 are connected in parallel with each other to form a bridge circuit, wherein the first and second body Q1, Q4 are upper arms, The second and third logic transistors are arranged under the #, each of the input groups 14 respectively corresponding to the electrical connection of the Siam Road 12' M. The real gate provided by the metal oxide semiconductor is made of two: the logic of the road 12 The transistors Φ, Q2, Q3, and Q4 are taken as an example, and each of the ΐ3=4^1 receives the pulse width of the programmable chip 2Q output = the turn of the logic transistor 32 turns on or turns on the four Logic: The skin width modulation signal controls the first and the first: in synchronization. The operation of Q and Q4, as well as the simultaneous control of the operation of the second, electric, and electric Japanese and Japanese bodies Q2 and Q3. The first and fourth logics a Q1, Q4 or the second and third logic transistors Q3, Q4 receive (S) 6 1351805
同步之脈波寬度調變訊號，可將該些輸入端組14之一第一 及一第四輸入端組142、148電性連接該可程式化晶片20 之一第一接腳22，該些輸入端組14之一第二及一第三輸 入端組144、146電性連接該可程式化晶片2〇之一第二接 腳24 ;因此該可程式化晶片20可利用兩組脈波寬度調變 訊號，分別自該第一接腳22控制該第一、第四邏輯電晶體 Q卜Q4觸發導通以及自該第二接腳24控制該第二、第三 邏輯電晶體Q2、Q3觸發導通。 該可程式化晶片20係以如第三圖所示具有正半週波 之二週期方波SQ1、SQ2訊號為基礎，利用選擇性諧波抑 制脈波寬度調變（selective harmonic elimination pulse widthThe first and fourth input groups 142 and 148 of the input terminal group 14 are electrically connected to one of the first pins 22 of the programmable chip 20, One of the second and third input groups 144, 146 of the input terminal group 14 is electrically connected to one of the second pins 24 of the programmable wafer 2; thus, the programmable wafer 20 can utilize two sets of pulse widths. The modulation signal is controlled from the first pin 22 to control the first and fourth logic transistors Q4 and Q4 to be turned on, and the second and third logic transistors Q2 and Q3 are controlled to be turned on from the second pin 24. . The programmable chip 20 is based on a two-period square wave SQ1 and SQ2 signal having a positive half cycle as shown in the third figure, and uses selective harmonic suppression pulse width modulation (selective harmonic elimination pulse width).
modulation，SHE-PWM)技術產生如第四圖所示之二脈波 寬度調變訊號PWM卜PWM2，控制換流器各邏輯電路12 開關，使上臂Q卜Q4、下臂Q2、Q3交替切換達成換流且 ^制諸波之目的：請配合以下推論方程式參照，本發明所 提供換流^之嚼音抑制方法係由可程式化“ 2()以譜波 抑制技術規劃換流器1()之輸出波形，將自低次諸波起^多 個奇數次触消除，因此使該直流電源3()轉流器⑺之 ^輯轉換為如第五圖所示之以四分之—週期對稱之方波交 流訊號，並由該換流器1〇之輸出端組16輸出。 由於任-非弦波之週期性波形f⑴皆可由傅立葉級 數分析表示為： J 00 fit) = 2 Λ〇 + Σ K sin(w〇/) + bn cos(«iy〇} ”=丨 …··.式（1)，The modulation, SHE-PWM technology generates a two-pulse width modulation signal PWM Bu PWM2 as shown in the fourth figure, and controls each logic circuit 12 switch of the inverter to alternately switch the upper arm Q b Q4 and the lower arm Q2 and Q3. The purpose of commutating and controlling the waves: Please refer to the following inference equation for reference. The method for suppressing the chewing sound provided by the present invention is to program the converter 2 (1) by the spectral wave suppression technique. The output waveform is eliminated from the lower-order waves by a plurality of odd-numbered touches, so that the DC power supply 3() converter (7) is converted to a quadruple-cycle symmetry as shown in the fifth figure. The square wave AC signal is output by the output group 16 of the inverter 1. Since the periodic waveform f(1) of the arbitrary-non-sine wave can be expressed by Fourier series analysis: J 00 fit) = 2 Λ〇+ Σ K sin(w〇/) + bn cos(«iy〇} ”=丨...··. (1),
1351805 其中η為f(t)的諧波次數， °〇 = - V f(t)d{o>t) γ ……式⑵， :χ ···…式(3)， bn~~^t f(.t)cos(nat)d^t) ( · .若式⑷等於零，剩下式(3)，則該波形稱為偶函數對 稱:^式（3)等於零’剩下式⑷，則該波形稱為奇函數斜 稱’右式（3)與式⑷對偶數n等於零且僅辭奇數心 該波形稱為半波函數對稱。 因此’該可程式化晶片20之譜波規劃消除原理是以如 第三圖所示正半週波之週期方波SQ卜SQ2作為基礎對 波作凹陷，亦即抑制該週期方波SQ1、SQ2之每―正 中多個相位角度的振幅，成為如第四圖所示之二脈 調變訊號觸1、P键為时之一週期對稱之奇函數ς 形，藉由凹陷所帶來的自由度可控制換流器π)所輸出電ί 之基本波或魏成分大小。請參閱如第五圖所示，由換户 器10欲規劃之輪出電壓波形，即對應可得該程式化晶= 20對週期方波之規劃，使該些受抑制的相位角度以π 中心於相反相位方向兩兩對稱；故於四分之一週期内，右 多個自由度變數a,、心“.^為欲規劃之自由度的相 度，當波形_為Μ個角度，就會有Μ個欲控制的既定体 件〜規劃之波形可以寫為非線性聯立方程式如下、 式： 8 fi(a\,a2..£cM) h f2(al,a2..jau) - h -ΓΜ- 式（5); 規晝波形的傅立葉分析與推導如下，進而求解規劃之 自由度變數〇：1、CK2.··0：!!: 1 * 式（6); /(0 -~a0^^[an sin(nwt) + bn cos(nmt)] 2 n=\ 使a〇=0及bn=0，則 式⑺； α» = ~ f f (t)sia{nat)d(at) 根據第五圖所示，對於奇數n，使 αη = ^ηωί)ά(ωή + ζ\ΐη(ηωί)ά(ωί)...+ sm(nmt)d(at)] 4 Μ ηπ …·式(8)， 其中 0<α1<α2.··<ατΜ —Σ㈠)《+1 c〇s⑽欠 Μ個自由角度代入式（8)必須要等於零才能消除規劃 之譜波’其方程式可表示為： i=l,2, -Μ · 其中ni = 2i+l , ακ為各該相位角度； 乂 (α) =丄Σ(_1广1 cos ημκ = 〇 式（9) 以圖不波形而言’欲規劃消除3次、5次、7次、9次、 11次、13次、15次、17次及19次諧波，故自由度變數有 :1 ' α2、α4、〇:5、α6、α7、α8 及 α9,而欲 工制之既定條件Μ有r3、r5、r7、、ru、、 H7及rl9 j將自由角度變數與既定條件代入式⑼後再代 入式⑸可㈣—非祕聯立方她如下式，求解其非線性 聯立方餘可 _α1、α2、α3、α4、α5、α6、^、 1351805 α8、α9九個自由度變數解： 'cos 3α, - cos 3α2 + cos 3α3 - c〇s 3α4 + cos 3as cos 5α, - cos 5α2 + cos 5α3 - cos 5α4 + cos 5α5 cos 7α, - cos 7«2 + cos 7a3 - cos 7a4 + cos 7as cos 9a, - cos 9a2 + cos 9a3 - cos 9or4 + cos 9a5 F(a) = cos 1 la, - cos 1 la2 + cos 1 la3 - cos 1 la4 + cos 1 las cos 13% - cos 13a2 + cos 13a3 - cos 13a4 + cos 13a5 cos 15a, - cos 15a2 + cos 15or3 - cos 15a4 + cos 15a5 cos 17a, -cosl7a2 +cosl7or3 -cosl7a4 +cosl7a5 cos 19a, -cos19qt2 +cosl9a3 — cosl9a4 +cosl9ar5 -cos 3a6 + cos 3α7 - cos 3ag + cos 3α9 >3 -cos 5α6 + cos 5α7 - cos 5α8 + cos 5«9 5/-5 -cos 7a6 + cos 7a7 - cos 7a8 + cos 7a9 7r7 -cos 9a6 + cos 9αΊ - cos 9as + cos 9ag 9r9 -cos 1 la6 + cos 1 \αΊ - cos 1 la8 + cos 1 \a9 7t —— 4 llru -cos 13a6 + cos 13a7 - cos 13a8 + cos 13<ar9 13r13 -cos 15a6 + cos 15a1 - cos 15ag + cos 15a9 15rl5 -cos 17a6 + cos 11αΊ - cos 17ag + cos 1 la9 17rl7 -cosl9ar6 +cosl9ar7 -cosl9arg +cosl9ar9 1% 式（10)。 因此若以消除19次諧波以前的低次諧波設計，該可程 式化晶片20之則規劃產生如第四圖所示之二脈波寬度調 變訊號PW1VQ、PWM2，將各週期方波SQ1、SQ2於各相 位角度 α 1、α 2、α 3、α 4、α 5、α 6、α 7、〇: 8 及 α 9 凹陷’藉由凹陷所帶來的自由度即可抑制換流器1〇所輸出 電壓之基本波以外低次諧波成分。請參閱如第六圖所示， 當可程式化晶片以如第三圖之週期方波Sqi、SQ2控制該 換流器10，則得該換流器10之輸出電壓波形於頻域之諧 波分佈如第六圖Α所示，除了基本波更有明顯的低次諧波 成分；相較於以如第四圖之脈波寬度調變訊號、 PWM2控制職—1()，麟該誠㈣之輪出電壓波 形於頻域之諧波分佈如第六圖B所示，明顯可見，基本皮 1351805 以外的低次諧波成分皆有效被抑制。 _波器40電性連接該換流器1〇之輸出端組16，係 =多個濾、波it件42、44將換流器1G輸出之方波交流訊號 、為正弦波喊提供貞载5〇所需，本實施靖提供者為 以低通濾波器濾除換流器1G所輸出的高頻諧波，同時可渡 $換流器10開關電路12所產生的高頻切換雜訊；由於‘ 流器10低次諸波成分已被抑制，因此以小於該換流器1〇 • 輸出之諸波頻率即可作為該遽波器40之低通遽波截止頻 率。該些遽;皮元件42、44具有特定之電感、電容條件，設 計之前，首先了解負載50之元件特性，例如使用紅測 量儀等，測量負載50在不同操作頻率下之對應特性阻抗； 對於有特定操作頻率需求之負載5〇而言，越高特性阻抗之 負載50則該濾波器40需設計有越高電感值的等效電感元 當然，在負载5〇操作頻率可調整之彈性範圍内，可提 肖操作頻率以維持貞載50之特性阻抗。經由上述脈波寬度 矚觸峨PWM1、PWM2抑觀次讀職生之音頻噪音 部分，使賴流H 1G輸出方波交流訊號之基頻僅夾帶高次 譜波部分’因此由電感公式XL = 2;rfL可知，對於後級之 該濾波器40而言’當濾波頻段越高，·所需要的等效電 感之電感值就可越小。如此一來，低電感即可集中滤掉高 次諧波成分或電晶體開關切換產生的高頻雜訊干擾，且低 電感元件可使該濾、波器4〇所佔用之電路空間體積大幅縮 因此本發明所提供換流器10之噪音抑制方法，可使最 後輸出至負載5G之玉作波形為無諸波成分之正弦波；至於 因應不同負載50元件特性時，僅需改變基本波的操作頻率 及對應調整驗器4()的截止頻率，同樣可在有效節省電路 體積下:抑制電路之音_音或高頻雜訊干擾。 、值=一提的是，本發明所提供換流器之噪音抑制方法 並不限定如上述實_所娜之全橋式電路所構成的換流 器10:對於如第七圖所示本發明第二較佳實施例所提供一 換流器60之電路結構而言’關於第—圖所示之電路功能 亦可對僅以二邏輯電晶體Q5、Q6所串接之半橋式電路且 有等效之應用。差職在於，在相同直流電源3Q之輪入電 壓下’全橋式的最大輸出電壓料橋式的兩倍，對於同功 率條件下，全橋式的輸出電流與開關通過之電流只要一 半，g然，全橋式之邏輯電晶體之財壓、耐流值都可以比 較小，單顆電晶體開關的體積也會較小，對於電子產品小 型化有些幫助，不過因半橋式電路成本較低，故雖單顆電 晶體開關耐壓、耐流_高，但可刺於巾低功率需求之 電子產品。 综上所陳，本發明於前述實施例中所揭露的構成元 件’僅為舉例說明’並非用來限制本案之範圍，其他等效 疋件的替代或變化，亦應為本案之申請專利範圍所涵蓋。 1351805 【圖式簡單說明】 第一圖為本發明第一較佳實施例所提供之電路功能示 意圖， 第二圖為上述第一較佳實施例所提供之電路結構示意 圖； 第三圖為上述第一較佳實施例所提供諧波抑制技術之 基礎週期方波之波形示意圖；1351805 where η is the harmonic order of f(t), °〇= - V f(t)d{o>t) γ ...... Equation (2), :χ ···... Equation (3), bn~~^tf (.t)cos(nat)d^t) ( · . If equation (4) is equal to zero, leaving equation (3), the waveform is called even function symmetry: ^ (3) is equal to zero 'remaining equation (4), then The waveform is called the odd function oblique scale 'Right equation (3) and Equation (4). The even number n is equal to zero and only the odd number of hearts is called the half wave function symmetry. Therefore, the principle of spectral wave planning elimination of the programmable wafer 20 is As shown in the third figure, the periodic square wave SQ and SQ2 of the positive half cycle are used as a basis for the wave to be recessed, that is, the amplitude of the plurality of phase angles of each of the periodic square waves SQ1 and SQ2 is suppressed, as shown in the fourth figure. The two-pulse modulation signal shows that the P-type and P-keys are one-cycle symmetrical odd-function ς, and the fundamental wave or Wei component of the output voltage of the inverter π) can be controlled by the degree of freedom brought by the depression. size. Please refer to the round-out voltage waveform to be planned by the changer 10 as shown in the fifth figure, that is, the corresponding programmable crystal = 20 pairs of periodic square waves can be obtained, so that the suppressed phase angles are π centers. Symmetrical in the opposite phase direction; therefore, in the quarter cycle, the right multiple degrees of freedom variable a, the heart ".^ is the degree of freedom of the degree of freedom to be planned, when the waveform _ is an angle, There is a certain body to be controlled ~ the planned waveform can be written as a nonlinear simultaneous equation as follows: 8 fi(a\,a2..£cM) h f2(al,a2..jau) - h - ΓΜ- (5); Fourier analysis and derivation of the gauge waveform are as follows, and then solve the degree of freedom of the program 〇: 1, CK2.··0:!!: 1 * Equation (6); /(0 -~ A0^^[an sin(nwt) + bn cos(nmt)] 2 n=\ Let a〇=0 and bn=0, then equation (7); α» = ~ ff (t)sia{nat)d(at) According to the fifth figure, for an odd number n, let αη = ^ηωί)ά(ωή + ζ\ΐη(ηωί)ά(ωί)...+ sm(nmt)d(at)] 4 Μ ηπ ... (8), where 0 <α1<α2.··<ατΜ—Σ(1)) “+1 c〇s(10) owes a free angle substitution equation (8) must wait Zero can eliminate the planned spectral wave', and its equation can be expressed as: i=l,2, -Μ · where ni = 2i+l , ακ is the phase angle; 乂(α) =丄Σ(_1广1 cos ημκ = 〇 (9) In the case of non-waveforms, you want to plan to eliminate 3, 5, 7, 9, 11, 13th, 15th, 17th, and 19th harmonics, so the degrees of freedom have :1 ' α2, α4, 〇: 5, α6, α7, α8 and α9, and the established conditions of the system are r3, r5, r7, ru, H7 and rl9 j to substitute the free angle variable with the established condition. After equation (9), substituting into equation (5) can be (4) - non-secret joint cube. She is as follows, and solves the nonlinear joint cubic _α1, α2, α3, α4, α5, α6, ^, 1351805 α8, α9 nine degrees of freedom variables Solution: 'cos 3α, - cos 3α2 + cos 3α3 - c〇s 3α4 + cos 3as cos 5α, - cos 5α2 + cos 5α3 - cos 5α4 + cos 5α5 cos 7α, - cos 7«2 + cos 7a3 - cos 7a4 + Cos 7as cos 9a, - cos 9a2 + cos 9a3 - cos 9or4 + cos 9a5 F(a) = cos 1 la, - cos 1 la2 + cos 1 la3 - cos 1 la4 + cos 1 las cos 13% - cos 13a2 + cos 13a3 - cos 13a4 + cos 13a5 cos 15a, - cos 15a2 + cos 15or3 - cos 15a4 + cos 15a5 cos 17a, -cosl7a2 +cosl7or3 -cosl7a4 +cosl7a5 cos 19a, -cos19qt2 +cosl9a3 — cosl9a4 +cosl9ar5 -cos 3a6 + cos 3α7 - cos 3ag + cos 3α9 >3 -cos 5α6 + Cos 5α7 - cos 5α8 + cos 5«9 5/-5 -cos 7a6 + cos 7a7 - cos 7a8 + cos 7a9 7r7 -cos 9a6 + cos 9αΊ - cos 9as + cos 9ag 9r9 -cos 1 la6 + cos 1 \αΊ - Cos 1 la8 + cos 1 \a9 7t —— 4 llru -cos 13a6 + cos 13a7 - cos 13a8 + cos 13<ar9 13r13 -cos 15a6 + cos 15a1 - cos 15ag + cos 15a9 15rl5 -cos 17a6 + cos 11αΊ - cos 17ag + cos 1 la9 17rl7 -cosl9ar6 +cosl9ar7 -cosl9arg +cosl9ar9 1% Equation (10). Therefore, if the low-order harmonic design before the 19th harmonic is eliminated, the programmable chip 20 is planned to generate the two-pulse width modulation signals PW1VQ and PWM2 as shown in the fourth figure, and the periodic square wave SQ1. , SQ2 at each phase angle α 1 , α 2 , α 3 , α 4 , α 5 , α 6 , α 7 , 〇 : 8 and α 9 depression ' can reduce the inverter by the degree of freedom brought by the depression 1〇 Low-order harmonic components other than the fundamental wave of the output voltage. Referring to FIG. 6 , when the programmable wafer controls the inverter 10 with the periodic square waves Sqi and SQ 2 as shown in FIG. 3 , the output voltage waveform of the converter 10 is harmonic in the frequency domain. As shown in the sixth figure, the basic wave has more obvious lower harmonic components; compared with the pulse width modulation signal as shown in the fourth figure, PWM2 control position -1 (), Lin Chengcheng (4) The harmonic distribution of the wheel voltage waveform in the frequency domain is as shown in the sixth figure B. It is obvious that the low-order harmonic components other than the basic skin 1351805 are effectively suppressed. The wave device 40 is electrically connected to the output terminal group 16 of the inverter 1 , and the plurality of filters and wave devices 42 and 44 provide a square wave alternating current signal output by the inverter 1G to provide a sine wave shouting 5〇 required, the present embodiment provides a low-pass filter to filter out the high-frequency harmonics outputted by the inverter 1G, and can exchange the high-frequency switching noise generated by the converter 10 switching circuit 12; Since the low-order wave components of the streamer 10 have been suppressed, the wave frequencies smaller than the inverter output can be used as the low-pass chopping cutoff frequency of the chopper 40. The skin elements 42 and 44 have specific inductance and capacitance conditions. Before designing, first understand the component characteristics of the load 50, for example, using a red measuring instrument, etc., to measure the corresponding characteristic impedance of the load 50 at different operating frequencies; For a load of a specific operating frequency requirement, the higher the characteristic impedance of the load 50, the higher the inductance value of the filter 40 is to be designed. Of course, in the elastic range where the load 5 〇 operating frequency can be adjusted, The operating frequency can be increased to maintain the characteristic impedance of the load 50. Through the above-mentioned pulse width 瞩 峨 PWM1, PWM2 suppresses the audio noise part of the secondary reading, so that the fundamental frequency of the tributary H 1G output square wave AC signal only entrains the high-order spectral part's ;rfL knows that for the filter 40 of the latter stage, 'when the filter frequency band is higher, the inductance value of the equivalent inductance required can be smaller. In this way, the low inductance can concentrate the high-frequency noise interference generated by the high-order harmonic component or the switching of the transistor switch, and the low-inductance component can greatly reduce the space of the circuit space occupied by the filter and the filter device. Therefore, the noise suppression method of the inverter 10 provided by the present invention can make the waveform of the final output to the load 5G be a sine wave without the wave component; as for the operation of the 50 component according to different loads, only the basic wave operation needs to be changed. The frequency and the cutoff frequency of the corresponding calibrator 4() can also be used to effectively save the circuit volume: suppress the sound of the circuit or the high frequency noise interference. Value = mention that the noise suppression method of the inverter provided by the present invention is not limited to the inverter 10 constructed as the above-described full bridge circuit: for the present invention as shown in the seventh figure In the circuit structure of an inverter 60 provided by the second preferred embodiment, the circuit function shown in the first figure can also be a half bridge circuit connected in series with only two logic transistors Q5 and Q6. Equivalent application. The difference is that under the same DC power supply 3Q wheel-in voltage, the full-bridge maximum output voltage bridge is twice as large. For the same power condition, the full-bridge output current and the current through the switch are only half, g However, the full-bridge logic transistor can be relatively small in terms of financial pressure and current resistance, and the volume of a single transistor switch will be small, which is helpful for miniaturization of electronic products, but the cost of the half-bridge circuit is low. Therefore, although the single transistor switch is resistant to pressure and current, it can pierce the electronic products with low power requirements. In conclusion, the constituent elements of the present invention disclosed in the foregoing embodiments are merely illustrative and are not intended to limit the scope of the present invention. The alternatives or variations of other equivalents should also be the scope of the patent application of the present application. Covered. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a circuit function provided by a first preferred embodiment of the present invention, and FIG. 2 is a schematic diagram of a circuit structure provided by the first preferred embodiment; A waveform diagram of a fundamental periodic square wave of a harmonic suppression technique provided by a preferred embodiment;
第四圖為上述第一較佳實施例所提供諧波抑制技術之 脈波寬度調變訊號之波形示意圖，表示對第三圖之波形凹 陷所對應之凹陷自由度相位關係； 第五圖為上述第一較佳實施例所提供換流器之輸出波 形不意圖； 、第/、圖A為上述第一較佳實施例所提供換流器以基礎 週期方波輸人所得之㈣電壓彡祕，表示於頻域之諸波分 佈示意圖；The fourth figure is a waveform diagram of the pulse width modulation signal of the harmonic suppression technique provided by the first preferred embodiment, and shows the phase relationship of the depression degree corresponding to the waveform depression of the third figure; The output waveform of the inverter provided by the first preferred embodiment is not intended; and FIG. A is the voltage of the inverter provided by the above-mentioned first preferred embodiment by the fundamental period square wave input. A schematic diagram showing the distribution of waves in the frequency domain;
U B為上述第—較佳實關所提供換流器以脈波 變峨輸Μ得之—電壓_ 波分佈示意圖； 圖 第圖本發明第二較佳實施例所提供之電路結構示意 【主要元件符號說明】 1〇、60換流^ 12邏輯電路 AG. Q Q3、Q4、Qs、Q6邏輯電晶體 13 1351805 14輸入端組 144第二輸入端組 148第四輸入端組 20可程式化晶片 24第二接腳 SQ1、SQ2週期方波 142第一輸入端組 146第三輸入端組 16輸出端組 22第一接腳 30直流電源 PWM1、PWM2脈波寬度調變訊號 α 1、α2··_ αμ自由度變數 40低通濾波器 42、44濾波元件 50負載UB is a schematic diagram of the voltage-wave distribution provided by the inverter according to the first-best implementation of the above-mentioned preferred embodiment. FIG. 1 is a schematic diagram of the circuit structure provided by the second preferred embodiment of the present invention. DESCRIPTION OF SYMBOLS 1〇, 60 commutation ^ 12 logic circuit AG. Q Q3, Q4, Qs, Q6 logic transistor 13 1351805 14 input terminal group 144 second input terminal group 148 fourth input terminal group 20 programmable wafer 24 Second pin SQ1, SQ2 periodic square wave 142 first input terminal group 146 third input terminal group 16 output terminal group 22 first pin 30 DC power supply PWM1, PWM2 pulse width modulation signal α 1, α2··_ Αμ degrees of freedom variable 40 low pass filter 42, 44 filter component 50 load