33941twf.doc/n 201140877 1 «/»✓〆 vrvv-» Γ\ν 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種發光元件及其製造方法，且特別 是有關於一種發光二極體（light-emitting diode, LED)晶 片及其製造方法。 【先前技術】 氮化鎵類（GaN-based)的半導體材料已被證實極具 潛力以應用於製作發光二極體’且其發光波長所涵蓋的範 圍可從紅外光、可見光至紫外光。因此，近年來氮化錄類 半導體逐漸受到廣大的重視。 ' 一般而言，發光二極體的亮度取決於内部量子效率及 光取出效率，其中内部量子效率為電子與電洞結合的比 例。然而’由於空氣與氮化鎵材料的折射率差❸】5，使 得發光二極體的發光層所產生的光易因被氮化鎵與空氣的 介面全反射’而局限在發光二極體㈣，造成光取出效率 明顯偏低。 士 許多研究ί出提高光取出效率的方法。舉例而 二/中-種方法為猎由對晶片_部作表面處理，來破 =反射條件，以提高光取岐率。此表面處理例 面粗化、改變奸二極體的形貌等 ;片，頂，露_半導體層作處理m 取出效率還是會受到一定程度的限制。 此外另種方法為將氮化鎵半導體層與基板分離， 201140877 P51990003TW 33941twf.doc/n 然後在tub料導n層上形絲憾構，最 將氮化嫁半導體層黏回基板上，藉此提高絲出 而j此種方法過㈣於繁雜，考慮卿體散熱不佳的 問題。 、 【發明内容】 、本發明提供一種發光二極體晶片的製作方法，其可以 較為簡單的製程步驟製作出光取出效率高的發光二極體晶 片。 本發明提供一種發光二極體晶片，其具有較高的光取 出效率。 本發明之一實施例提出一種發光二極體晶片的製造 方法，其包括下列步驟。此製造方法提供一基板。此外， 在基板上形成一缓衝層（buffer iayer)。再者，在緩衝層 上形成一第一摻雜態半導體層。另外，在第一摻雜態半導 體層上形成一發光層。除此之外，在發光層上形成一第二 摻雜態半導體層。再者，利用一穿透基板的光束照射於緩 衝層一部分與第一摻雜態半導體層之與緩衝層的此部分鄰 接之一第一部分上，以使緩衝層的此部分與第一摻雜態半 導體層的第一部分產生一反應。另外，蝕刻經反應的緩衝 層的此部分與第一摻雜態半導體層的第一部分，以形成至 少一空洞。 本發明之另一實施例提出一種發光二極體晶片，包括 —基板、一圖案化緩衝層、一第一摻雜態半導體層、一發 20114087733941twf.doc/n 201140877 1 «/»✓〆vrvv-» Γ\ν VI. Description of the Invention: [Technical Field] The present invention relates to a light-emitting element and a method of manufacturing the same, and more particularly to a light-emitting device A light-emitting diode (LED) wafer and a method of manufacturing the same. [Prior Art] Gallium nitride-based (GaN-based) semiconductor materials have been proven to have potential for use in the fabrication of light-emitting diodes, and their wavelengths range from infrared light to visible light to ultraviolet light. Therefore, in recent years, nitride-based semiconductors have received increasing attention. In general, the brightness of a light-emitting diode depends on the internal quantum efficiency and the light extraction efficiency, where the internal quantum efficiency is the ratio of electrons to holes. However, due to the difference in refractive index between the air and the gallium nitride material, the light generated by the light-emitting layer of the light-emitting diode is easily confined to the light-emitting diode by the interface of the gallium nitride and the air. , resulting in significantly lower light extraction efficiency. Many studies have developed ways to improve the efficiency of light extraction. For example, the second/middle method is to surface the wafer to the surface of the wafer to break the reflection condition to improve the light extraction rate. This surface treatment example is roughened, the morphology of the eclipse is changed, and the film, top, and dew-semiconductor layers are processed to remove m. The removal efficiency is still limited to some extent. In addition, another method is to separate the gallium nitride semiconductor layer from the substrate, and then form a wire on the n-layer of the tube material, and finally bond the nitrided semiconductor layer back to the substrate, thereby improving The method of silk out and j (4) is complicated, considering the problem of poor heat dissipation of the body. SUMMARY OF THE INVENTION The present invention provides a method for fabricating a light-emitting diode wafer, which can produce a light-emitting diode wafer having high light extraction efficiency in a relatively simple process step. The present invention provides a light emitting diode wafer having a high light extraction efficiency. One embodiment of the present invention provides a method of fabricating a light emitting diode wafer comprising the following steps. This manufacturing method provides a substrate. Further, a buffer iayer is formed on the substrate. Further, a first doped semiconductor layer is formed on the buffer layer. Further, a light-emitting layer is formed on the first doped semiconductor layer. In addition to this, a second doped semiconductor layer is formed on the light-emitting layer. Furthermore, a light beam penetrating the substrate is irradiated onto a portion of the buffer layer adjacent to a portion of the first doped semiconductor layer adjacent to the portion of the buffer layer such that the portion of the buffer layer and the first doped state The first portion of the semiconductor layer produces a reaction. Additionally, the portion of the reacted buffer layer is etched with the first portion of the first doped semiconductor layer to form at least one void. Another embodiment of the present invention provides a light emitting diode chip, including a substrate, a patterned buffer layer, a first doped semiconductor layer, and a hair.
Wiyyuuu^rw 33941twf.doc/n 光層、-第二#_半導體層 上。第-摻雜態半導體層配== —I:二酬上，位於緩衝層，二 方;ί :本發明之實施例之發光二極體晶片的製造 ^利用光束來使緩衝層的—部分及第—_辭導體層 產生反應’進而藉由侧來形成”，以產生光 政射區。如此-來’本發明之實蘭的製造方法便可以用 ，為簡單的製程步驟，來形成絲出效率較高的發光二極 ^晶片。此外，由於本發明之實施例之發光二極體晶片具 有位於緩衝層中且陷入第一摻雜態半導體層中的空洞，以 形成，散射區，因此本發明之實施例之發光二極體晶片具 有較而的光取出效率。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 圖1A至圖1F為本發明之一實施例之發光二極體晶片 的製造方法之流程剖面示意圖，而圖2為圖1A之發光二 極體晶片的上視圖。本實施例之發光二極體晶片的製造方 法包括下列步驟。請先參照圖1A，首先，提供一基板11〇。 在本實施例中，基板110例如為氧化鋁基板（sapphire substrate)。然而，在其他實施例中，基板11〇亦可以是 201140877 P51990003TW 33941twf.doc/n 其他適當的透光基板或不透光基板。接著，在基板HQ上 形成一緩衝層120。在本實施例中，形成緩衝層丨2〇的步 驟為先在基板110上形成一成核層（nucleation layer) 122， 然而再在成核層122上形成一無摻雜半導體層 (unintentionally doped semiconductor layer) 124。在本實 施例中，成核層122例如為5奈米至100奈米的無摻雜氮 化鎵（galliumnitride, GaN)層。無摻雜半導體層124例如 φ 是無摻雜氮化鎵層，其庠‘度例如為500奈米至2000奈米。 然後，在緩衝層120上形成一第一摻雜態半導體層 130。在本實施例中，第一摻雜態半導體層13〇為N型半 導體層，例如為N型氮化鎵層，其厚度例如為15⑻〇奈米 至50000奈米。之後，在第一摻雜態半導體層13〇上形成 一發光層140。在本實施例中，發光層14〇為一多重量子 井層（multiple quantum well，MQW) ’其例如由複數對井 層（well)與阻障層（barrier)所形成。舉例而言，井層例 如為氮化銦鎵（Indium gallium nitride，InGaN)層，而阻障 層例如為氮化鎵層。在本實施例中，發光層14〇可具有1〇 對氮化銦鎵層與氮化鎵層，即氮化銦鎵層與氮化鎵層交替 堆豐，其中氮化銦鎵層的厚度例如為3〇埃（angstr〇m)， 而氮化鎵層的厚度例如為70埃，但本發明不以此為限。在 其他實施例中’井層與阻障層的厚度與對數可根據所選用 的不同材料來作適當的調整與設定。 再來，在發光層140上形成一第二摻雜態半導體層 150。在本實施例中，第二摻雜態半導體層15〇為p型^ 201140877 fW 33941twf.doc/n 導體層，例如為P型氮化鎵層。在本實施例中，第二摻雜 態半導體層150的厚度例如為100奈米至5〇〇奈米。在其 他實施例中，亦可以是第一摻雜態半導體層13〇為p型半 導體層，而第二摻雜態半導體層15〇為N型半導體層。在 本實施例中，緩衝層120、第—摻雜態半導體層13(^發光 層140及第二摻雜態半導體層15()的材f包括氮化物 (nitride)，然而，在其他實施例中，這些膜層亦可以包 括其他適當的半導體材賀或其他材質。 請再參照圖1B，接著，在緩衝層12〇、第一摻雜態半 導體層130、發光層140及第二摻雜態半導體層15〇^刻 劃出至少-道刻痕S (在圖丨B中是以多道刻痕s為例）X。 在本實施例中’例如是利用雷射光束來關出刻痕s 炼燒出刻痕S。舉例而言，此雷射光束例如 奈米的雷射絲。—，在其他實施财，此雷射I5; 可以是波長為奈米至365奈米的紫外#射光束或其他 波段的雷射光束。然而，刻劃出刻痕§的步驟不—定 行，在其他實施财，亦可以不關A祕S，即不執行 圖1B的步驟。 卜矾仃 請參照® 1C ’再來，利用—穿透基板110的光束5〇 照射於緩衝層12G的-部分a與第—摻雜態半導體層咖 之與緩衝層12G的部分A鄰接之—部分B上，以使緩衝屏 12〇的部分A與第-摻雜態半導體層m的部分b產生二 在本實施例中，光束5G例如為—穿透基㈣。且聚 焦於# A與部分B之雷射光束，緩衝層i2Q的部分a 201140877 r 31 y y υυ03 TW 33941twf. doc/n 包括成核層122的一部分A1及無摻雜半導體層i24的一 部分A2。此外，在本實施例中，當光束5〇照射於部分a 與部分B時，會使部分A與部分B產生化學反應。舉例 而言，部分A與部分B原本的材質皆為氮化鎵，而此化學 反應會使氮化鎵反應成鎵原子與氮氣，其中氮 環境中，而部分A與部分B的材質則變成鎵/、9Wiyyuuu^rw 33941twf.doc/n light layer, - second #_ semiconductor layer. The first-doped semiconductor layer is matched with ==I: two: in the buffer layer, two sides; ί: the fabrication of the light-emitting diode wafer of the embodiment of the invention uses a light beam to make the buffer layer The first-_conductor layer produces a reaction 'and then formed by the side" to produce a photo-irradiation zone. Thus, the manufacturing method of the present invention can be used for a simple process step to form wire-out efficiency. a higher light-emitting diode chip. Further, since the light-emitting diode wafer of the embodiment of the present invention has a cavity in the buffer layer and trapped in the first doped semiconductor layer to form a scattering region, the present invention The light-emitting diode wafer of the embodiment has a relatively high light extraction efficiency. In order to make the above features and advantages of the present invention more comprehensible, the following specific embodiments will be described in detail below with reference to the accompanying drawings. 1A to 1F are schematic cross-sectional views showing a method of fabricating a light emitting diode wafer according to an embodiment of the present invention, and Fig. 2 is a top view of the light emitting diode wafer of Fig. 1A. Dipolar crystal The manufacturing method of the sheet includes the following steps. Referring first to Figure 1A, first, a substrate 11 is provided. In the present embodiment, the substrate 110 is, for example, a sapphire substrate. However, in other embodiments, the substrate 11 〇 may also be 201140877 P51990003TW 33941twf.doc/n other suitable transparent substrate or opaque substrate. Next, a buffer layer 120 is formed on the substrate HQ. In this embodiment, the step of forming the buffer layer 丨2〇 is A nucleation layer 122 is first formed on the substrate 110, but an unintentionally doped semiconductor layer 124 is formed on the nucleation layer 122. In the present embodiment, the nucleation layer 122 is, for example, It is an undoped gallium nitride (GaN) layer of 5 nm to 100 nm. The undoped semiconductor layer 124 such as φ is an undoped gallium nitride layer, and its 庠' degree is, for example, 500 nm to 2000. Then, a first doped semiconductor layer 130 is formed on the buffer layer 120. In this embodiment, the first doped semiconductor layer 13 is an N-type semiconductor layer, for example, an N-type gallium nitride layer. , its thickness, for example It is 15 (8) 〇 nanometer to 50,000 nm. Thereafter, a light-emitting layer 140 is formed on the first doped semiconductor layer 13A. In this embodiment, the light-emitting layer 14 is a multiple quantum well layer (multiple quantum well layer). , MQW) 'is formed, for example, by a complex pair of wells and barriers. For example, the well layer is, for example, an indium gallium nitride (InGaN) layer, and the barrier layer is, for example, It is a gallium nitride layer. In this embodiment, the light-emitting layer 14A may have a 1-inch-on-indium gallium nitride layer and a gallium nitride layer, that is, an indium gallium nitride layer and a gallium nitride layer are alternately stacked, wherein the thickness of the indium gallium nitride layer is, for example, It is 3 angstroms, and the thickness of the gallium nitride layer is, for example, 70 angstroms, but the invention is not limited thereto. In other embodiments, the thickness and logarithm of the well and barrier layers may be suitably adjusted and set according to the different materials selected. Further, a second doped semiconductor layer 150 is formed on the light emitting layer 140. In the present embodiment, the second doped semiconductor layer 15 is a p-type ^ 201140877 fW 33941 twf. doc / n conductor layer, for example, a P-type gallium nitride layer. In the present embodiment, the thickness of the second doped semiconductor layer 150 is, for example, 100 nm to 5 nm. In other embodiments, the first doped semiconductor layer 13 is a p-type semiconductor layer, and the second doped semiconductor layer 15 is an N-type semiconductor layer. In the present embodiment, the material f of the buffer layer 120, the first doped semiconductor layer 13 (the light emitting layer 140 and the second doped semiconductor layer 15) includes a nitride, however, in other embodiments The film layers may also include other suitable semiconductor materials or other materials. Referring again to FIG. 1B, then, in the buffer layer 12, the first doped semiconductor layer 130, the light emitting layer 140, and the second doped state. The semiconductor layer 15 scribes at least a track score S (in the figure B, a multi-track score s is taken as an example) X. In the present embodiment, for example, a laser beam is used to turn off the score s. The scoring S is smelted. For example, the laser beam is a laser of nanometer. - In other implementations, the laser I5; may be a UV beam having a wavelength of from nanometer to 365 nm. Or other wavelengths of the laser beam. However, the steps of scoring the nicks are not - fixed, in other implementations, you can also not close the A secret S, that is, do not perform the steps of Figure 1B. 1C 'Return, using the light beam 5 穿透 penetrating the substrate 110 to illuminate the - portion a of the buffer layer 12G and the first doped semiconductor layer The portion A of the buffer layer 12G is adjacent to the portion B such that the portion A of the buffer screen 12A and the portion b of the first-doped semiconductor layer m are generated. In the present embodiment, the light beam 5G is, for example, a penetrating base (4) and focusing on the laser beam of #A and part B, a portion of the buffer layer i2Q a 201140877 r 31 yy υυ03 TW 33941twf. doc/n including a part of the nucleation layer 122 A1 and the undoped semiconductor layer i24 In addition, in the present embodiment, when the light beam 5 is irradiated to the portion a and the portion B, the portion A and the portion B are chemically reacted. For example, the original materials of the portions A and B are Gallium nitride, and this chemical reaction will cause gallium nitride to react into gallium atoms and nitrogen, in which the nitrogen environment, while the material of part A and part B becomes gallium /, 9
在本實施例中，光束50的波長落在使緩衝層12〇的 部分A與第-換雜態半導體層13〇的部分B產生反應的範 圍内。舉例而言，光束50例如為波長為355奈米的雷射光 束。然而，在其他實施例巾，光束5〇亦可以是波長為19〇 奈米至365奈米的紫外雷射光束或其他波段的雷射光束。 此外，在本實施例中，產生反應的部分A與部分B呈網格 狀，但本發明不以此為限。在其他實 部分A與部分B亦可以呈長條狀、方形、菱形 、h奸、1 ID，然後，钱刻經反應的緩衝層12〇的部 分A與第—摻㈣半導㈣13()的部&b，以形成至少一 在本實補巾，例如是_非等向濕錢利製程 A與部分B，亦即可利祕刻液絲刻部分A 溶：刀丄舉例而言’可將圖1D之整體結構置於熱鹽酸 # 、，、、攝氏25度至45度的鹽酸溶液）中浸泡約〇 5分 =^分鐘。接著’再將整體結構置於攝氏75度至9〇度 =氧化鉀溶液約3分鐘至15分鐘。如此—來，在 例中，便可將材質為鎵的部分A與部分B移除， 201140877 to lyyuwj nv 33941tw£doc/n 洞H。此外’在本實施例中刻痕s與空洞h相通y奐言之，In the present embodiment, the wavelength of the light beam 50 falls within a range in which the portion A of the buffer layer 12A and the portion B of the first-differential semiconductor layer 13 are reacted. For example, beam 50 is, for example, a laser beam having a wavelength of 355 nm. However, in other embodiments, the beam 5 〇 may also be an ultraviolet laser beam having a wavelength of from 19 奈 to 365 nm or a laser beam of other wavelengths. Further, in the present embodiment, the portion A and the portion B which generate the reaction are in the form of a mesh, but the invention is not limited thereto. In other real parts A and B can also be strips, squares, diamonds, traits, 1 ID, and then, the portion A of the buffer layer 12 与 and the first doped (four) semi-conductive (four) 13 () Department &b, to form at least one in the actual patch, such as _ non-isotropic wet money process A and part B, can also be used to engrave the engraved part of the A solution: knife 丄 for example ' The whole structure of Fig. 1D was placed in a hydrochloric acid solution of hot hydrochloric acid #,,, and 25 to 45 degrees Celsius for about 5 minutes = ^ minutes. Then, the overall structure is placed at 75 degrees Celsius to 9 degrees Celsius = potassium oxide solution for about 3 minutes to 15 minutes. So—in the example, part A and part B with the material gallium can be removed, 201140877 to lyyuwj nv 33941tw£doc/n hole H. Further, in the present embodiment, the score s is in communication with the hole h, y, in other words,
在本實施例中’請先參照圖1C，刻痕S會暴露出部分A 與部分B，因此當進行圖id之步驟時，蝕刻液可順著刻 痕S流至部分A與部分B，以產生餘刻的效果。另一方面， 部分A與部分B亦可以延伸至圖lc之整體結構的側表 面，而使蝕刻液從位於此側表面處之部分A與部分B開始 钱刻。 在本實施例中，當蝕刻液蝕刻完部分A與部分B之 後’會繼續朝著發光層140的方向蝕刻第一摻雜^態半導體 層130。如此一來，當形成空洞11後，第一摻雜‘態半導體 層130之位於空洞η頂部的表面132會形成朝向基板ιι〇 凸出的複數則錐狀表面結，134，而此角錐狀表面結構 134可包括氮化鎵晶體的（1〇Π)面。值得注意的是，本發明 並不限定須先形成刻痕S而後形成孔洞Η。在其他實^例 中亦可以疋先形成孔洞Η，而後形成刻痕s。刻痕s有 助於使整體結構分割成複數個晶片結構。 凊參照圖1Ε，接著，侧第二摻雜態半導體声15〇 :;=C1、發光層140的一部分C2及第-摻雜i半導 部分C3，以暴露出第一摻雜態半•體層130 刻表面136。在本實施财，在此_步驟後，剩 態半導體層150、發光層140及部分位於頂 。:的:-摻雜態半導體層130會形成一平台區p。在本實 _中，此餘刻步驟可為乾式姓刻，例如為交感輕喂 (md她vely c〇upledplasma，lcp)姓刻或反應性離^刻 201140877 P51990003TW 33941twf.doc/n (reactive ion etching, RIE )。 請參照®1F’然後，在餘刻表面136上形成一第 極·，且在第二摻雜態半導體層15〇的一部分以（即^ 由圖1E之蝕刻步驟後所剩下的那一部分）上形成一第二 電極17G。在本實施财，可先在部分C4上形成—透明& 電廣胁然後再在透明導電層⑽上形成電極⑺。至此， 可完成發光二極體晶片100之製作。在本實施例中，第〜 電極160與第二電極170例如為金屬電極，而透明導電層 180例如為氧化銦錫（indium如〇xide，IT〇)層但本^ 明不以此為限。 χ 圖2為圖IF之發光一極體晶片1〇〇的上視示意圖。 请參照圖1F與圖2，在本實施例中，空洞H為一網格狀 空洞，如圖2所繪示，而上述部分A與部分B呈網格狀之 說明亦可參照圖2之網格狀空洞的形狀。然而，在其他實 施例中’當產生反應的部分A與部分B呈長條狀、方形焉 菱形或其他幾何圖形時’空洞亦可呈對應的長條狀空洞、 方升> 空洞、菱形空洞或呈其他幾何圖形的空洞。在本實施 例中，空洞Η佔了基板11〇之朝向第一摻雜態半導體層13〇 的表面112之20%至75%的面積。再者，空洞Η (即網格 狀空洞）包括多道長條形子空洞Η1與多道長條形子空洞 Η2 ’這些長條形子空洞Η1與這些長條形子空洞互相交 又。在本實施例中’每一長條形子空洞Η2的寬度wi例 如為20微米，且任二相鄰之長條形子空洞Η2的間距W2 例如為50微米，但本發明不以此為限。此外’發光二極體 11 201140877 而 ywim'W 33941twf.doc/n 晶片100包括上述基板11〇、上述經姓刻後的緩衝層12〇 (即形成一圖案化緩衝層）、上述第一摻雜態半導體層 130、上述發光層140、上述第二摻雜態半導體層15〇及上 述空洞Η，其中空洞Η位於緩衝層12〇中，且陷入第一摻 雜態半導體層130中。在本實施例中，空洞η中可填有空 氣或氣體，或者空洞Η可為真空空洞。 此外，在本實施例中，發光二極體晶片1〇〇可更包括 配置於第一摻雜態半導體層130上的第一電極160及配置 於第一掺雜態半導體層150上的第二電極170。此外，在 籲 本實施例中，空洞Η可由基板11〇之朝向第一摻雜態半導 體層130的表面112延伸至第一摻雜態半導體層13〇内。 此外，在本實施例中，基板110之朝向第一摻雜態半導體 層130的表面112例如為一平坦表面。 本實施例之發光二極體晶片100的製造方法利用光束 50來使緩衝層120的部分a及第一摻雜態半導體層13〇 的部分B產生反應，進而藉由蝕刻來形成空洞H，以產生 光散射區。在本實施例中，位於空洞H頂部的角錐狀表面 籲 結構134可產生良好的散射效果。如此一來，本實施例的 製造方法便可以用較為簡單的製程步驟，來形成光取出效 率較尚的發光一極體晶片1〇〇。此外，角錐狀表面結構134 易於使來自發光層140的光產生全反射，而使光在全反射 後，射出發光一極體晶片1〇〇外，這亦是提升發光二極體 晶片100之光取出率的原因。此外，由於空洞Η可在緩衝 層120、第一摻雜態半導體層130、發光層14〇及第二摻雜 12 201140877 P51990003TW 3394 ltwf.doc/n 態半導體層150皆磊晶完成後再形成，而無須打斷磊晶過 程，因此本實施例之製造方法較為簡單，且可避免習知技 術在打斷磊晶過程而將待磊晶物拿出反應爐時所造成的污 染。 此外，由於本實施例之發光二極體晶片1〇〇具有位於 緩衝層120中且陷入第一摻雜態半導體層13〇中的空洞 Η，以形成光散射區，因此本實施例之發光二極體晶片1〇〇 φ 具有較高的光取出效率，進而使發光二極體晶片100具有 較高的亮度與發光效率。 圖3Α與圖3Β為圖1F之發光二極體晶片100的實驗 數據圖。請先參照圖1F與圖3Α，當藉由第一電極16〇與 第二電極170將電流輸入發光二極體晶片1〇〇時，發光二 極體晶片100的輸出功率（即發光二極體晶片1〇〇所發出 的光之功率）隨電流大小之變化如圖3Α中之虛曲線所示。 此外，當電流輸入無本實施例之空洞Η的一般發光二極體 晶片時，一般發光二極體晶片的輸出功率隨電流大小之變 馨 化如圖3Α之實曲線所示。由圖3Α可知，當通入電流為 20毫安培時，本實施例之發光二極體晶片1〇〇的輸出功率 比一般發光二極體晶片的輸出功率高出47%，由此可證明 本實施例之發光二極體晶片議具有較高的發光效率。 5月再參照圖3Β，其為本實施例之發光二極體晶片1〇〇 與無本實施例之空洞Η的一般發光二極體晶片之電壓-電 流特性曲線圖。由圖3Β可知，當電流為2〇毫安培時，本 實關之發光二極體晶片1〇〇之第一電極16〇與第二電極 13 201140877 33941twf.doc/n 170的電壓差之絕對值為319伏特，而一般發光二極體晶 片的電壓差之絕對值則為3.17伏特，由此可證明本實施例 之空洞Η對電壓-電流特性曲線的影響很小，不會導致發 光二極體晶片100的串聯電阻過高，這是因為空洞Η是位 於靠近基板110的位置。 、综上所述’本發明之實施例之發光二極體晶片的製造 方法利用光束來使緩衝層的一部分及第一摻雜態半導體層 的一部分產生反應，進而藉由侧來形成空洞，以產生光 散射ΐ:如此—來’本發明之實施例的製造方法便可以用 =簡單的製程步驟，來形成光取出效率較高的發光二極 士日日片此外，由於本發明之實施例之發光二極體晶片具 緩衝層中且陷人第—摻雜態半導體層中的空洞，以 二:二ί射區’因此本發明之實施例之發光二極體晶片具 有較尚的光取出效率。 士众t、、:本^明已以貫施例揭露如上’然其並非用以限定 所屬技術領域中具有通常知識者，在不脫離 範圍内’當可作些許之更動與潤飾，故本 …&1U視後附之申言青專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1F為本發明之一 _ ^ 的製造方私流㈣面轉圖。實_之料—極體B曰片 =為圖1A<發光二極體晶片的上視圖。 為圖1F之發光二極體晶片⑽的實驗 14 201140877 P51990003TW 33941twf.doc/n 數據圖。 【主要元件符號說明】 50 :光束 100 :發光二極體晶片 110 :基板 120 :緩衝層 ‘ · / 122 :成核層 β 124:無雜半導體層 130 :第一摻雜態半導體層 134 :角錐狀表面結構 136 :独刻表面 140 :發光層 150 :第二摻雜態半導體層 160 :第一電極 170 :第二電極 • 180 :透明導電層 A、Α卜 Α2、Β、C卜 C2、C3、C4 :部分 Η :空洞 m、H2:長條形子空洞 P :平台區 S :刻痕 W1 :寬度 W2 :間距 15In the present embodiment, please refer to FIG. 1C first, the score S will expose the portion A and the portion B, so when the step of the diagram id is performed, the etching liquid can flow along the score S to the portion A and the portion B, Produce the effect of the moment. On the other hand, the portions A and B can also extend to the side surface of the overall structure of Fig. 1c, and the etching liquid is burned from the portions A and B located at the side surface. In the present embodiment, the first doped semiconductor layer 130 is etched toward the light-emitting layer 140 after the etching solution etches the portion A and the portion B. As a result, after the cavity 11 is formed, the surface 132 of the first doped 'state semiconductor layer 130 at the top of the cavity η forms a plurality of tapered surface junctions 134 protruding toward the substrate ι, and the pyramidal surface Structure 134 can include a (1) plane of a gallium nitride crystal. It is to be noted that the present invention is not limited to the formation of the score S and then the formation of the hole Η. In other embodiments, the hole Η can also be formed first, and then the scribe s is formed. The score s helps to divide the overall structure into a plurality of wafer structures. Referring to FIG. 1A, next, the side second doped semiconductor sound 15〇:;=C1, a portion C2 of the light emitting layer 140, and the first doped i semiconductor portion C3 to expose the first doped half body layer 130 engraved surface 136. In this implementation, after this step, the remaining semiconductor layer 150, the light-emitting layer 140, and a portion are located at the top. :: The doped semiconductor layer 130 forms a land region p. In this real _, this remaining step can be dry type engraving, for example, sympathetic light feeding (md her vely c〇upledplasma, lcp) surname or reactive away from engraving 201140877 P51990003TW 33941twf.doc/n (reactive ion etching , RIE). Referring to FIG. 1F', then, a first pole is formed on the surface 136, and a portion of the second doped semiconductor layer 15 is (ie, the portion remaining after the etching step of FIG. 1E). A second electrode 17G is formed thereon. In the present implementation, the electrode (7) may be formed on the transparent conductive layer (10) by forming a transparent & Thus, the fabrication of the light-emitting diode wafer 100 can be completed. In the present embodiment, the first electrode 160 and the second electrode 170 are, for example, metal electrodes, and the transparent conductive layer 180 is, for example, an indium tin oxide (ITO) layer, but the present invention is not limited thereto. Figure 2 is a top plan view of the light-emitting diode wafer 1 of Figure IF. Referring to FIG. 1F and FIG. 2, in the embodiment, the cavity H is a mesh-shaped cavity, as shown in FIG. 2, and the part A and the part B are in a grid shape. The shape of the lattice. However, in other embodiments, 'When the part A and the part B which generate the reaction are elongated, square, rhomboid or other geometric shapes, the 'cavity may also correspond to a long strip, square liters> hollow, diamond hollow Or a void in other geometric shapes. In the present embodiment, the voids occupy an area of 20% to 75% of the surface 112 of the substrate 11 facing the first doped semiconductor layer 13A. Furthermore, the void Η (ie, the grid-like void) includes a plurality of long strip-shaped hollow holes Η 1 and a plurality of long strip-shaped hollow holes Η 2 ′ these long strip-shaped hollow holes 与 1 and the long strip-shaped sub-holes intersect each other. In the present embodiment, the width wi of each of the elongated strip holes 例如 2 is, for example, 20 μm, and the pitch W2 of any two adjacent strip-shaped sub-holes Η 2 is, for example, 50 μm, but the invention is not limited thereto. . In addition, the 'light emitting diode 11 201140877 and the ywim'W 33941 twf.doc/n wafer 100 includes the above substrate 11 , the above-mentioned buffer layer 12 姓 (ie, forming a patterned buffer layer), the first doping The semiconductor layer 130, the light-emitting layer 140, the second doped semiconductor layer 15 and the cavity Η, wherein the cavity Η is located in the buffer layer 12〇 and is trapped in the first doped semiconductor layer 130. In the present embodiment, the void η may be filled with air or gas, or the void Η may be a vacuum void. In addition, in the embodiment, the LED wafer 1 may further include a first electrode 160 disposed on the first doped semiconductor layer 130 and a second disposed on the first doped semiconductor layer 150. Electrode 170. Further, in the present embodiment, the cavity Η may extend from the surface 112 of the substrate 11 toward the first doped semiconductor layer 130 into the first doped semiconductor layer 13A. Further, in the present embodiment, the surface 112 of the substrate 110 facing the first doped semiconductor layer 130 is, for example, a flat surface. The manufacturing method of the light-emitting diode wafer 100 of the present embodiment utilizes the light beam 50 to react the portion a of the buffer layer 120 and the portion B of the first doped semiconductor layer 13A, thereby forming a cavity H by etching. A light scattering region is generated. In the present embodiment, the pyramidal surface of the cavity H is urged to produce a good scattering effect. In this way, the manufacturing method of the present embodiment can form a light-emitting monopole wafer having a higher light extraction efficiency by a relatively simple process step. In addition, the pyramidal surface structure 134 is easy to cause total reflection of the light from the light-emitting layer 140, and the light is emitted after the total reflection, and the light-emitting diode wafer 100 is raised. The reason for the removal rate. In addition, since the cavity Η can be formed after the epitaxial completion of the buffer layer 120, the first doped semiconductor layer 130, the luminescent layer 14 〇, and the second doping 12 201140877 P51990003TW 3394 ltwf.doc/n semiconductor layer 150, There is no need to interrupt the epitaxial process, so the manufacturing method of the embodiment is relatively simple, and the pollution caused by the prior art when the epitaxial process is interrupted and the epitaxial material is taken out of the reaction furnace can be avoided. In addition, since the light-emitting diode wafer 1 of the present embodiment has a cavity 位于 located in the buffer layer 120 and trapped in the first doped semiconductor layer 13 以 to form a light scattering region, the light-emitting region of the present embodiment The polar body wafer 1 〇〇 φ has a high light extraction efficiency, which in turn enables the light-emitting diode wafer 100 to have high luminance and luminous efficiency. 3A and 3B are experimental data diagrams of the LED array 100 of Fig. 1F. Referring to FIG. 1F and FIG. 3A, when a current is input to the LED substrate 1 by the first electrode 16A and the second electrode 170, the output power of the LED chip 100 (ie, the LED) The power of the light emitted by the wafer 1 varies with the magnitude of the current as shown by the dashed curve in Figure 3Α. In addition, when the current is input to the general light-emitting diode chip without the cavity of the present embodiment, the output power of the general light-emitting diode wafer changes with the magnitude of the current as shown by the solid curve in FIG. As can be seen from FIG. 3A, when the current is 20 mA, the output power of the LED of the present embodiment is 47% higher than that of the general LED chip. The light-emitting diode wafer of the embodiment has a high luminous efficiency. Referring again to Fig. 3, in May, it is a graph showing the voltage-current characteristics of the light-emitting diode wafer 1 of the present embodiment and the general light-emitting diode wafer without the cavity of the present embodiment. As can be seen from FIG. 3A, when the current is 2 mA amps, the absolute value of the voltage difference between the first electrode 16 〇 and the second electrode 13 201140877 33941 twf.doc/n 170 of the actual LED chip It is 319 volts, and the absolute value of the voltage difference of the general light-emitting diode chip is 3.17 volts, which proves that the cavity 本 of this embodiment has little influence on the voltage-current characteristic curve and does not cause the light-emitting diode. The series resistance of the wafer 100 is too high because the void Η is located close to the substrate 110. In the above, the method for manufacturing a light-emitting diode wafer according to the embodiment of the present invention uses a light beam to cause a part of the buffer layer and a portion of the first doped semiconductor layer to react, thereby forming a cavity by the side. Producing Light Scattering ΐ: Thus, the manufacturing method of the embodiment of the present invention can use a simple process step to form a light-emitting diodes having a higher light extraction efficiency. Further, due to an embodiment of the present invention The light-emitting diode wafer has a cavity in the buffer layer and is trapped in the first doped semiconductor layer, and has a two-dimensional radiance region. Therefore, the light-emitting diode chip of the embodiment of the present invention has a relatively high light extraction efficiency. .士众,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, &1U shall be subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1F are diagrams showing the manufacturing side private flow (four) surface of one of the inventions. Real material - polar body B = = is the top view of the light emitting diode wafer of Figure 1A < Experiment with the light-emitting diode wafer (10) of Fig. 1F 14 201140877 P51990003TW 33941twf.doc/n data map. [Description of main component symbols] 50: Light beam 100: Light-emitting diode wafer 110: Substrate 120: Buffer layer '· / 122: Nucleation layer β 124: No impurity semiconductor layer 130: First doped semiconductor layer 134: Pyramid Shaped surface structure 136: etched surface 140: luminescent layer 150: second doped semiconductor layer 160: first electrode 170: second electrode • 180: transparent conductive layer A, Α Α 2, Β, C C C2, C3 , C4 : Partially Η : void m, H2: long strip shaped cavity P : platform area S : notch W1 : width W2 : spacing 15