201135960 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種去疵方法，及一種太陽能電池， 特別疋#曰一種石夕晶圓的去疯方法，及利用該去疫方法製得 之太陽能電池。 【先前技術】 晶圓（wafer)是製作光電元件晶片、半導體元件晶片、 太陽能電池元件等的最重要基礎材料’其中，以矽太陽電 池而言，由於目前矽材料短缺的現象產生，使得矽材料約 佔石夕太陽電池成本結構超過五成，此也是目前各國於發展 石夕太陽電池時共同面臨的發展瓶頸及亟待克服的問題之 因此如何回收石夕晶圓材料、降低晶圓厚度同時提升 矽晶圓品質、並提高其能量轉換效率則是現階段技術研發 的主轴。 一般晶圓的回收通常都會先利用酸性化學劑或喷砂等 方式，將1C等級晶圓上之電路研磨、化學蝕刻、拋光處理 後去除晶圓表面上的電路，使得處理過的晶圓可重新利用 於太陽能面板的製作，而古日* I下而有助於減緩太陽能電池矽晶材料 的短缺問題，然而在一般的加工過程中晶圓容易受到重金 屬的汙染，而這些存在晶圓内的摻雜元素（例如蝴、砰 以及金屬雜質（例如鐵、鋅、 鏢鈷）’在矽晶圓中會造成深階 (deep-level)缺陷，所以必猪 員將日日圓中的金屬雜質濃度 低，才能提高其在1C或是太 4疋太％能電池應用上的良率。 目前利用晶圓本身，或再 刀工處理形成其它結構來控 201135960 制或消除該晶圓内的金屬離子雜質，進而確保製作之半導 體電元件效能的方法統稱為去疵方法，其大致可再區分為 内部去疵（Intrinsic gettedng )、外部去疵（Extrinsic gettedng)，以及化學去疵（Chemical gettedng)三大類； 内部去疵方式是利用晶圓的内部缺陷吸附金屬雜質，因 此，最終金屬雜質還是會存在晶圓内部；化學去疫 (Chemical gettering)方式，則是僅能有效處理晶圓表面 10〜20微米内的缺陷，而其中，外部去疵則是在晶圓的其中 一表面上形成一層由多晶矽（p〇ly_silic〇n )構成的應力鲁 層，利用該應力層來補捉存在於晶圓内部的金屬雜質。而 由於結晶性太陽能電池必需使用整塊矽基材當做光電轉換 層，因此，外部去疵法將是一種非常有潛力的技術，可以 將矽基材内大部分的金屬污染物去除。 目前’外部去疵大多是利用低壓化學氣相沉積方式201135960 VI. Description of the Invention: [Technical Field] The present invention relates to a method for removing germanium, and a solar cell, in particular, a method for removing madness from a stone wafer, and using the method of removing the disease Solar battery. [Prior Art] Wafer is the most important basic material for fabricating photovoltaic element wafers, semiconductor element wafers, solar cell elements, etc. - In the case of solar cells, due to the current shortage of germanium materials, germanium materials are produced. About 30% of the cost structure of Shixi solar cells is the development bottleneck and the problems that need to be overcome in the development of Shixi solar cells. How to recover Shishi wafer materials and reduce the thickness of wafers at the same time. Wafer quality and improved energy conversion efficiency are the main axes of technology development at this stage. Generally, wafer recycling usually uses an acid chemical or sand blasting method to remove the circuit on the surface of the wafer by grinding, chemical etching, and polishing the circuit on the 1C grade wafer, so that the processed wafer can be reworked. It is used in the manufacture of solar panels, and the ancient days can help alleviate the shortage of solar cell twinning materials. However, in general processing, wafers are easily contaminated by heavy metals, and these are incorporated in the wafer. Miscellaneous elements (such as butterflies, bismuth, and metallic impurities (such as iron, zinc, and darts) can cause deep-level defects in the wafer, so the pigs will have low metal impurity concentrations in the yen. In order to improve the yield of 1C or too 4% energy battery applications, the wafer itself or the knife is used to form other structures to control the 201135960 system or eliminate the metal ion impurities in the wafer, thereby ensuring The methods for fabricating the performance of semiconductor electrical components are collectively referred to as de-scission methods, which can be roughly classified into Intrinsic gettedng and Extrinsic gettedng. And chemical gettedng three types; the internal decarburization method is to use the internal defects of the wafer to adsorb metal impurities, so the final metal impurities will still exist inside the wafer; the chemical gettering method is Only the defects within 10~20 micrometers of the wafer surface can be effectively processed, and the external deuterium is formed on one surface of the wafer by a layer of stress layer composed of polycrystalline germanium (p〇ly_silic〇n). The stress layer compensates for the metal impurities present inside the wafer. Since the crystalline solar cell must use a monolithic substrate as the photoelectric conversion layer, the external deuterium method will be a very promising technology. Most of the metal contaminants in the substrate are removed. At present, most of the external deuterium is by low pressure chemical vapor deposition.
(Low pressure chemical vapor deposit，LPCVD)，以 650°C 以上的溫度，沉積時間不小於3〇分鐘的條件下，在矽晶基 材的其中一表面沉積一厚度約為〇5μιη且由多晶矽構成的 _ 應力層；但對一般具有摻雜元素或重金屬污染的半導體材 料而& ’ 650C的溫度已經是屬於會形成大量的缺陷核的高 溫，特別是對具有高摻雜的半導體材料而言，這樣的溫度 更是容易在晶片内部成核（nuclei),而在後續元件製程中的 向溫作用成長形成大的缺陷，反而會降低晶圓的品質及製 得之半導體太陽能電池元件的效能。 由於石夕是生產太陽能電池的重要原材料，然而矽材料 201135960 的供應短缺卻已成為 如何改盖…… 成長的最大障礙’所以， 金屬離子的濃度 、.·έ ’有效降切晶圓材料内重 圓的。質二*卩’碎Μ片内缺陷核產生，以改善晶 圓的4進而確保製作出之光電元件的效能，—直 技術領域研究者努力研究的目標。 【發明内容】(Low pressure chemical vapor deposit, LPCVD), depositing a thickness of about μ5 μm and consisting of polycrystalline germanium on one surface of the twinned substrate at a temperature of 650 ° C or higher and a deposition time of not less than 3 〇 minutes. _ stress layer; but for semiconductor materials with general doping or heavy metal contamination, & '650C temperature is already a high temperature that will form a large number of defect cores, especially for semiconductor materials with high doping, The temperature is more likely to nuclei inside the wafer, and the growth of the temperature in the subsequent component process forms a large defect, which in turn reduces the quality of the wafer and the performance of the fabricated semiconductor solar cell component. Since Shixi is an important raw material for the production of solar cells, the shortage of 矽Material 201135960 has become a major obstacle to growth... Therefore, the concentration of metal ions, έ 有效 'effectively cut the wafer material within the round of. The defect nucleus in the mass II*卩's broken slab is produced to improve the crystal 4 and thus ensure the efficiency of the fabricated photovoltaic element. [Summary of the Invention]
之曰，本發明之㈣，即在提供-種將高重金屬含量 之曰曰圓轉變成高品質晶圓的去財^ 法赞^ ▲本^之另—目的’為提供—種湘該去疲方 製传之兩品f晶圓製作而得的太陽能電池。 於是，本發明的一種去疲方法是包含一準備步驟一 ，，、力層形成步驟，及一熱作用步驟。 邊準備步驟是先準備一由組成份包含重金屬之體 材料構成的基板。 該應力層形成步驟太，/。 取7鄉疋在250 C〜400〇c的溫度範圍條件 下’於該基板的其中一裊面、节接π > 衣面'儿積形成—具有非晶矽結構的 應力層，且該應力層會同時於該表面形成背應力。 該熱作用步驟是將前述製得形成有該應力層的基板， 再經過_t:〜謂。(：的熱作用，令該基板的重金屬於此溫 度條件下沿著應力層方向擴散、沉積，使該半導體材料於 遠離該應力層之區域的重金屬濃度降低。 此外，本發明一種利用該去疲方法製得之太陽能電池 包含：一基材、—第—型半導體層、-第二型半導體層， 及一電極單元。 201135960 該基材由半導體材料構成，具有一基板，及一形成在Then, (4) of the present invention, that is, providing a kind of high-heavy metal content into a high-quality wafer, the method of deciding ^ ▲ this ^ other - purpose 'to provide - the species should be tired The solar cell produced by the two-product f wafer produced by the system. Thus, a method of de-wetting of the present invention comprises a preparation step 1, a force layer forming step, and a heat-acting step. The preparation step is to prepare a substrate composed of a bulk material containing a heavy metal. The stress layer forming step is too long. Take 7 nostalgia 疋 in the temperature range of 250 C~400〇c 'in one of the surface of the substrate, the joint π > the surface of the clothing to form a stress layer with an amorphous 矽 structure, and the stress The layer will simultaneously form back stresses on the surface. The thermal action step is to obtain the substrate on which the stress layer is formed, and then pass _t:~. The thermal action of (:: causes the heavy metal of the substrate to diffuse and deposit along the stress layer under such temperature conditions, so that the concentration of the heavy metal of the semiconductor material in the region away from the stress layer is lowered. Further, the present invention utilizes the fatigue The solar cell produced by the method comprises: a substrate, a first-type semiconductor layer, a second-type semiconductor layer, and an electrode unit. 201135960 The substrate is composed of a semiconductor material, has a substrate, and is formed on
該基板其中—表面的應力層，且該基材是先在25(TC~400°C 的溫度範圍條件下於該基板的其中一表面形成一層非晶矽 結構的應力層，接著再經過9〇〇〇c〜11〇〇〇c熱作用，令該應 力層的非晶矽結構轉變成多晶矽結構而得到。 該第一型半導體層是形成於該應力層上。 該第一型半導體層是形成於該基板反向於該應力層的 一表面。 該電極單元具有一第一電極，及一第二電極，且該第 一、二電極分別形成於該第一、二型半導體層表面。 本發明之功效在於：先以低溫製程在基板的其中一表 面形成一應力層，再借由高溫熱作用條件，使得高溫時具 有高擴散速率的重金屬沿著該應力層方向擴散、沉積在該 應力層與該基板的接觸邊界，可有效的降低基板内的重金 屬辰度，而得到一高品質基材，並可再將以此去疵方法製 得之基材用以製得太陽能電池。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將 清楚的呈現。 ° 本發明的去疫方法是用於降低具有高濃度重金屬之曰 圓内的重金屬濃度，以提升晶圓的品質，並可以該去疒 法製得的晶圓用於製作光電⑽，於本較佳實施例中，方 利用該去疯方法製得之基材製作太陽能電池為例作說=乂 201135960 惟本發明之應用並不以此為限。 多閱圖1纟發明—種太陽能電池的較佳實施例是包含 -基材2、-第-型半導體層3、—第二型半導體層4，及 一電極單元5。 該基材2由半導體材料構成，具有—基板21及一形成 在該基板21其中一表面的應力層22。 具體的說，該基材2是經過—去疲方法後所製得，該The substrate has a stress layer on the surface thereof, and the substrate is first formed with a layer of amorphous germanium structure on one surface of the substrate at a temperature range of TC to 400 ° C, and then passed through 9 〇. The thermal action of 〇〇c~11〇〇〇c is obtained by converting the amorphous germanium structure of the stress layer into a polycrystalline germanium structure. The first type semiconductor layer is formed on the stress layer. The first type semiconductor layer is formed. The substrate is opposite to a surface of the stress layer. The electrode unit has a first electrode and a second electrode, and the first and second electrodes are respectively formed on the surface of the first and second semiconductor layers. The utility model has the advantages that a stress layer is formed on one surface of the substrate by a low temperature process, and then a high-temperature thermal action condition is adopted, so that a heavy metal having a high diffusion rate at a high temperature is diffused along the stress layer and deposited on the stress layer. The contact boundary with the substrate can effectively reduce the heavy metal in the substrate, thereby obtaining a high-quality substrate, and the substrate prepared by the method can be used to obtain a solar cell. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of a preferred embodiment with reference to the drawings. The method of decontamination of the present invention is for reducing The concentration of heavy metals in the circle of high concentration heavy metals is used to improve the quality of the wafer, and the wafer prepared by the method can be used to fabricate photovoltaics (10). In the preferred embodiment, the method of using the de-mad method is used. The substrate is made of a solar cell as an example = 乂201135960 However, the application of the invention is not limited thereto. More preferably, the preferred embodiment of the solar cell comprises - substrate 2, - - The semiconductor layer 3, the second semiconductor layer 4, and an electrode unit 5. The substrate 2 is made of a semiconductor material, and has a substrate 21 and a stress layer 22 formed on one surface of the substrate 21. Specifically, The substrate 2 is obtained by a method of de-wetting, which
去庇方法包含一準備步驟、一應力層形成步驟，及一熱作 用步驟。 該準備步驟是準備—組成份包含高濃度重金屬的半導 體材料構成的基板，該基板可為經過電路研磨、化學# 刻、拋光處理後去除晶圓表面電路後< ic等級的回收晶 圓’或是-般具有高濃度重金屬的半導體材料，例如， 石夕、氮化石夕、氧化石夕、砂化鎵、鍺 '具有n_型捧雜的半導 體材料，或是具有ρ·型掺雜的半導體材料，重金屬則是在 製作半導體材料的製程過程中常見之重金屬污染物，例如 鐵、錄、#，或此等之-組合，由於該些半導體材料及相 關的重金屬雜質污染物是相關業者所週知，因此，不再多 加贅述，於本實施例中’該基板是選自具有高濃度重金屬 捧雜：石夕晶圓，而該等具有高濃度重金屬的石夕晶圓目前業 界—般統稱為冶金級（metallurgical graded)晶圓。 、▲該應力層形成步驟是在25(TC〜400t的溫度範圍條件下 於遠基板的其中—表面沉積形成—層具有非晶石夕結構的應 力層，且該應力層會同時於該表面形成一背應力。 201135960 要說明的疋，當該應力層的沉積溫度低於25(TC時，該 應力層成長的速度會太慢，不利於量產製程；而當溫度大 於4〇〇t時，特別是對具有高濃度摻雜（heavy doped)的半導 體材料而言，大於的溫度及較長的沉積時間更容易令 知·些摻雜70素在基板内部成核（nuclear)，而在後續製作的 咼溫製程中在成核的地方長成較大的缺陷（defect)，而影響 後續製得之太陽能電池的品質，因此’該應力層的沉積溫 度是控制在250〜400。(：之間，且沉積時間不大於5分鐘。 又，值得一提的是，雖然該應力層的厚度愈大，其產 生的背應力會同時增加，使得捕捉重金屬的能力亦相對增 加，然而當該應力層的厚度太大時，與該基板之間亦會產 生過大的應力，反而會造成在後段製程時容易產生較大的 變異性而造成良率降低的問題，因此，較佳地，該應力層 的沉積時間是控制在1〜5分鐘之間，且厚度是控制在 〇·1〜Ιμιη ;更佳地，該應力層的沉積時間是控制在3〜5分 鐘，且該應力層的厚度疋控制在〇.3〜1.〇 之間，在此沉積 溫度及沉積時間的控制條件下，可更有效的減低存在基板 中之換雜元素在該基板内形成缺陷核的機率。 更詳細地說，該應力層可以電漿增強化學氣相沉積（以 下簡稱PECVD)方式或熱絲化學氣相沉積（以下簡稱hwcvd) 沉積而得。 以PEC VD方式沉> 積該應力層時’是控制在：工作壓力 0.3〜0.5 Ton:、功率密度0.05〜1 W/cm2、通入氣體源流量 (seem)是 SiH4 : = 5〜20 : 15〜100，及溫度在 250〜4〇〇。〇 得 201135960 條件下進行。 以HWCVD方式沉積該應力層時，是控制在：腔體壓 力0’3 0.5 Torr、板材溫度在250〜400°C、熱絲溫度控制在 1400 1800 C ’及通入氣體源流量（sccm)是yH4 : h2 =5~20 = 15〜1〇〇的條件下進行。The method of removing the shelter includes a preparation step, a stress layer forming step, and a thermal action step. The preparation step is to prepare a substrate composed of a semiconductor material containing a high concentration of heavy metals, which may be a reclaimed wafer of < ic grade after circuit polishing, chemical etching, polishing, and removal of the wafer surface circuit. It is a semiconductor material having a high concentration of heavy metals, for example, a stone material having a high concentration of heavy metals, such as a stone alloy, a cerium nitride, a oxidized stone, a gallium arsenide, a semiconductor material having an n-type dopant, or a semiconductor having a p-type doping. Materials, heavy metals are heavy metal contaminants commonly found in the manufacturing process of semiconductor materials, such as iron, recording, #, or the like, because these semiconductor materials and related heavy metal impurity contaminants are relevant to the industry. Therefore, in this embodiment, the substrate is selected from the group consisting of high-concentration heavy metal holdings: Shi Xi wafers, and the Shi Xi wafers with high concentration of heavy metals are currently collectively referred to as the industry. Metallurgical graded wafers. ▲ The stress layer forming step is a stress layer having an amorphous slab structure formed on the surface of the far substrate at a temperature range of 25 (TC to 400 t), and the stress layer is simultaneously formed on the surface. A back stress. 201135960 To be described, when the deposition temperature of the stress layer is lower than 25 (TC, the growth rate of the stress layer will be too slow, which is not conducive to the mass production process; and when the temperature is greater than 4〇〇t, Especially for semiconductor materials with high doped doping, larger temperatures and longer deposition times make it easier to know that some doped nucleus is nucleated inside the substrate, and in subsequent fabrication. In the temperature-temperature process, a large defect is formed in the nucleation place, which affects the quality of the subsequently produced solar cell, so the deposition temperature of the stress layer is controlled at 250 to 400. And the deposition time is no more than 5 minutes. It is also worth mentioning that although the thickness of the stress layer is larger, the back stress generated by the stress layer is increased at the same time, so that the ability to capture heavy metals is relatively increased, however, when the stress layer is When the degree is too large, excessive stress is generated between the substrate and the substrate, which may cause a large variability in the subsequent process and cause a problem of a decrease in yield. Therefore, preferably, the deposition of the stress layer is performed. The time is controlled between 1 and 5 minutes, and the thickness is controlled at 〇·1~Ιμιη; more preferably, the deposition time of the stress layer is controlled at 3 to 5 minutes, and the thickness of the stress layer is controlled at 〇 Between 3 and 1. 〇, under the control conditions of the deposition temperature and the deposition time, the probability of the impurity-containing elements present in the substrate forming a defect core in the substrate can be more effectively reduced. More specifically, the stress The layer can be obtained by plasma enhanced chemical vapor deposition (hereinafter referred to as PECVD) or hot wire chemical vapor deposition (hereinafter referred to as hwcvd) deposition. The PEC VD method is used to accumulate the stress layer when it is controlled at: working pressure 0.3~0.5 Ton:, power density 0.05~1 W/cm2, flow rate of incoming gas source (seem) is SiH4: = 5~20: 15~100, and temperature is 250~4〇〇. Under the condition of 201135960 When depositing the stress layer by HWCVD It is controlled at: cavity pressure 0'3 0.5 Torr, plate temperature at 250~400 °C, hot wire temperature control at 1400 1800 C ' and gas flow rate (sccm) is yH4 : h2 =5~20 = 15 It is carried out under conditions of ~1〇〇.
該熱作用步驟是將前述形成有該應力層的基板在90(TC 1100 C進行熱作用，令該應力層的結構從非晶矽結構轉為 多晶矽結構，且同時讓高溫時具有高擴散速度之重金屬可 快速沿著背應力方向擴散，而沉積在該應力層及該應力層 與忒基板接觸的邊界，使該基板於遠離該應力層的區域轉 變成一低重金屬含量的高品質矽晶基板，而得到該矽晶基 材。 特別要說明的是，當利用熱作用過程將該應力層從非 晶矽結構轉為多晶矽結構的過程，須避免因為氫迅速擴散 而造成該應力層潰裂，較佳地，該熱作用步驟須採取多階 段升溫步驟，於本實施例中，該熱作用步驟是以三階段升 溫方式進行，先以每分鐘升溫5。〇，並於非晶矽轉為多晶矽 之交界處持溫約30-60分鐘，最後再以每分鐘升溫5t升溫 至900〜11〇〇。〇並持溫約30·60分鐘而完成。 此外，要說明的是，該去疵方法可更包含一實施在該 熱作用步驟之後的應力層移除步驟，將該應力層移除而 得到一低重金屬含量的高品質矽晶基板，而該高品質矽晶 基板也可直接做為製作光電元件所需之基材。 詳細地說，該應力層移除步驟可以蝕刻或砂磨方式將 201135960 該應力層移除，由於以㈣或砂磨移除非晶石夕或多晶石夕材 料為本技術領域業者週知，因此，於此不再多加贅述。 又要說明的是，在進行該應力層移除步驟時，可更進 一步將該基材與該應力層接觸之表面移除至一預定深度， 如此可更確保沉積在該應力層與該基材邊界的重金屬可被 完全移除，以減少殘留之重金屬對後續高溫製程的不良影 響。 該第一型半導體層3是形成於該應力層22上，是選自 η型摻雜或p型摻雜的半導.體材料所構成。 在此要說明的是’ η型摻雜或ρ型摻雜的選擇是與該第 二型半導體層4相對應的’也就是說，當該第一型半導體 層3是選自η型摻雜的半導體材料構成時，第二型半導體 層4則是由ρ型半導體材料構成，反之亦然，由於該第一 型半導㈣3的材料選擇及製程控制為本技術領域者所週 知因此不再多加說明；於本實施例巾，該第_財導體層3 是選自η型摻雜的非晶⑦所構成，且為直接沉積形成在該 應力層22上。 該第二型何體層4是形成於該基板21反向於該應力 層22的一表面。 詳細的說，該第二型半導體層4是選自電性與該第一 型半導體I 3相反的半導體材料所構成，可與該第一型半 導體層3相互配合，提昇載子的產生效率，於本實施例中 該第二型半導體層4是選自ρ型掺雜的非晶石夕所構成。 該電極單元5具有分別形成於該第一、二型半導體層 10 201135960 3、4表面的一第-電極51，及-第二電極52,該第一、二 電極51、52可選自金屬（例如：鋁、全 备銀）、合金金屬（例 如：金鍺錦合金），或是多層結構的導電材料所構成，可相 互配合將電流向外輸出’由於該電極單元5的材料選擇為 本技術領域者所週知，因此不再多加說明，於本實施例 中，該第-、二電極51、52分別具有依序由該第—、二型 半導體層3、4表面形成的透明導電膜川、52卜與電極片 512、522。 $The thermal action step is to heat the substrate on which the stress layer is formed at 90 (TC 1100 C to change the structure of the stress layer from an amorphous germanium structure to a polycrystalline germanium structure, and at the same time, to have a high diffusion rate at high temperatures. The heavy metal can be rapidly diffused along the back stress direction, and deposited on the stress layer and the boundary of the stress layer contacting the germanium substrate, so that the substrate is transformed into a high-quality twin crystal substrate with a low heavy metal content in a region away from the stress layer. The twinned substrate is obtained. In particular, when the stress layer is converted from the amorphous germanium structure to the polycrystalline germanium structure by a thermal action process, the stress layer is prevented from being cracked due to rapid diffusion of hydrogen, preferably. The heat-acting step is a multi-stage heating step. In this embodiment, the heat-acting step is performed in a three-stage heating mode, firstly heating the temperature by 5 〇, and switching from amorphous to polycrystalline germanium. Hold the temperature for about 30-60 minutes, and finally heat up to 500~11 以 at a temperature of 5t per minute. 〇 and hold the temperature for about 30.60 minutes. In addition, it should be noted that the 疵The method further includes a stress layer removing step performed after the thermal action step, the stress layer being removed to obtain a low-quality metal content high-quality twinned substrate, and the high-quality twin crystal substrate can also be directly used as The substrate required for the fabrication of the photovoltaic element. In detail, the stress layer removal step may remove the stress layer of 201135960 by etching or sanding, due to the removal of the amorphous stone or polycrystalline stone by (4) or sanding. The material is well known to those skilled in the art and, therefore, will not be further described herein. It is also noted that, in performing the stress layer removal step, the surface of the substrate in contact with the stress layer may be further removed. Up to a predetermined depth, it is further ensured that the heavy metal deposited on the boundary between the stress layer and the substrate can be completely removed to reduce the adverse effect of residual heavy metals on the subsequent high temperature process. The first type semiconductor layer 3 is formed on The stress layer 22 is formed of a semiconductor material selected from n-type doping or p-type doping. It is to be noted that the selection of the n-type doping or the p-type doping is the same as the second Type semiconductor layer 4 relative That is, when the first type semiconductor layer 3 is composed of a semiconductor material selected from an n-type doping, the second type semiconductor layer 4 is composed of a p-type semiconductor material, and vice versa, due to the first The material selection and process control of the type semi-conductive (four) 3 are well known to those skilled in the art and therefore will not be further explained; in the embodiment of the invention, the first-conductor conductor layer 3 is composed of amorphous 7 selected from n-type doping. And forming a direct deposition on the stress layer 22. The second type of the body layer 4 is formed on a surface of the substrate 21 opposite to the stress layer 22. In detail, the second type semiconductor layer 4 is selected. The self-conducting semiconductor material opposite to the first type semiconductor I 3 is formed to cooperate with the first type semiconductor layer 3 to improve the efficiency of generating carriers. In the embodiment, the second type semiconductor layer 4 is It is composed of a p-type doped amorphous stone. The electrode unit 5 has a first electrode 51 formed on the surface of the first and second semiconductor layers 10 201135960 3, 4, and a second electrode 52, and the first and second electrodes 51, 52 may be selected from metal ( For example: aluminum, full silver), alloy metal (for example: gold bismuth alloy), or a multilayer structure of conductive materials, can cooperate with each other to output current to the outside 'Because the material of the electrode unit 5 is selected as the technology It is well known in the art, and therefore, the first and second electrodes 51 and 52 respectively have transparent conductive films formed on the surface of the first and second semiconductor layers 3 and 4 in this embodiment. 52 and the electrode sheets 512 and 522. $
此外’要說明的是’當該應力層22於經過熱作用步驟 後若再經過該應力層移除步驟而被移除，則該應力層22被 移除後所得到的矽晶基板21也可直接用來當成太陽能電池 所需之基材，如此，該第一、二型半導體層3、4為分別沉 積在該矽晶基板21的相反表面，該第一、二電極51、52 分別形成在該第一、二型半導體層3、4上，而可得到一太 陽能電池。 综上所述，本發明藉由兩階段去疵方法而得到高品質 之矽晶基材；第一階段是先以250〜40(TC的低溫製程條件， 在含南濃度重金屬摻雜的基板表面沉積形成一應力層，由 於該應力層是以不大於400T：的低溫方式形成，因此可得到 一幾乎無缺陷核產生的基板，所以可避免習知以高溫（大於 650 °C )製程方式形成應力層時，基板内部的摻雜元素由於 在長時間的高溫作用下，容易在該基板成核（nuclear)，反 而使得基板内部的重金屬雜質容易殘留在基板内部，並且 會在後續元件製程中的高溫製程時，例如在高於1 〇〇〇的 201135960 1C製程時，容易沿著缺陷核而成大的缺陷（defect)，而降低 製得之半導體光電元件的效能。 第二階段再藉由熱處理方式，讓在高溫時具有高擴散 速率的重金屬沿著應力層方向擴散，而沉積在該應力層及 該應力層與該基板接觸之界面，降低該基板之重金屬雜質 濃度’將該基板轉變成一低重金屬含量之高品質矽晶基 板，而彳于到一具有一應力層及一矽晶基板的基材，此外， 也可再進一步將該應力層移除，得到不具有應力層的矽晶 基板，該經去疵方法處理後得到的基材或矽晶基板則可進 一步用來製作太陽能電池等光電元件，而可有效提升太陽 能電池等光電元件的品質及光電效率，故確實能達成本發 :以上所述者’僅為本發明之較佳實施例與具體例而 申^不^此限定本發明實狀_，即大凡依本發明 飾，皆仍屬本發明專利涵蓋之範圍内。 ^ 【圖式簡單說明】 圖1是一示意圖，芎日日士 例。 ° 明太陽能電池的較佳實施 12 201135960 【主要元件符號說明】 2 基材 5 1 第一電極 21 基板 511 透明導電膜 22 應力層 512 電極片 3 第一型半導體層 52 第二電極 4 第二型半導體層 521 透明導電膜 5 電極單元 522 電極片In addition, it is to be noted that when the stress layer 22 is removed through the stress layer removal step after the thermal action step, the twin layer substrate 21 obtained after the stress layer 22 is removed may also be used. Directly used as a substrate required for a solar cell, such that the first and second semiconductor layers 3, 4 are respectively deposited on opposite surfaces of the twin crystal substrate 21, and the first and second electrodes 51, 52 are respectively formed on On the first and second semiconductor layers 3, 4, a solar cell can be obtained. In summary, the present invention obtains a high quality twin substrate by a two-stage decanting method; the first stage is firstly performed at a low temperature process condition of 250 to 40 (TC) in a substrate containing a heavy metal doped with a south concentration. Depositing to form a stress layer, since the stress layer is formed in a low temperature manner of not more than 400T:, a substrate having almost no defect nucleus can be obtained, so that it is possible to avoid forming a stress at a high temperature (greater than 650 ° C) process. When the layer is formed, the doping element inside the substrate is easily nucleated on the substrate due to the high temperature for a long period of time, and the heavy metal impurities inside the substrate are likely to remain inside the substrate, and the high temperature in the subsequent component process is high. During the process, for example, in the 201135960 1C process above 1 ,, it is easy to make a large defect along the defect core, and reduce the performance of the fabricated semiconductor photovoltaic element. The second stage is further processed by heat treatment. a heavy metal having a high diffusion rate at a high temperature is diffused along the stress layer, and deposited at the interface between the stress layer and the stress layer and the substrate, Lowering the heavy metal impurity concentration of the substrate to convert the substrate into a low-quality metal-crystalline high-quality twinned substrate, and to a substrate having a stress layer and a twinned substrate, and further reducing the stress The layer is removed to obtain a twinned substrate without a stress layer, and the substrate or the twinned substrate obtained by the de-twisting method can be further used for fabricating photovoltaic elements such as solar cells, and can effectively improve photovoltaic elements such as solar cells. The quality and photoelectric efficiency of the present invention can be achieved by the present invention. All of them are still covered by the patent of the present invention. ^ [Simple description of the drawing] Fig. 1 is a schematic diagram of a Japanese example. The preferred embodiment of a solar cell is 12 201135960 [Signature of main components] 2 Substrate 5 1 first electrode 21 substrate 511 transparent conductive film 22 stress layer 512 electrode sheet 3 first type semiconductor layer 52 second electrode 4 second type semiconductor layer 521 transparent conductive film 5 electrode Element electrode tab 522
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