201135877 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體元件封裝結構，尤指一種 具有保護功能之半導體元件封裝結構。 【先前技術】 隨著科技的進步，各種電子設備產品皆朝向輕、薄、 紐收小的方向發展，而變阻器主要用途在於吸收外來突波 而^電壓至安全的範圍，以避免電源線或電子電路中的 波電壓破壞。為了延長電子科的壽命及提供安 王的“作％<境，因此有必要加錢阻器來 【發明内容】 件封斤Γ決的技術問題’在於提供-種半導體元 件封裝結構，其能夠用來封裝任何的保護元件（例如且有 突波電壓之保護晶片)，以製作一種具 保禮功能之半導體元件封裝結構。 β為了解決上述技術問題，根據本發明之其中—種方案 姑提^齡錢護魏之半導體元件縣結構，其包 括且:基板單元、一絕緣單元及一保護單元。該基板單 少—頂層基板及至少—底層基板。該絕緣單元 一填充於上述至少一頂層基板及上述至少- =板之間之絕緣層。該保護單元具有至少一電性地 上述至少一頂層基板與上述至少-底層基板之 :二至少一絕緣層所包覆之具有防止突波電流 或大波電壓之保護晶片。 為了解決上述技術問題，根據本發明之其中一種方案 ^供種具有保護功能之铸體元件封裝結構，其包 4/13 201135877 括：一基板單元、一絕緣單元及一保護單元。該基板單 元具有至少-頂層基板及至少—底層基板。該絕緣單元 具有至少一設置於上述至少一頂層基板及上述至少一 底層基板之間之絕緣層，且上述至少一絕緣層具有一開 口。該保護單元具有至少一電性地設置於上述至少一頂 層基板與上述至少一底層基板之間且容置於上述至少 一絕緣層的開口内之具有防止突波電流或突波電壓之 保護晶片。 因此’本發明的有益效果在於：上述至少—頂層基板 與上述至少一底層基板之間具有一層容置空間以收容至 少一被上述至少一絕緣層所包覆或容置於上述至少一絕 緣層的開Π内之具有防止突波電流或突波電壓之保護晶 片。 為使能更進-步瞭解本發明之特徵及技術内容，請參 閱以下有關本發明之詳細說明與關，然而所關式僅提 供參考與·用’並非时對本剌加以限制者。 【實施方式】 明參㈣A®至第— DS1所示，本發明第—實施例 ^供一種脑_魏之轉體元件域職Z，其包括 .一基板單701、—絕緣單元2及-保護單元3。 其中’祕板單元丨具有至少1層基板丨丄及至少 2層基板12。舉例來說，上述至少—頂層基板丄工的 上表面具有至少_頂層導 餘板11㈣㈣〜了卿娜11B，I 底層f板12的上表面具有至少-底層導電轨 α 2 述至少—底層基板12的下表面具有至少 5/13 201135877 兩個底層導電焊墊1 2 B。 再者，該絕緣單元2具有至少一填充於上述至少一頂 層基板1 1及上述至少一底層基板1 2之間之絕緣層2 〇。此外，上述至少一頂層基板1 1、上述至少一絕緣層 2 0及上述至少一底層基板1 2由上而下依序堆疊在一 起。 另外，上述至少一頂層基板1 1的側邊具有至少兩個 第一半穿孔1 1C，上述至少一絕緣層2 0的側邊具有至 少兩個分別相對應上述至少兩個第一半穿孔11C之第 二半穿孔2 0A，且上述至少一底層基板12的側邊具有 至少兩個分別相對應上述至少兩個第二半穿孔2 0 A之 第三半穿孔1 2 C。換言之，每一個第一半穿孔1 1C、 每一個第二半穿孔2 0A及每一個第三半穿孔1 2 C皆 相連在一起以形成每一個貫穿孔P (如第一C圖所示的立 體組合示意圖）。 此外，上述至少一頂層基板1 1具有至少兩個分別成 形於上述至少兩個第一半穿孔11C的内表面上之第一 導電層1 1 D，上述至少一絕緣層2" 0具有至少兩個分別 成形於上述至少兩個第二半穿孔2 0A的内表面上且分 別電性連接於該些第一導電層1 1D之第二導電層2 0 B，且上述至少一底層基板12具有至少兩個分別成形於 上述至少兩個第三半穿孔1 2 C的内表面上且分別電性 連接於上述至少兩個第二導電層2 0 B之第三導電層1 2 D。換言之，每一個第一導電層1 1D、每一個第二導 電層2 0 B及每一個第三導電層1 2D皆相連在一起以 形成每一個導電層C (如第一C圖所示的立體組合示意圖 6/13 201135877 )° 再者，該保護單元3具有至少一電性地設置於上述至 少—頂層基板11與上述至少一底層基板12之間且被 上述至少一絕緣層2 〇所完全包覆之具有防止突波電流 或突波電壓之保護晶片3 0 (例如變阻器），其中上述至 少—具有防止突波電流戒突波電壓之保護晶片3 〇電性 連接於上述至少一頂廣導電軌跡11B及上述至少—底 層導電軌跡1 2 A之間。 如第一D圖所示，上述至少一頂層基板1 1與上述至 少—底層基板12之間具有一層容置空間以收容至少一 被上述至少一絕緣層2 0所完全包覆之具有防止突波電 流或突波電壓之保護晶片30 (上述至少一絕緣層2〇完 全貼緊上述至少一保護晶片3 0的周圍，亦即上述至少一 絶緣層2 0與上述至少/保護晶片3 0之間沒有任何的 間隙）’以使得本發明可達成具有保護功能之半導體元件 封裝結構之製作。 請參閱第二圖所示，本發明第二實施例提供一種具有 保護功能之半導體元件封裝結構z，其包括：一基板^元 1、一絕緣單元2及一保護單元3。其中，該基板單元丄 ，有至少-頂層基板！ i及至少—底層基2。該絕 =兀2具有至少-設置於上述至少—頂層基板。 ，至少-底料板1 2之間之絕緣層2 Q，且上述至少一 =層2 Q具有-開σ 2◦〇。該保護單元3具有至少— ^生地設置於上述至少1層基板i i與上述至少 =1 2之間且容置於上述至少—絕緣層2 〇的開口 〇 0内之具有防止突波電流或突波電壓之保護晶 7/13 201135877 SUb ’本發明第二實施例與第—實施例最大的差別在 ，二在第二實施例中，上述至少一保護晶片3 〇容置於上 屉'乂、絕緣層2 0的開口 2 〇 〇内，且上述至少一絕緣 古推0只5圍繞上述至少―保護晶片3 ◦的關，而並沒 實施例一樣完全緊貼上述至少一保護晶片3 〇。 °月參閱第二圖所示’本發明第三實施例提供一種具有 保護功能之半導體元件封裝結構z，其包括：—基板單元 1 絕緣單元2及-保護單元3。其中，該基板單元工 ^有至少—頂層基板1 1及至少-底層基板12。該絕緣 單几2具有至少-填充於上述至少—頂層基板丄丄及上 述至少-底層基板12之間之絕緣層2 〇。該保護單元3 具有至少一電性地設置於上述至少一底層基板12上且 破上述至少一絕緣層2 〇所包覆之具有防止突波電流或 突波電壓之保護晶片3 〇。因此，本發明第三實施例與第 一實施例最大的差別在於：在第三實施例中，省略上述至 少-頂層導電軌跡1 1B，而增加至少-底層導電軌跡工 2 A，以使得上述至少一保護晶片3〇的底部直接電性連 接於兩個底層導電軌跡1 2 A。 請參閱第四圖所示，本發明第四實施例提供一種具有 保護功能之半導體元件封裝結構Z，其包括：一基板單元 1、一絕緣單元2及一保護單元3。其中，該基板單元1 具有至少一頂層基板1 1及至少一底層基板12。該絕緣 單元2具有至少一設置於上述至少一頂層基板i丄及上 述至少一底層基板12之間之絕緣層20，且上述至少一 絕緣層2 0具有一開口 2 0 0。該保護單元3具有至少一 電性地設置於上述至少一底層基板12上且容置於上述 8/13 201135877 至少-絕緣層2 0的開口 2 Q Q内之具有防止突波電流 或突波電壓之賴晶片3 0。因此，本㈣第四實施例與 第一貫細•例最大的差別在於：在第四實施例中，上述至少 -保濩晶片3 0容置於上述至少一絕緣層2 q的開口 2 0 0内’且上述至少-絕緣層2()只是圍繞上述至少一保 護晶片3 0關1)，而並沒有像第三實施例（或第一實施 例）一樣完全緊貼上述至少一保護晶片3 〇。 综上所述，上述至少一頂層基板與上述至少一底層基 板之間具有一層容置空間以收容至少一被上述至少一絕 緣層所包覆或容置於上述至少一絕緣層的開口内之具有 防止突波電流或突波電壓之保護晶片。 以上所述僅為本發明之較佳可行實施例，非因此侷限 本發明之專利㈣，故舉凡利本發明說明書及圖式内容 所為之等效技術變化，均包含於本發明之範圍内。 【圖式簡單說明】 第一A圖為本發明第一實施例之其中一視角之立體分解 示意圖； 第一B圖為本發明第一實施例之另外一視角之立體分解 示意圖； 第一C圖為本發明第一實施例之立體組合示意圖； 第D圖為本發明第一實施例之剖面示意圖； 第二圖為本發明第二實施例之剖面示意圖； 第二圖為本發明第三實施例之剖面示意圖；以及 第四圖為本發明第四實施例之剖面示意圖。 【主要元件符號說明】 半導體元件封裝結構 z 9/13 201135877BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element package structure, and more particularly to a semiconductor element package structure having a protection function. [Prior Art] With the advancement of technology, various electronic equipment products are developing in the direction of light, thin, and small-sized, and the main purpose of the varistor is to absorb external surges and voltage to a safe range to avoid power lines or electronics. The wave voltage in the circuit is destroyed. In order to extend the life of the electronics department and provide An Wang's "%" environment, it is necessary to add money to the device. [Inventive content] The technical problem of the package is to provide a semiconductor component package structure, which can It is used to package any protective component (for example, a protection chip with a surge voltage) to fabricate a semiconductor component package structure with a ceremonial function. In order to solve the above technical problem, according to the present invention, The structure of the semiconductor component of Wei Zhiwei includes: a substrate unit, an insulating unit and a protection unit. The substrate is a single-top substrate and at least a bottom substrate. The insulating unit is filled in the at least one top substrate and the above At least - = an insulating layer between the plates. The protection unit has at least one electrically insulating layer of the at least one top substrate and the at least one of the underlying substrates: at least one insulating layer is coated with a surge current prevention or a large wave voltage Protecting the wafer. In order to solve the above technical problem, according to one of the aspects of the present invention, a casting body component package having a protective function is provided. The structure of the package includes: a substrate unit, an insulating unit and a protection unit. The substrate unit has at least a top substrate and at least a bottom substrate. The insulating unit has at least one of the at least one top substrate and An insulating layer between the at least one underlying substrate, and the at least one insulating layer has an opening. The protection unit has at least one electrically disposed between the at least one top substrate and the at least one underlying substrate and is received in the above a protective wafer having an anti-surge current or a surge voltage in the opening of at least one of the insulating layers. Therefore, the present invention has an advantageous effect that the at least one of the top substrate and the at least one underlying substrate has a receiving space for receiving At least one protective wafer having a surge current prevention or surge voltage protected by the at least one insulating layer or housed in the opening of the at least one insulating layer. To enable further understanding of the features of the present invention And the technical content, please refer to the following detailed description and related to the present invention, however, the closed type only provides reference and use ' The present invention is not limited to the present invention. [Embodiment] As shown in the following paragraphs (4) A® to DS-DS1, the first embodiment of the present invention provides a brain-wei-transfer component domain Z, which includes a substrate single 701. The insulating unit 2 and the protective unit 3, wherein the 'myster unit 丨 has at least one substrate 丨丄 and at least two substrates 12. For example, at least the upper surface of the top substrate has at least _ top layer The remaining plates 11 (four) (four) ~ Qing Na 11B, I the bottom surface of the bottom plate 12 has at least - the bottom conductive track α 2 described above - at least the lower surface of the bottom substrate 12 has at least 5 / 13 201135877 two bottom conductive pads 1 2 B. Furthermore, the insulating unit 2 has at least one insulating layer 2 填充 filled between the at least one top substrate 1 1 and the at least one underlying substrate 1 2 . In addition, the at least one top substrate 1 1 , the at least one insulating layer 20 and the at least one underlying substrate 12 are sequentially stacked from top to bottom. In addition, the side of the at least one top substrate 11 has at least two first semi-perforations 11C, and the sides of the at least one insulating layer 20 have at least two corresponding to the at least two first semi-perforations 11C. The second semi-perforation 20A, and the side of the at least one bottom substrate 12 has at least two third semi-perforations 1 2 C corresponding to the at least two second semi-perforations 20A, respectively. In other words, each of the first semi-perforations 1 1C, each of the second semi-perforations 20A, and each of the third semi-perforations 1 2 C are joined together to form each through hole P (as shown in the first C-picture Combination diagram). In addition, the at least one top substrate 11 has at least two first conductive layers 11 D respectively formed on the inner surfaces of the at least two first semi-perforations 11C, and the at least one insulating layer 2 " 0 has at least two Formed on the inner surfaces of the at least two second semi-perforations 20A, respectively, and electrically connected to the second conductive layers 20B of the first conductive layers 11D, respectively, and the at least one bottom substrate 12 has at least two And a third conductive layer 1 2 D respectively formed on the inner surfaces of the at least two third semi-perforations 1 2 C and electrically connected to the at least two second conductive layers 20B, respectively. In other words, each of the first conductive layers 1 1D, each of the second conductive layers 20B, and each of the third conductive layers 1 2D are connected together to form each conductive layer C (as shown in FIG. Combination diagram 6/13 201135877 ) Further, the protection unit 3 has at least one electrically disposed between the at least one top substrate 11 and the at least one underlying substrate 12 and is completely encapsulated by the at least one insulating layer 2 Protecting the wafer 30 (for example, a varistor) having a surge current or a surge voltage, wherein the at least the protection wafer 3 having the surge current or the surge voltage is electrically connected to the at least one top conductive track 11B and at least the above-mentioned underlying conductive track 1 2 A. As shown in FIG. D, the at least one top substrate 1 1 and the at least the bottom substrate 12 have an accommodating space for accommodating at least one of the at least one insulating layer 20 to be completely covered. a protective wafer 30 of current or surge voltage (the at least one insulating layer 2 〇 is completely adjacent to the periphery of the at least one protective wafer 30, that is, between the at least one insulating layer 20 and the at least/protective wafer 30 Any gap)' is such that the present invention can achieve the fabrication of a semiconductor device package structure having a protective function. Referring to the second embodiment, a second embodiment of the present invention provides a semiconductor device package structure z having a protection function, comprising: a substrate 1, an insulating unit 2, and a protection unit 3. Wherein, the substrate unit 丄 has at least a top substrate! i and at least - the underlying base 2. The absolute = 兀 2 has at least - disposed on at least the top substrate. At least - the insulating layer 2 Q between the primer plates 12, and the at least one = layer 2 Q has -open σ 2 ◦〇. The protection unit 3 has at least one of the at least one substrate ii and the at least =1 and is accommodated in the opening 〇0 of the at least-insulating layer 2 具有 to prevent surge current or surge Voltage protection crystal 7/13 201135877 SUb 'The second embodiment of the present invention differs from the first embodiment in the second embodiment. In the second embodiment, the at least one protective wafer 3 is placed in the upper drawer '乂, insulated The opening 2 of the layer 20 is inside the crucible, and the at least one insulating layer 5 surrounds the at least one of the protective wafers 3, and is completely in close contact with the at least one protective wafer 3 without the embodiment. Referring to the second figure, the third embodiment of the present invention provides a semiconductor device package structure z having a protective function, which includes: a substrate unit 1 an insulating unit 2 and a protection unit 3. Wherein, the substrate unit has at least a top substrate 11 and at least a bottom substrate 12. The insulating sheet 2 has at least an insulating layer 2 填充 filled between the at least the top substrate 丄丄 and the at least the underlying substrate 12. The protection unit 3 has at least one protective wafer 3 that is electrically disposed on the at least one underlying substrate 12 and is covered by the at least one insulating layer 2 to prevent surge current or surge voltage. Therefore, the greatest difference between the third embodiment of the present invention and the first embodiment is that in the third embodiment, the at least-top conductive track 1 1B is omitted, and at least the underlying conductive track 2 A is added to make the above-mentioned at least The bottom of a protective wafer 3 is directly electrically connected to the two underlying conductive traces 1 2 A. Referring to the fourth embodiment, a fourth embodiment of the present invention provides a semiconductor device package structure Z having a protection function, comprising: a substrate unit 1, an insulation unit 2, and a protection unit 3. The substrate unit 1 has at least one top substrate 11 and at least one bottom substrate 12. The insulating unit 2 has at least one insulating layer 20 disposed between the at least one top substrate i and the at least one bottom substrate 12, and the at least one insulating layer 20 has an opening 200. The protection unit 3 has at least one electrically disposed on the at least one base substrate 12 and is received in the opening 2 QQ of the 8/13 201135877 at least the insulating layer 20 to prevent surge current or surge voltage. Lai wafer 30. Therefore, the fourth embodiment of the present invention has the greatest difference from the first embodiment in that, in the fourth embodiment, the at least-protective wafer 30 is accommodated in the opening 2 0 0 of the at least one insulating layer 2 q . And the at least-insulating layer 2() is only closed around the at least one protective wafer 30), and does not completely adhere to the at least one protective wafer 3 as in the third embodiment (or the first embodiment). . In summary, the at least one top substrate and the at least one bottom substrate have a receiving space for receiving at least one of the at least one insulating layer or the opening of the at least one insulating layer. Protect the wafer from surge current or surge voltage. The above is only a preferred embodiment of the present invention, and is not intended to limit the invention (i), and the equivalents of the invention are included in the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The first A is a perspective exploded view of one of the perspectives of the first embodiment of the present invention; the first B is a perspective exploded view of another perspective of the first embodiment of the present invention; FIG. 3 is a schematic cross-sectional view showing a first embodiment of the present invention; FIG. 2 is a cross-sectional view showing a second embodiment of the present invention; A schematic cross-sectional view of the fourth embodiment of the present invention. [Main component symbol description] Semiconductor component package structure z 9/13 201135877
基板單元 1 頂層基板 11 頂層導電焊墊 1 1 A 頂層導電軌跡 1 1 B 第一半穿孔 11C 第一導電層 1 1 D 底層基板 12 底層導電軌跡 1 2 A 底層導電焊墊 1 2 B 第三半穿孔 1 2 C 第三導電層 1 2D 絕緣單元 2 絕緣層 2 0 開口 2 0 0 第二半穿孔 2 0 A 第二導電層 2 0 B 保護單元 3 保護晶片 3 0 貫穿孔 P 導電層 CSubstrate unit 1 Top substrate 11 Top conductive pad 1 1 A Top conductive trace 1 1 B First half via 11C First conductive layer 1 1 D Underlying substrate 12 Underlying conductive trace 1 2 A Underlayer conductive pad 1 2 B Third half Perforation 1 2 C Third Conductive Layer 1 2D Insulation Unit 2 Insulation Layer 2 0 Opening 2 0 0 Second Half Perforation 2 0 A Second Conductive Layer 2 0 B Protection Unit 3 Protection Wafer 3 0 Through Hole P Conductive Layer C
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