TW201134069A - De-glitch switching power supply circuit and controller for controlling the same - Google Patents

Abstract

The present invention uses time judgment to filter high-frequency noises, so as to avoid erroneous judgments of a controller due to the noises, which affecting the stability of output voltage and output current. The conventional arts use a low-pass capacitor with a larger capacitance to filter noises and it results in increasing the cost. Compared with the conventional arts, the present invention just uses time delay judging unit that may need a small capacitance of a capacitor to filter noise, even the noises with large amplitude. The present invention further sets a timer delay parameter to hold short transient response time while filtering noises.

Description

201134069 VI. Description of the Invention: [Technical Field] The present invention relates to a switching conversion circuit and a controller thereof, relating to a switching conversion circuit and a noise control capability thereof. [Prior Art] The switching converter circuit is the mainstream in today's power supply, and has the advantages of high conversion efficiency, small circuit size, and low power consumption at no load. However, the disadvantage is that the circuit is complicated and the ripple is relatively large. Electromagnetic interference is also relatively large. At present, there are two main control methods for switching converter circuits commonly available on the market, namely, PulseWidth Modulated (PWM) and Pulse Frequency Modulated (pFM). Since the pulse width modulation technology is a fixed frequency operation, electromagnetic wave interference is relatively easy to filter out and has strong anti-noise capability, but the disadvantage is that the circuit conversion efficiency is low and the transient response is slow at light loads. In contrast, the pulse frequency modulation technology has the advantages of conversion efficiency and fast transient response, but the electromagnetic interference caused by it is less easy to filter out and the ability to resist noise is weak. Please refer to the first figure, which is a circuit diagram of a DC-to-DC buck conversion circuit using a pulse frequency modulation technique. The DC-to-DC buck conversion circuit includes a switch SW, a synchronous diode D, an inductor L, an output capacitor C, a voltage detecting circuit composed of resistors R1 and R2, and a controller 10. The voltage detecting circuit detects an output voltage V0UT of the DC-to-DC buck conversion circuit and generates a voltage feedback signal VFB accordingly. The controller 10 includes a comparator 12, a fixed pulse width controller 22, and a driver 32. The comparator 12 receives the voltage feedback signal VFB and a reference signal No. 201134069 Vref, and triggers the fixed pulse width controller to generate a fixed pulse width when the level of the _ to the electric feedback signal WB is lower than the reference signal (4). The pulse signal is sent to the driver 32. The driver 32 generates a control signal Sc according to the pulse signal of the @定 pulse width controller 22 to switch the switch Sw, thereby controlling the magnitude of the power transmitted from an input voltage to the output terminal to stabilize the output voltage ν〇υτ near a voltage. . Next, see the second figure' as the DC-to-DC-conversion circuit shown in the first figure. When the tester grants WB τ to the reference signal _ level, the controller 1 generates a fixed pulse width control signal & the switch is turned on to transfer power to the output, so that the output voltage ν 〇υ τ rises. Due to the interference of the circuit noise, the voltage feedback signal VFB is chopped, and the controller 1 has a misjudgment and affects the stability of the output voltage VOUT. As shown in the figure, the knives circled by the dotted circle Q are caused by the disturbance of the afl', causing the controller 10 to malfunction and output the control signal Sc early, so that the highest value of the output voltage νουτ circled by the dotted circle S is significantly higher than other cycle. In order to filter out the interference of the noise, the device and method for improving the noise sensitivity of the switching system are disclosed in U.S. Patent No. 7,023,253. Please refer to the third figure, which is a circuit diagram of the switching system disclosed in the above patent, wherein the controller 1A includes two amplifiers 14, 15, a low pass filter 16, an adder π, a comparator 24 and a The working time circuit 31 is fixed. The amplifier 14 amplifies the voltage feedback signal VFB by a factor of two and outputs an amplification signal FBF. The amplifier 15 amplifies the voltage feedback signal VFB by a factor of two and outputs it, and then filters it through the low-pass filter 16 into an amplification filter signal! The adder 18 superimposes the amplified signal FBF and the amplified filtered signal FBS into a round of signal FBX. Comparing the output signal FBX and the reference signal Vref, the comparator 24 triggers the fixed working time circuit 31 to generate the control numbers SI, S2 to control a first switch swi and a second switch SW2 when the output signal FBX is lower than the reference signal Vref. Switch. Refer to the fourth figure for the signal timing diagram of the switching system shown in the third figure. Since the noise of the amplification 峨FBF is improved, the level of the noise caused by the wave n is relatively far from the valley to filter out the noise. However, since the low-pass filter 16 used in the above patent for filtering noise needs to use a large capacitor to achieve the function of the ship, the chip (10) E) needs to increase the area to set the wave capacitance 'or external capacitance setting. It is necessary to increase the number of bits of the chip (Qnp) to increase the cost, and the noise of the higher amplitude may still cause the circuit to malfunction, so that the stability of the output voltage is still affected. [Summary of the Invention] The problem of the circuit cost increase and the inability to completely (four) high-shock secrets caused by the inferior ants of the New Zealand technology, the use of the time judgment method can not only avoid the substantial increase of the circuit cost. It is also possible to filter out high amplitude noises and to listen to the transient response of the film path with appropriate age parameters. To achieve the above object, the present invention provides a controller for an anti-noise switching type conversion circuit comprising - a filter, a noise unit, an on-time unit, and a - drive unit. The 遽 单元 单元 根据 根据 根据 根据 根据 根据 根据 根据 遽 遽 遽 遽 遽 遽 遽 遽 遽 遽 遽 — — — — — — — — — — — — — — — — — — — — The guide is called the yuan _ pulse wave city output _ solid 镰 wide signal. The drive unit root_Dingsaki _ field conversion, so that the output power 201134069 is stabilized at a predetermined output voltage. This month also provides a circuit that includes a conversion circuit and a controller. The conversion circuit transmits the power that has been continuously input to the power source to the wheel-out terminal according to at least one control signal to provide a DC output voltage for driving a load. Controlling the woven-to-scheduled-length and the dc-transformation circuit of the dc-transfer circuit is lower than the state of taking the round-out, and the result of the determination is determined, and the output is determined to be a control signal, wherein the pulse width of at least one control signal is A fixed width. The invention also provides another controller for the purchase and replacement of the miscellaneous purchase, including a-passing noise unit, a guide unit single core and a crane unit. The Herxun unit is provided with a load current lower than - pre-recorded (four) red (four) break according to the predetermined length of time and the switching converter circuit, and the recording result determines whether the output-pulse signal is output. The on-time unit outputs a pulse-based signal based on the pulse signal. The drive element is given a u_domain type according to the mosquito vein width, so that the load voltage is stabilized at a predetermined output current. The invention also provides another anti-noise city type conversion circuit * package conversion circuit and - control (four) conversion circuit, according to at least __ control signal, the power of the input power source is transmitted to the output terminal to provide The __DC output voltage is used to drive a load. The control data - the predetermined length of time and the switching converter circuit is supplied to a load - the load current is lower than - the state of the silent (four) flow into the shed, and according to the judgment result, the mosquito is recorded - the pulse signal, the towel at least - The pulse width of the control ship is a fixed width. The above summary and the following detailed description are exemplary in order to further illustrate the scope of the invention. Other objects related to the present invention will be explained in the following description and drawings. [Embodiment] A fifth schematic diagram of a switching converter circuit controller according to the present invention is described. The switching converter circuit controller includes a data unit m, an on-time unit 135, and a driving unit (10). The noise unit 110 & includes a comparison unit 112 and a delay unit 丨2〇. The comparison unit 112 receives the feedback signal FB representing the load state of the switching converter circuit (for example, the voltage across the load, the current of the load, etc.) and a reference signal (4), which is generated when the feedback signal FB is lower than the reference 峨Vrel. Compare the signal to the delay unit (10). The delay list < 120 receives the comparison signal and determines whether the comparison signal continues for a predetermined length of time or whether the cumulative time of the comparison comparison signal exceeds a predetermined time length every week. If yes, the output-pulse signal P is viewed. The on-time unit 135 generates a -solid pulse width signal τ〇η after receiving the pulse wave fl. The driving unit 〇5 产生 generates at least one control signal Gate according to the fixed pulse width signal Ton to control the operation of the switching conversion circuit. Therefore, when the noise causes the timing of the feedback signal FB to be instantaneous but is lower than the reference signal Vrel, the comparison unit briefly outputs the comparison signal to the delay unit of 12 〇, but the output time is shorter than the predetermined time length. The delay unit 120 is not outputted with the pulse signal PWM. In this way, it is ensured that the noise does not affect the operational stability of the switched converter circuit. When the output voltage of the switching converter circuit is lower than the predetermined output voltage 201134069, the feedback signal FB will continue to be lower than the reference signal Vrel, and the delay unit 120 will output the pulse signal, so that the on-time unit 135 generates a fixed signal. Pulse width signal Ton. The driving unit 150 also generates at least one control signal Gate according to the fixed pulse width signal τ〇ηα to cause the switching conversion circuit to transmit power to the output terminal, so that the level of the feedback (10) is raised. Moreover, by appropriately setting the predetermined length of time, not only the influence of the noise can be filtered out, but also the (four) responsiveness of the power exchange can be switched. Please refer to the sixth figure, which is a circuit diagram of a DC-to-DC buck conversion circuit according to the second preferred embodiment of the present invention. The DC transfer money buck conversion circuit includes a filter noise unit 210, an upper edge trigger unit 23A, an on time unit 235, a shortest off time unit 245, a driving unit 250, a first switch M1, and a second The switch M2, an inductor L, an output capacitor c and a voltage detecting circuit formed by the resistors R1 and R2 are used to drive a load 260 〇 voltage detecting circuit to detect an output voltage generated by the DC-DC buck converting circuit 〇υττ to generate a feedback signal fb representing one of the magnitudes of the output voltage VOUT. The filter δ ΐ unit 210 includes a comparison unit 212, an inverter 214, a current source 221, a first switch 222, a second switch 224, a capacitor 226, and a comparator 228. The first switching switch 222 and the second switching switch 224 respectively control the charging process and the discharging process of the capacitor 226, and the conduction timings of the first switching switch 222 and the second switching switch 224 are preferably set to be shifted from each other. The comparison unit 212 receives the recovery signal FB and a reference signal vrel, and generates a high level comparison signal 213 when the feedback signal FB is lower than the reference signal Vrel, so that the first switch 222 is turned on. The first switch 222 is coupled to the current source 221 and the capacitor 226, and charges the capacitor 226 with the current of the current source 221 when the battery is turned on. At this time, the inverter 214 inverts the comparison signal 213' to output a low level signal to turn off the second switching switch 224. Therefore, one of the capacitors 226 gradually rises across the voltage 225. When the feedback signal FB is higher than the reference signal Vrel, the comparison unit 212 generates a low level comparison signal 213 to turn off the first switch 222 to stop charging the capacitor 226. At this time, the inverter 214 inverts the comparison signal 213' to turn a high level signal to turn on the second switching switch 224 to discharge the capacitor 226' so that the capacitance drops to zero across the voltage 225. Comparator 228 compares capacitor crossover voltage 225 and a reference voltage Vb' to output a pulse signal PWM when capacitor crossover voltage 225 is higher than reference voltage Vb. The upper edge trigger unit 230 is coupled to the filter noise unit 210. When the upper edge of the pulse signal PWM is detected, an upper edge detection signal is generated to trigger the on time unit 235 to generate a fixed pulse width signal T〇n. The driving unit 250 controls the switching of the first switch M1 according to the fixed pulse width signal τ〇η to generate the -first control signal UG, and according to the current flowing through the second switch M2, the current side signal cs and the first control signal ug The first control signal LG is generated to control the switching of the second switch M2, so that when the first switch M1 is turned off, the average value of the inductance L can be passed through the second _[freewheeling. The fixed pulse width signal Ton is also transmitted to the most local time unit 2 milk, and the shortest cut-off time unit is moved to the lower edge of the m-definite pulse width signal TGn, and one of the shortest cut-off time signals with the money width is generated. The edge trigger unit 23〇. The upper edge trigger unit receives the most _ _ _ _, stop _ pulse signal

The upper edge of the PWM is used to ensure that the energy stored in the inductor L can be released. Next, please refer to the seventh figure, which is the signal timing diagram of the circuit conversion of the circuit of the sixth round. Please also refer to the sixth figure. When the level of the feedback signal FB is lower than the reference signal Vrel, the comparison signal 213 is turned to the high level and the inverted signal 215 is turned to the low level, so that the first-switch 222 is turned The second switch 2 is turned on to be turned on. At this point, current source 221 begins to charge capacitor 226, causing the scale to gradually rise from zero. When the capacitor cross voltage 225 rises above the reference voltage, the comparator 228 outputs the pulse signal PWM of the high level, so that the upper edge trigger unit 23 triggers the on-time unit 235 to generate a fixed pulse width signal τ〇η for a fixed length of time. . At this time, the driving unit 250 generates the first control signal ug according to the fixed pulse width signal τ〇η to turn on the first switch m, so that the input voltage begins to transmit power to the DC-to-DC buck conversion circuit. rise. When the fixed pulse width signal τ〇η is turned to the low level after a fixed length of time, the shortest cutoff time unit 245 generates the shortest cutoff time signal T〇ff having a fixed width (time length dt). At this time, the driving unit 250 outputs the low level first control signal UG to turn off the first switch group and output the high level second control signal LG to turn on the second _ M2, and the inductor current IL passes through the second open source. . When the freewheeling inductor current IL gradually drops to zero, the second control signal that drives the rim 250 to output a fresh position is called that the first control signal UG remains at a low level, and the second switch M2 is turned off. As shown in the seventh figure, the noise is not judged by the comparison unit 212 in the first cycle T1 and the fourth cycle, but in the second week, the second cycle, the third cycle, the third cycle, and the fifth cycle, the fifth cycle. Because of the timing of the feedback signal FB and the reference signal (4) at this time: the near-synchronization unit 212 has a misjudgment. However, due to the short-term influence of noise, the capacitance span (four) 25 did not rise above the reference voltage %, which was affected by 201134069. The time parameter of charging the electric valley across the voltage 225 to be equal to the reference voltage vb is TRsCf^Vb/n ' where Cf is the capacitance value of the capacitor 226, and η is the current value of the current source 221. Appropriate time parameters can be set to adjust the noise and transient response of the circuit. Please refer to the eighth figure, which is a circuit diagram of a DC-to-DC boost converter circuit according to a third preferred embodiment of the present invention. The DC-to-DC buck conversion circuit includes a filter noise unit 310, an upper edge trigger unit 330, an on-time unit 335, a shortest off-time unit 340, a driving unit 350, a transistor switch M3, an inductor L, An output capacitor C and a current detecting circuit R are used to drive a load 360. The current detecting circuit detects a load current I1〇ad flowing through the load 360 to generate a feedback signal FB representing one of the magnitudes of the load current Iload. The filter unit 310 includes a comparison unit 312, an inverter 314, a first current source 321, a first switch 322, a second current source 323, a second switch 324, a capacitor 326, and a Comparator 328. The first changeover switch 322 and the second changeover switch 324 respectively control the charging process and the discharging process of the capacitor 326. Please also refer to the signal timing diagram of the DC-to-DC boost converter circuit shown in Figure VIII. The comparison unit 312 receives the feedback signal FB and a reference signal Vrel, and generates a high-level comparison signal 313 when the feedback signal FB is lower than the reference signal Vrel, so that the first switch 322 is turned on. The first switch 322 is coupled to the first current source 321 and the capacitor 326, and charges the capacitor 326 with the current of the first current source 321 when turned on. At this time, the inverter 314 inverts the comparison signal 313 to output a low-level reverse signal 315 to turn off the second switching switch 324, so that one of the capacitors 326 is electrically 12 201134069

The cross-over pressure 325 gradually rises. When the feedback signal FB is higher than the reference signal Vrel, the comparison signal 313 which generates a low level in the comparison unit 312 turns off the first switching switch 322 to stop charging the capacitor 326. At this time, the inverter 314 inverts the comparison signal 313 to output a high level signal to turn on the second switching switch 324. The second switch 324 is coupled to the second current source 323 and the capacitor 326. When turned on, the capacitor 326 is discharged by the current of the second current source 323. Therefore, the capacitor across the voltage 325 begins to decrease. To ensure that the capacitor across voltage 325 returns to zero at the end of each cycle, it is preferred that the current of the second current source 323 is greater than the current of the first current source 321 . The comparator 328 compares the capacitor voltage across the voltage 325 and a reference voltage vb, and outputs a pulse signal PWM when the capacitor voltage 325 is higher than the reference voltage vb. The upper edge triggering unit 330 generates an upper edge detection signal to trigger the on-time unit 335 to generate a fixed pulse width signal when detecting the upper edge of the pulse signal p.

Ton. The driving unit 35G generates a control signal _ conduction crystal off M3 according to the fixed pulse width signal Τοη. The suspected wide signal Tc)n is also transmitted to the shortest cutoff time unit 340. The shortest cutoff time unit 34 produces a shortest cutoff time signal with a fixed pulse width when the lower edge of the fixed pulse width signal τ〇η is thin. . Move to the upper edge trigger unit 330. The upper edge triggering unit 33 stops the upper edge of the pulse signal PWM during the period of receiving the shortest cutoff time signal to ensure that the energy stored in the inductor 1 can be released. Please note that the dotted circles A and B' in the figure represent the interference of the output voltage during the rising and falling processes. Since the capacitor crossover voltage 325 at this time is at a relatively high level and a relatively low level, the high frequency noise time lag is insufficient to affect the output of the 134 device 328. Please refer to the tenth figure, which is according to the present invention. A schematic diagram of a controlled circuit of a DC-to-DC converter circuit of a fourth preferred embodiment. The DC-to-DC-return conversion circuit includes an age-sensing unit, an upper-edge trigger unit, an on-time unit το 435, a shortest off-time unit 44A, and a drive unit 45A. The filter noise unit 410 includes a comparison unit 412, a reverse $414, a gate 416, a current source 42, a first switch 422, a second switch 424, a capacitor, and a comparator 428. The first-switch 422 and the second switch 424 respectively control the charging process and the discharging process of the valley 426. Compared with the controller of the DC-to-DC converter circuit shown in the sixth figure, the difference in this embodiment is that the capacitance of your discharge is controlled according to the fixed pulse width signal generated by the on-time unit 435. In order to ensure that the on-switch and the on-switching timing of the second switch 424 are preferably shifted from each other', the gate 416 receives the fixed pulse width signal τ〇η and the comparison signal 413 inverted by the inverter 414 to output a signal. Controlling the conduction of the second switching switch. Thus, when capacitor 426 accumulates a sufficient charge such that the voltage is above the reference voltage, conduction time unit 435 will produce a fixed pulse width signal τ 〇 η. At this time, the electric charge accumulated by the capacitor 426 may be released. In other words, the filter noise unit 41G determines that the DC output time of the DC input ibf voltage is lower than the vertical input (four) voltage by a predetermined time length, and if so, the pulse signal is output. Here, in the present embodiment, the start (end) point of each cycle is the time point at which the shortest deadline time is regretted. In the same way, the DC switch of the eighth riding indicator «the conversion circuit towel can also pass the increase-and-gate receiving reverse 314 output of the reverse signal 315 and the fixed pulse width signal 201134069 No more than the predetermined time

Tori controls the second changeover switch 324 to determine whether or not to output the pulse signal p by the cumulative time. According to Shang Laiming, the method of the present invention can filter out high frequency noises to avoid the noise control period and affect the stability of the output voltage or output current. Moreover, she needs to make materials with low financial resources. Capacitance to reach the job wave method, not only does not need to increase the cost significantly, but also the ability to filter out the noise of higher amplitude (4). At the same time, the setting parameters of 'Benedict of the _# can be used to eliminate the noise function. At the same time, it can also avoid affecting the transient response of the circuit. As described above, the present invention fully complies with the three requirements of the patent: novelty progress and industrial clarity. The present invention has been disclosed above in the preferred embodiment. It should be noted that the present invention should not be interpreted as limiting the scope of the present invention. It should be noted that any changes and permutations equivalent to the embodiment should be set. The invention is intended to be within the scope of the following claims. [First description of the drawings] The first figure is a DC of the conventional application of pulse wave frequency modulation technology. Circuit diagram of the DC-to-DC step-down conversion circuit. The second figure is the signal timing diagram of the DC-to-DC buck converter circuit shown in the first figure. The second figure is the circuit diagram of the conventional switching system for improving the noise sensitivity of the switching system. 15 201134069 The fourth picture is the third The signal timing diagram of the switching system shown in the figure. The fifth figure is a circuit diagram of the switching converter circuit controller according to a first preferred embodiment of the present invention. The sixth figure is a second comparison according to the present invention. The circuit diagram of the DC-to-DC buck conversion circuit of the preferred embodiment. The seventh figure is the signal timing diagram of the DC-to-DC buck conversion circuit shown in the sixth figure. The eighth figure is a third comparison according to the present invention. The schematic diagram of the circuit of the DC-to-DC boost converter circuit of the preferred embodiment. The ninth figure is the timing diagram of the signal of the change of the power of Zhao Qing (10). The tenth figure is the light touch compensation according to the present invention. Schematic diagram of the controller of the DC-to-DC boost converter circuit. [Main component symbol description] Prior art: Controller 10, 10' Comparator 12 Amplifier 14, 15 Low-pass waver 16 Adder 18 Solid Switch SW 31 pulse width controller 22 drives the comparator 24 201 134 069 32 fixed operating time synchronization circuit diode output capacitor C L D inductance resistors Rl, R2

φ output voltage VOUT

Voltage feedback signal VFB reference signal Vref control signal Sc input voltage VIN amplification filter signal FBS output signal FBX output signal FBX The present invention: filter noise unit 110, 210, 310, 410 comparison unit 112, 212, 312, 412 delay unit 120 On-time unit 135, 235, 335, 435 drive unit 150, 250, 350, 450 17 201134069

Feedback signal FB reference signal Vrel

Pulse signal PWM fixed pulse width signal Ton control signal Gate comparison signal 213, 313, 413 reverser 214, 314, 414 current source 22 421 first switch 222, 322, 422 second switch 224, 324, 424 Capacitor Transmitter 225, 325, 425 Capacitors 226, 326, 426 Comparators 228, 328, 428 Upper Edge Trigger Units 230, 330, 430 Shortest Cutoff Time Units 245, 340, 440 and Gate 416 First Switch M1 Second Switch M2

Inductance L

Output Capacitor C Resistor Rl, R2 Load 260, 360 201134069 First Current Source 321 Second Current Source 323 Output Voltage V0UT Feedback Signal FB Reference Signal Vrel Reference Voltage Vb Pulse Signal PWM Fixed Pulse Width Signal Ton First Control Signal UG Current Detection signal CS Second control signal LG Inductor current IL Shortest off time signal Toff First period Ή Second period Τ 2 Third period Τ 3 Fourth period Τ 4 Fifth period Τ 5 Transistor switch M3 Current detection circuit R Load current I load 19

Claims (1)

201134069 VII. Patent application scope: ^ A controller for anti-noise switching conversion circuit, comprising: a filtering noise unit, according to a predetermined time length and a condition that the output voltage of the switching conversion circuit is lower than a predetermined output voltage Determining, and determining whether to output a pulse signal according to the judgment result; - conducting a time unit, outputting a fixed pulse width signal according to the pulse signal; and - driving unit, controlling the switching conversion circuit according to the fixed pulse width signal, The output voltage is stabilized at the predetermined output voltage. 2. The controller of the anti-noise switching conversion circuit according to claim 1, wherein the filtering noise unit outputs the pulse signal when the output voltage continues to be lower than the predetermined output voltage for the predetermined length of time. . The controller of the anti-noise switching conversion circuit according to claim 2, wherein the sigma filtering unit comprises a comparison unit and a delay single value, and the comparison unit is used for outputting the electric ship at the output Voltage output - compares the signal, and the delay unit illuminates the pulse signal at the tb. 4. If the application of the patent (4) 1 item of the anti-missing conversion conversion circuit = the device 'the towel's Hexun unit in each job _ the 丨 丨 丨 低于 低于 低于 低于 低于 低于 低于If the predetermined length of time is, the 20 201134069 pulse wave signal is output. 5. If you apply for a special (4) 4 _ the controller of the anti-missing conversion circuit 'the towel's age-based unit contains - compare single mosquito - cumulative delay unit, the comparison __ wheel output voltage is lower than the Gud output The voltage, if it is, is output-compared to the length of time that the delay is greater than the length of time during which the cumulative delay is accumulated, and if so, the pulse signal is output. 6. An anti-noise switching conversion circuit comprising: a conversion circuit for transmitting a power of at least a control-to-DC input power source to an output terminal to provide a DC output voltage for driving a load; and a The controller performs, according to a predetermined length of time and the DC output voltage of the conversion circuit is lower than a predetermined voltage, and determines whether to output the m) control signal, wherein the at least the control signal is The pulse width is a fixed width. • The anti-noise switching conversion circuit according to item 6 of the patent scope of claim π, wherein the X controller outputs the at least-control signal when the DC touch voltage is lower than the predetermined time (4). 8. The anti-noise collision type circuit of claim 6, wherein the control unit comprises a comparison unit and a delay unit, and the comparison unit is determined by the straight 21 201134069, and the stream output voltage is lower than the predetermined output. When the voltage is output, a comparison signal is outputted, and the delay unit outputs the at least one control signal when the accumulated time length of the comparison signal reaches the predetermined length of time in each period. 9. A controller for an anti-noise switching converter circuit, comprising: a filter noise unit, wherein the load current is lower than a predetermined output current according to a predetermined length of time and the switching converter circuit provides a load to a load Determining, and determining whether to output a pulse signal according to the judgment result; a conduction time unit 'outputting a fixed pulse width signal according to the pulse signal; and a driving unit, controlling the switching conversion circuit according to the fixed pulse width signal The load current is stabilized at the predetermined output current. 10. The controller of the anti-noise switching conversion circuit of claim 9, wherein the filter noise unit outputs the pulse signal when the load current continues to be lower than the predetermined output current for the predetermined length of time. . 11. The controller of the anti-noise switching conversion circuit according to claim 10, wherein the 泸 and the noise unit comprise a comparison unit and a delay unit, and the comparison unit determines whether the load current is lower than the The output current is predetermined, and if so, a comparison signal is output 'the delay unit determines whether the comparison signal continues for the predetermined length of time'. If yes, the pulse signal is output. 22 201134069 1 p ^ An anti-noise switching conversion circuit comprising: a conversion circuit for transmitting power of a constant input power source to a wheel output terminal according to at least one control signal to provide a DC output voltage for driving a load; And the controller is determined according to a predetermined length of time and a state in which the switching converter circuit supplies a load current lower than a predetermined output current, and outputs a pulse signal according to the determination result, wherein the at least The pulse width of a control signal is a fixed width. 13. The anti-noise switching conversion circuit of claim 12, wherein the controller outputs the at least one control signal when the load current continues to be lower than the predetermined output current for the predetermined length of time. 14. The anti-noise switching conversion circuit of claim 12, wherein the controller comprises a comparison unit and a delay unit, and the comparison unit outputs a comparison signal when the load current is lower than the predetermined output current. And the delay unit rotates the at least one control signal when the accumulated time length of the comparison signal is determined in the parent period for the predetermined length of time. twenty three