TWI403079B - De-glitch switching power supply circuit and controller for controlling the same - Google Patents

Description

Anti-noise switching conversion circuit and controller thereof

The invention relates to a switching conversion circuit and a controller thereof, in particular to a switching conversion circuit with anti-noise capability and a controller thereof.

Switching conversion circuit is the mainstream in today's power supply. It has the advantages of high conversion efficiency, small circuit size and low power consumption during no-load. However, the disadvantage is that the circuit is more complicated, and the chopping is larger and the electromagnetic interference is larger. . At present, there are two main control methods for switching converter circuits on the market, one is Pulse Width Modulated (PWM) and the other is Pulse Frequency Modulated (PFM). Since the pulse width modulation technology is a fixed frequency operation, electromagnetic wave interference is relatively easy to filter out and has strong anti-noise capability, but the disadvantage is that the circuit conversion efficiency is low and the transient response is slow at light loads. In contrast, the pulse wave frequency modulation technology has the advantages of high conversion efficiency and fast transient response, but the electromagnetic wave interference caused by it is less easy to filter out and the ability to resist noise is weak.

Please refer to the first figure, which is a circuit diagram of a DC-to-DC buck conversion circuit using a pulse frequency modulation technique. The DC-to-DC buck conversion circuit includes a switch SW, a synchronous diode D, an inductor L, an output capacitor C, a voltage detecting circuit composed of resistors R1 and R2, and a controller 10. The voltage detecting circuit detects one of the output voltages VOUT of the DC-to-DC buck conversion circuit and generates a voltage feedback signal VFB accordingly. The controller 10 includes a comparator 12, a fixed pulse width controller 22, and a driver 32. The comparator 12 receives the voltage feedback signal VFB and a reference signal Vref, and triggers the fixed pulse width controller 22 to generate a fixed pulse width when detecting that the level of the voltage feedback signal VFB is lower than the reference signal Vref. The pulse signal is sent to the driver 32. The driver 32 generates the control signal Sc according to the pulse signal of the fixed pulse width controller 22 to switch the switch SW, thereby controlling the magnitude of the power transmitted from the input voltage VIN to the output terminal, so that the output voltage VOUT is stabilized near a voltage.

Next, please refer to the second figure, which is the signal timing diagram of the DC-to-DC buck converter circuit shown in the first figure. When the voltage feedback signal VFB falls to the level of the reference signal Vref, the controller 10 generates a control signal Sc of a fixed pulse width, so that the switch SW is turned on to transfer power to the output terminal, so that the output voltage VOUT rises. Due to the interference of the circuit noise, the voltage feedback signal VFB is chopped, and the controller 10 has a misjudgment and affects the stability of the output voltage VOUT. As shown in the figure, the portion circled by the dotted circle Q causes the controller 10 to malfunction and output the control signal Sc early due to the interference of the noise, so that the highest value of the output voltage VOUT circled by the dotted circle S is significantly higher than other periods. .

In order to filter out the interference of the noise, a device and a method for improving the noise sensitivity of the switching system are disclosed in U.S. Patent No. 7,023,253. Please refer to the third figure, which is a circuit diagram of the switching system disclosed in the above patent, wherein the controller 10' includes two amplifiers 14, 15, a low pass filter 16, an adder 18, a comparator 24 and a fixed Working time circuit 31. The amplifier 14 amplifies the voltage feedback signal VFB by K times and outputs an amplification signal FBF. The amplifier 15 amplifies the voltage feedback signal VFB by N times, outputs it, and filters it through the low-pass filter 16 into an amplification filter signal FBS. The adder 18 superimposes the amplified signal FBF and the amplified filtered signal FBS to form an output signal FBX. The comparator 24 compares the output signal FBX with the reference signal Vref, and triggers the fixed working time circuit 31 to generate the control signals S1 and S2 to control the switching of the first switch SW1 and the second switch SW2 when the output signal FBX is lower than the reference signal Vref. Please refer to the fourth figure, which is the signal timing diagram of the switching system shown in the third figure. Since the level of the amplification signal FBF is improved, the level of the noise located in the trough is easily moved away from the trough to filter out the noise.

However, since the low-pass filter 16 used in the above patent for filtering noise requires a large capacitor to achieve the filtering function, the chip (DIE) needs to increase the area to set the filter capacitor, or when the external filter capacitor is set. It is necessary to increase the number of pins of the chip to increase the cost, and the noise of the higher amplitude may still cause the circuit to malfunction, so that the stability of the output voltage is still affected.

In view of the problem of increasing the circuit cost caused by the low-pass filter in the filtering noise of the prior art and the inability to completely filter out the high amplitude noise, the present invention can not only avoid the substantial increase of the circuit cost by using the time judgment method. The high amplitude amplitude noise can also be filtered out, and the parameters can be filtered out by appropriate settings to avoid affecting the transient response of the circuit.

To achieve the above objective, the present invention provides a controller for an anti-noise switching conversion circuit, comprising a filter noise unit, an on-time unit and a driving unit. The filtering noise unit determines according to a predetermined time length and a condition that one of the switching conversion circuits has an output voltage lower than a predetermined output voltage, and determines whether to output a pulse signal according to the determination result. The on-time unit outputs a fixed pulse width signal according to the pulse signal. The driving unit controls the switching conversion circuit according to the fixed pulse width signal to stabilize the output voltage to a predetermined output voltage.

The invention also provides an anti-noise switching conversion circuit, comprising a conversion circuit and a controller. The conversion circuit transmits the power of the input power source to an output according to the at least one control signal to provide a DC output voltage for driving a load. The controller determines whether the DC output voltage of the switched conversion circuit is lower than a predetermined output voltage according to a predetermined time length, and determines whether to output at least one control signal according to the determination result, wherein the pulse width of the at least one control signal is one Fixed width.

The invention also provides another controller for the anti-noise switching conversion circuit, comprising a filter noise unit, an on-time unit and a driving unit. The filter noise unit determines according to a predetermined length of time and a state in which the switching converter circuit supplies a load current to a load lower than a predetermined output current, and determines whether to output a pulse signal according to the determination result. The on-time unit outputs a fixed pulse width signal according to the pulse signal. The driving unit controls the switching converter circuit according to the fixed pulse width signal to stabilize the load voltage to a predetermined output current.

The invention also provides another anti-noise switching conversion circuit, comprising a conversion circuit and a controller. The conversion circuit transmits the power of the input power source to an output according to the at least one control signal to provide a DC output voltage for driving a load. The controller determines according to a predetermined length of time and a state in which the switching converter circuit supplies a load current to a load below a predetermined output current, and determines whether to output a pulse signal according to the determination result, wherein at least one pulse of the control signal The width is a fixed width.

The above summary and the following detailed description are exemplary in order to further illustrate the scope of the claims. Other objects and advantages of the present invention will be described in the following description and drawings.

Please refer to FIG. 5, which is a circuit diagram of a switching converter circuit controller according to a first preferred embodiment of the present invention. The switching converter circuit controller includes a filter noise unit 110, an on-time unit 135, and a driving unit 150. The filter noise unit 110 includes a comparison unit 112 and a delay unit 120. The comparison unit 112 receives one of the feedback signals FB representing the load state of the switching converter circuit (eg, the voltage across the load, the current of the load, etc.) and a reference signal Vre1, which is generated when the feedback signal FB is lower than the reference signal Vre1. Compare the signal to the delay unit of 120. The delay unit 120 receives the comparison signal and determines whether the comparison signal continues for a predetermined length of time or determines whether the accumulated time of the comparison signal exceeds a predetermined length of time in each period, and if so, outputs a pulse signal PWM. The on-time unit 135 generates a fixed pulse width signal Ton after receiving the pulse signal PWM. The driving unit 150 generates at least one control signal Gate according to the fixed pulse width signal Ton to control the operation of the switching conversion circuit.

Therefore, when the noise causes the timing of the feedback signal FB to be instantaneous but is lower than the level of the reference signal Vre1, the comparison unit 112 temporarily outputs the comparison signal to the delay unit 120, but the output time is shorter than the predetermined time length, and The delay unit 120 is not caused to output the pulse signal PWM. In this way, it is ensured that the noise does not affect the operational stability of the switched converter circuit. When the output voltage of the switching converter circuit is lower than the predetermined output voltage, the feedback signal FB is continuously lower than the reference signal Vre1, and the delay unit 120 outputs the pulse signal PWM, so that the on-time unit 135 generates a fixed pulse. Wide signal Ton. The driving unit 150 will also generate the at least one control signal Gate according to the fixed pulse width signal Ton to cause the switching conversion circuit to transmit power to the output terminal, so that the level of the feedback signal FB is raised. Moreover, by appropriately setting the predetermined length of time, not only the influence of the noise can be filtered, but also the better transient response capability of the switched converter circuit can be maintained.

Please refer to the sixth figure, which is a circuit diagram of a DC-to-DC buck conversion circuit according to a second preferred embodiment of the present invention. The DC-to-DC buck conversion circuit includes a filter noise unit 210, an upper edge trigger unit 230, an on-time unit 235, a shortest off-time unit 245, a drive unit 250, a first switch M1, and a second switch. M2, an inductor L, an output capacitor C, and a voltage detecting circuit composed of resistors R1 and R2 for driving a load 260. The voltage detecting circuit detects one of the output voltages VOUT generated by the DC-to-DC buck converting circuit to generate a feedback signal FB representing one of the magnitudes of the output voltage VOUT.

The filter noise unit 210 includes a comparison unit 212, an inverter 214, a current source 221, a first switch 222, a second switch 224, a capacitor 226, and a comparator 228. The first switching switch 222 and the second switching switch 224 respectively control the charging process and the discharging process of the capacitor 226, and the conduction timings of the first switching switch 222 and the second switching switch 224 are preferably set to be shifted from each other. The comparison unit 212 receives the feedback signal FB and a reference signal Vre1, and generates a high-level comparison signal 213 when the feedback signal FB is lower than the reference signal Vre1, so that the first switching switch 222 is turned on. The first switch 222 is coupled to the current source 221 and the capacitor 226 to charge the capacitor 226 with the current of the current source 221 when turned on. At this time, the inverter 214 inverts the comparison signal 213 to output a low level signal to turn off the second switching switch 224, so that one of the capacitors 226 gradually rises across the voltage 225. When the feedback signal FB is higher than the reference signal Vre1, the comparison unit 212 generates a low level comparison signal 213 to turn off the first switch 222 to stop charging the capacitor 226. At this time, the inverter 214 inverts the comparison signal 213 to output a high level signal to turn on the second switching switch 224 to discharge the capacitor 226, so the capacitor cross voltage 225 drops to zero. The comparator 228 compares the capacitor voltage 225 and a reference voltage Vb, and outputs a pulse signal PWM when the capacitor voltage 225 is higher than the reference voltage Vb.

The upper edge trigger unit 230 is coupled to the filter noise unit 210. When the upper edge of the pulse signal PWM is detected, an upper edge detection signal is generated to trigger the on time unit 235 to generate a fixed pulse width signal Ton. The driving unit 250 controls the switching of the first switch M1 according to the fixed pulse width signal Ton to generate a first control signal UG, and generates the current detecting signal CS and the first control signal UG according to the current flowing through the second switch M2. A second control signal LG controls the switching of the second switch M2, so that when the first switch M1 is turned off, the inductor current IL of the inductor L can be freewheeled through the second switch M2. The fixed pulse width signal Ton is also transmitted to the shortest cutoff time unit 245. When the minimum cutoff time unit 245 detects the lower edge of the fixed pulse width signal Ton, the shortest cutoff time signal Toff with the fixed pulse width is generated to the upper edge trigger unit. 230. The upper edge triggering unit 230 stops detecting the upper edge of the pulse signal PWM during the shortest off-time signal Toff to ensure that the energy stored in the inductor L can be released.

Next, please refer to the seventh figure, which is the signal timing diagram of the DC-to-DC buck converter circuit shown in the sixth figure. Please also refer to the sixth figure. When the level of the feedback signal FB is lower than the reference signal Vre1, the comparison signal 213 is turned to the high level and the inverted signal 215 is turned to the low level, so that the first switch 222 is turned The second switch 224 is turned off. At this point, current source 221 begins to charge capacitor 226, causing capacitor across voltage 225 to gradually rise from zero. When the capacitor cross voltage 225 rises above the reference voltage Vb, the comparator 228 outputs the high level pulse signal PWM, so that the upper edge trigger unit 230 triggers the on time unit 235 to generate the fixed pulse width signal Ton for a fixed length of time. At this time, the driving unit 250 generates the first control signal UG according to the fixed pulse width signal Ton to turn on the first switch M1, so that the input voltage VIN starts to transmit power to the DC-to-DC buck conversion circuit, and the inductor current IL starts to rise. When the fixed pulse width signal Ton is turned to the low level after a fixed length of time, the shortest cutoff time unit 245 generates the shortest cutoff time signal Toff having a fixed pulse width (time length dt). At this time, the driving unit 250 outputs the low level first control signal UG to turn off the first switch M1, and outputs the high level second control signal LG to turn on the second switch M2, and the inductor current IL passes through the second switch M. flow. When the freewheeling inductor current IL gradually drops to zero, the driving unit 250 outputs the low level second control signal LG (when the first control signal UG remains at the low level), and the second switch M2 is turned off.

As shown in the seventh figure, during the first period T1 and the fourth period T4, the noise does not affect the judgment of the comparison unit 212, but in the second period T2, the third period T3, and the fifth period T5, At this time, the level of the feedback signal FB is close to the level of the reference signal Vre1, so that the comparison unit 212 has a misjudgment. However, since the time of the influence of the noise is short, the capacitance across the voltage 225 does not rise above the reference voltage Vb, so there is no influence. The time parameter that the capacitor is charged across the voltage 225 to be equal to the reference voltage Vb is TR=Cf*Vb/I1, where Cf is the capacitance value of the capacitor 226, and I1 is the current value of the current source 221. Appropriate setting of the time parameter TR can adjust the filter noise and transient response capability of the circuit.

Please refer to the eighth figure, which is a circuit diagram of a DC-to-DC boost converter circuit according to a third preferred embodiment of the present invention. The DC-to-DC buck conversion circuit includes a filter noise unit 310, an upper edge trigger unit 330, an on-time unit 335, a shortest off-time unit 340, a driving unit 350, a transistor switch M3, an inductor L, An output capacitor C and a current detecting circuit R are used to drive a load 360. The current detecting circuit detects a load current Iload flowing through the load 360 to generate a feedback signal FB representing one of the magnitudes of the load current Iload.

The filter unit 310 includes a comparison unit 312, an inverter 314, a first current source 321, a first switch 322, a second current source 323, a second switch 324, a capacitor 326, and a Comparator 328. The first switch 322 and the second switch 324 respectively control the charging process and the discharging process of the capacitor 326. Please also refer to the ninth figure, which is the signal timing diagram of the DC-to-DC boost converter circuit shown in the eighth figure. The comparison unit 312 receives the feedback signal FB and a reference signal Vre1, and generates a high-level comparison signal 313 when the feedback signal FB is lower than the reference signal Vre1, so that the first switching switch 322 is turned on. The first switch 322 is coupled to the first current source 321 and the capacitor 326, and charges the capacitor 326 with the current of the first current source 321 when turned on. At this time, the inverter 314 inverts the comparison signal 313 to output a low-level reverse signal 315 to turn off the second switching switch 324, so that one of the capacitors 326 gradually rises across the voltage 325. When the feedback signal FB is higher than the reference signal Vre1, the comparison unit 312 generates a low level comparison signal 313 to turn off the first switch 322 to stop charging the capacitor 326. At this time, the inverter 314 inverts the comparison signal 313 to output a high level signal to turn on the second switching switch 324. The second switch 324 is coupled to the second current source 323 and the capacitor 326. When turned on, the capacitor 326 is discharged by the current of the second current source 323. Therefore, the capacitor across the voltage 325 begins to decrease. To ensure that the capacitor across voltage 325 returns to zero at the end of each cycle, it is preferred to set the current of the second current source 323 to be greater than the current of the first current source 321. The comparator 328 compares the capacitor across voltage 325 and a reference voltage Vb, and outputs a pulse signal PWM when the capacitor crossover voltage 325 is higher than the reference voltage Vb.

The upper edge triggering unit 330 generates an upper edge detection signal to trigger the on-time unit 335 to generate a fixed pulse width signal Ton when detecting the upper edge of the pulse signal PWM. The driving unit 350 generates a control signal Gate to conduct the crystal switch M3 according to the fixed pulse width signal Ton. The fixed pulse width signal Ton is also transmitted to the shortest cutoff time unit 340. When the minimum cutoff time unit 340 detects the lower edge of the fixed pulse width signal Ton, the shortest cutoff time signal Toff with the fixed pulse width is generated to the upper edge trigger unit. 330. The upper edge triggering unit 330 stops detecting the upper edge of the pulse signal PWM during the shortest off-time signal Toff to ensure that the energy stored in the inductor L can be released.

Please note the dotted circles A and B in the figure, which represent the interference of the output voltage during the rising and falling processes. Since the capacitance across voltage 325 at this time is at a relatively high level and a relatively low level, short-term interference of high frequency noise is insufficient to affect the output of the comparator 328.

Please refer to the tenth figure, which is a circuit diagram of a controller of a DC-to-DC boost converter circuit according to a fourth preferred embodiment of the present invention. The DC-to-DC buck conversion circuit includes a filter noise unit 410, an upper edge trigger unit 430, an on-time unit 435, a shortest off-time unit 440, and a driving unit 450. The filter unit 410 includes a comparison unit 412, an inverter 414, a gate 416, a current source 421, a first switch 422, a second switch 424, a capacitor 426, and a comparator 428. The first switch 422 and the second switch 424 respectively control the charging process and the discharging process of the capacitor 426. Compared with the controller of the DC-to-DC boost converter circuit shown in FIG. 6, the difference in this embodiment is that the discharge of the capacitor 426 is controlled according to the fixed pulse width signal Ton generated by the on-time unit 435. To ensure that the turn-on timings of the first switch 422 and the second switch 424 are preferably shifted from each other, the gate 416 receives the fixed pulse width signal Ton and the comparison signal 413 inverted by the inverter 414 to output the signal control. The switch 424 is turned on. Thus, when capacitor 426 accumulates a sufficient charge to cause the voltage to be higher than reference voltage Vb, on-time unit 435 will generate a fixed pulse width signal Ton. At this time, the electric charge accumulated by the capacitor 426 may be released. In other words, the filter noise unit 410 determines whether the accumulated time of the DC output voltage lower than the predetermined output voltage exceeds a predetermined length of time in each cycle, and if so, outputs a pulse signal PWM. Wherein, in the present embodiment, the start (end) point of each cycle is the time when the shortest cutoff time signal Toff is generated.

Similarly, the DC-to-DC boost converter circuit shown in FIG. 8 can also control the second switch 324 by adding a reverse signal 315 and a fixed pulse width signal Ton outputted by the gate receiving inverter 314. It is determined whether the pulse signal PWM is outputted by whether the accumulated time exceeds a predetermined length of time.

According to the above description, the present invention utilizes the method of time determination to filter out high frequency noise, avoiding the misjudgment caused by the noise and affecting the stability of the output voltage or the output current. Moreover, compared with the method of using a large capacitor to achieve filtering in a low-pass filter, not only does it not require a substantial increase in cost, but also the ability to filter out noise for higher amplitude. At the same time, the circuit of the invention can be set with appropriate parameters, and the noise response function can be avoided, and the transient response of the circuit can be avoided.

As described above, the present invention fully complies with the three requirements of the patent: novelty, advancement, and industrial applicability. The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

Prior art:

10, 10’. . . Controller

12. . . Comparators

14,15. . . Amplifier

16. . . Low pass filter

18. . . Adder

twenty two. . . Fixed pulse width controller

twenty four. . . Comparators

32. . . driver

31. . . Fixed working time circuit

SW. . . switch

D. . . Synchronous diode

L. . . inductance

C. . . Output capacitor

R1, R2. . . resistance

VOUT. . . The output voltage

VFB. . . Voltage feedback signal

Vref. . . Reference signal

Sc. . . Control signal

VIN. . . Input voltage

FBS. . . Amplified filter signal

FBX. . . Output signal

FBX. . . Output signal

this invention:

110, 210, 310, 410. . . Filter noise unit

112, 212, 312, 412. . . Comparison unit

120. . . Delay unit

135, 235, 335, 435. . . On time unit

150, 250, 350, 450. . . Drive unit

FB. . . Feedback signal

Vre1. . . Reference signal

PWM. . . Pulse signal

Ton. . . Fixed pulse width signal

Gate. . . Control signal

213, 313, 413. . . Comparison signal

214, 314, 414. . . Inverter

221, 421. . . Battery

222, 322, 422. . . First switch

224, 324, 424. . . Second switch

225, 325, 425. . . Capacitor crossover

226, 326, 426. . . capacitance

228, 328, 428. . . Comparators

230, 330, 430. . . Upper edge trigger unit

245, 340, 440. . . Shortest deadline unit

416. . . Gate

M1. . . First switch

M2. . . Second switch

L. . . inductance

C. . . Output capacitor

R1, R2. . . resistance

260, 360. . . load

321‧‧‧First current source

323‧‧‧second current source

VOUT‧‧‧ output voltage

FB‧‧‧ feedback signal

Vre1‧‧‧ reference signal

Vb‧‧‧reference voltage

PWM‧‧‧ pulse signal

Ton‧‧‧ fixed pulse width signal

UG‧‧‧First control signal

CS‧‧‧current detection signal

LG‧‧‧second control signal

IL‧‧‧Inductor Current

Toff‧‧‧Short deadline signal

T1‧‧‧ first cycle

T2‧‧‧ second cycle

T3‧‧‧ third cycle

T4‧‧‧ fourth cycle

T5‧‧‧ fifth cycle

M3‧‧‧Chip Switch

R‧‧‧ current detection circuit

I load‧‧‧ load current

The first figure is a circuit diagram of a DC-to-DC buck conversion circuit using a pulse frequency modulation technique.

The second figure is the signal timing diagram of the DC-to-DC buck conversion circuit shown in the first figure.

The third figure is a circuit diagram of a conventional switching system for improving the noise sensitivity of the switching system.

The fourth figure is the signal timing diagram of the switching system shown in the third figure.

Figure 5 is a circuit diagram of a switching converter circuit controller in accordance with a first preferred embodiment of the present invention.

Figure 6 is a circuit diagram of a DC-to-DC buck conversion circuit according to a second preferred embodiment of the present invention.

The seventh figure is the signal timing diagram of the DC-to-DC buck conversion circuit shown in the sixth figure.

Figure 8 is a circuit diagram of a DC-to-DC boost converter circuit in accordance with a third preferred embodiment of the present invention.

The ninth figure is the signal timing diagram of the DC-to-DC boost converter circuit shown in the eighth figure.

Figure 11 is a circuit diagram of a controller of a DC-to-DC boost converter circuit in accordance with a fourth preferred embodiment of the present invention.

110. . . Filter noise unit

112. . . Comparison unit

120. . . Delay unit

135. . . On time unit

150. . . Drive unit

FB. . . Feedback signal

Vre1. . . Reference signal

PWM. . . Pulse signal

Ton. . . Fixed pulse width signal

Gate. . . Control signal

Claims (10)

A controller for an anti-noise switching conversion circuit, comprising: a filter noise unit, determining according to a predetermined time length and a condition that an output voltage of the switched conversion circuit is lower than a predetermined output voltage, and determining according to the judgment result Determining whether to output a pulse signal; a conduction time unit, outputting a fixed pulse width signal according to the pulse signal; and a driving unit, controlling the switching conversion circuit according to the fixed pulse width signal to stabilize the output voltage a predetermined output voltage, wherein the filter noise unit includes a comparison unit and a delay unit, the comparison unit outputs a comparison signal when the output voltage is lower than the predetermined output voltage, the delay unit is continued for the predetermined time in the comparison signal The pulse signal is outputted in length. The controller of the anti-noise switching conversion circuit of claim 1, wherein the filtering noise unit outputs the pulse signal when the output voltage continues to be lower than the predetermined output voltage for the predetermined length of time. The controller of the anti-noise switching conversion circuit of claim 1, wherein the filtering noise unit determines, at each cycle, whether the accumulated time of the output voltage lower than the predetermined output voltage exceeds the predetermined time length If yes, the pulse signal is output. The controller of the anti-noise switching conversion circuit of claim 3, wherein the filtering noise unit comprises a comparison unit and a cumulative delay unit, and the comparison unit determines whether the output voltage is lower than the predetermined output. The voltage, if yes, outputs a comparison signal, the cumulative delay unit determines whether the length of time during which the comparison signal is accumulated continues for the predetermined length of time, and if so, outputs the pulse signal. An anti-noise switching conversion circuit comprising: a conversion circuit for transmitting power of a constant input power source to an output terminal according to at least one control signal to provide a DC output voltage for driving a load; and a controller Determining, according to a predetermined length of time and a condition that the DC output voltage of the conversion circuit is lower than a predetermined output voltage, and determining whether to output the at least one control signal according to the determination result, wherein a pulse width of the at least one control signal is fixed Width; wherein the controller includes a comparison unit and a delay unit, the comparison unit outputs a comparison signal when the DC output voltage is lower than the predetermined output voltage, the delay unit is accumulated in the comparison signal in each period The at least one control signal is output when the length of time reaches the predetermined length of time. The anti-noise switching conversion circuit of claim 5, wherein the controller outputs the at least one control signal when the DC output voltage continues to be lower than the predetermined output voltage for the predetermined length of time. A controller for an anti-noise switching conversion circuit includes: a filter noise unit, which is determined according to a predetermined length of time and a state in which the switching converter circuit supplies a load current to a load below a predetermined output current, And determining, according to the determination result, whether to output a pulse signal; a conduction time unit, outputting a fixed pulse width signal according to the pulse signal; and a driving unit, controlling the switching conversion circuit according to the fixed pulse width signal to make the load The current is stabilized at the predetermined output current; wherein the filter noise unit comprises a comparison unit and a delay unit, the comparison unit determines whether the load current is lower than the predetermined output current, and if yes, outputs a comparison signal, and the delay unit determines Whether the comparison signal continues for the predetermined length of time, and if so, outputs the pulse signal. The controller of the anti-noise switching conversion circuit of claim 7, wherein the filter noise unit outputs the pulse signal when the load current continues to be lower than the predetermined output current for the predetermined length of time. An anti-noise switching conversion circuit comprising: a conversion circuit for transmitting power of a constant input power source to an output terminal according to at least one control signal to provide a DC output voltage for driving a load; and a controller Determining according to a predetermined length of time and a state in which the switching converter circuit supplies a load current to a load below a predetermined output current, and Determining whether to output a pulse signal, wherein the pulse width of the at least one control signal is a fixed width; wherein the controller comprises a comparison unit and a delay unit, and comparing the unit to the load current is lower than the predetermined output When the current is output, a comparison signal is outputted, and the delay unit outputs the at least one control signal when the accumulated time length of the comparison signal is determined in each period for the predetermined length of time. The anti-noise switching conversion circuit of claim 9, wherein the controller outputs the at least one control signal when the load current continues to be lower than the predetermined output current for the predetermined length of time.