CN103973103B - Voltage conversion circuit - Google Patents
Voltage conversion circuit Download PDFInfo
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- CN103973103B CN103973103B CN201310045504.0A CN201310045504A CN103973103B CN 103973103 B CN103973103 B CN 103973103B CN 201310045504 A CN201310045504 A CN 201310045504A CN 103973103 B CN103973103 B CN 103973103B
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Abstract
The present invention is a kind of voltage conversion circuit.Voltage conversion circuit comprises: one drives input node；One drives output node；One drives reverser, and input is for receiving a drive input signal, and outfan exports a driving reverse signal reverse with this drive input signal；And, one first switch, determine conducting state according to this driving reverse signal, when this driving reverse signal is low level, this first switch conduction also exports this ground voltage in this driving output node；And, when this driving reverse signal is high level, this first switch presents off state and produces a conversion voltage in this driving output node.
Description
Technical field
The invention relates to a kind of voltage conversion circuit, and change mode in fact in particular to one by strings of transistors
Existing voltage conversion circuit.
Background technology
Supply voltage increase (boost up) is become higher by the function of boost converter (Boost Converter)
Conversion voltage.Such as: utilize the supply voltage of 1.8V to produce the conversion voltage of 3.6V.
Known technology collocation system single-chip (system on chip, referred to as SoC) passes through boost converter, will conversion
When voltage Vout is supplied to load circuit, commonly used be external in printed circuit board (PCB) (Printed Circuit Board, be called for short
For PCB) nmos pass transistor.
Refer to Fig. 1, it is that known technology is outside system single chip, it is provided that the schematic diagram of voltage conversion circuit.This figure
Formula with Vdd represent supply voltage, and voltage conversion circuit (booster circuit) by drive output node Sout and output voltage is electric
Put down the conversion voltage for 2*Vdd.
The nmos pass transistor herein selected, it is pressure that it can bear, and the conversion voltage related impact exported is
High voltage.
At this graphic in, the circuit in addition to system single chip 1, all set along with system single chip in printed circuit
On plate.Wherein, one end of inductance (inductor) is electrically connected to supply voltage Vdd, the other end then with the leakage of nmos pass transistor N1
Pole, the input of Schottky diode (Schottky Diode) are electrically commonly connected to drive output node Sout.Schottky two
The outfan of pole pipe D is electrically connected to electric capacity C.Wherein, electric capacity C is for representing the load capacitance of outside, and node Vc can electrically connect
To outside load.
As seen from Figure 1, nmos pass transistor herein will additionally take the space of printed circuit board (PCB).
Referring to Fig. 2, it is that known technology is inside system single chip, it is provided that the schematic diagram of voltage conversion circuit.In order to
The space of the printed circuit board (PCB) shared by saving, nmos pass transistor is arranged in system single chip 2 by this kind of way.
When designing booster circuit, regardless of whether nmos pass transistor is arranged in system single chip 2, nmos pass transistor N2
Drain electrode and source electrode between all allow for bearing the cross-pressure of 2*Vdd.Therefore, this kind of way need to use high pressure manufacturing process to realize can
Nmos pass transistor N2 with 2*Vdd cross-pressure.
Along with the development of manufacture of semiconductor, the size of semiconductor element is more and more less.Jointly, semiconductor element can hold
Be subject to is pressure more and more lower.Other circuit within system single chip 2 is not required to use high voltage, if in order to only
Account for a fraction of boost converter of allomeric function and must additionally use high-tension processing procedure, for system single chip, this
Plant the degree of difficulty designed during derivative manufacture, and the extra high voltage processing procedure that increases can increase cost.
According to preceding description it is known that how nmos pass transistor is integrated in system single chip, and can take into account in low
The manufacture of compacting journey and production, facing a difficult choice when being still design boost converter.
Summary of the invention
An aspect of of the present present invention is a kind of voltage conversion circuit, comprises: one drives input node；One drives output node；
One drives reverser, is electrically connected between this driving input node, a supply voltage and a ground voltage, and its input is used for receiving
One drive input signal, the driving reverse signal that outfan output is reverse with this drive input signal；And, one first opens
Close, be electrically connected to this driving output node and this supply voltage, and control node by one and be electrically connected to this driving reverser,
This first switch is to determine conducting state according to this driving reverse signal, and when this driving reverse signal is low level, this is the years old
One switch conduction also exports this ground voltage in this driving output node；And, when this driving reverse signal is high level, should
First switch presents off state and produces a conversion voltage in this driving output node.
More preferably understand in order to the above and other aspect of the present invention is had, special embodiment below, and coordinate institute's accompanying drawing
Formula, is described in detail below.
Accompanying drawing explanation
Fig. 1, it is that known technology is outside system single chip, it is provided that the schematic diagram of voltage conversion circuit.
Fig. 2, it is that known technology is inside system single chip, it is provided that the schematic diagram of voltage conversion circuit.
Fig. 3, it is that the present invention is inside system single chip, it is provided that the schematic diagram of voltage conversion circuit.
Fig. 4, its be the present invention voltage conversion circuit collocation output stage time, output stage capacitance voltage change waveform
Figure.
Fig. 5, it is that the present invention utilizes string transistor repeatedly, it is achieved the schematic diagram of voltage conversion circuit.
Fig. 6 A, it is the voltage conversion circuit of the present invention, when input signal is high level, the conducting of internal transistor/
The schematic diagram of closed mode.
Fig. 6 B, it is in Fig. 6 A, the list of each electrodes conduct pressure of the voltage conversion circuit internal transistor of the present invention.
Fig. 7 A, it is the voltage conversion circuit of the present invention, when input signal is low level, the conducting of internal transistor/
The schematic diagram of closed mode.
Fig. 7 B, it is in Fig. 7 A, the list of each electrodes conduct pressure of the voltage conversion circuit internal transistor of the present invention.
Fig. 8, it is the voltage conversion circuit of the present invention, and the level in response to pulse-modulated signal changes, internal each node electricity
The schematic diagram of buckling wave mode.
[main element label declaration]
System single chip 1,2,3, driving stage 301
Buffer stage 303 voltage conversion circuit 30
Detailed description of the invention
In order to improve the disappearance of known technology, the present invention proposes to utilize low pressure transistor, with superposition (cascode)
Mode realizes voltage conversion circuit.According to the embodiment of present invention conception, this kind of voltage conversion circuit can reach 2* by output level
The conversion voltage of Vdd.
Referring to Fig. 3, it is that the present invention is inside system single chip, it is provided that the schematic diagram of voltage conversion circuit.
At this graphic in, the output stage being made up of inductance L, diode D, electric capacity C is external in system single chip 3.
On the other hand, voltage conversion circuit 30 is integrated in system single chip 3, and voltage conversion circuit 30 comprises by driving
The driving stage 301 of reverser INV_drv and first switch M1 composition.Wherein, reverser INV_drv is driven to be electrically connected to drive defeated
Between ingress Sdrv_in, supply voltage Vdd and ground voltage Gnd；First switch M1 is then electrically connected to drive output node
Sout, supply voltage Vdd.Additionally, drive reverser INV_drv and first switch M1 to electrically connect by controlling node Sctrl.
Assume that the first switch M1 is nmos pass transistor, then its grid electrical ties is electrically connected in supply voltage Vdd, source electrode
Control node Sctrl, drain electrode is electrically connected to drive output node Sout.
Simultaneously, it is assumed that the conducting voltage of diode D is 0.45V.
When drive input signal is low level (such as: Vdrv_in=ground voltage Gnd=0V), reverser is driven
INV_drv by related output high level (such as: Vctrl=supplies voltage Vdd) in control node Sctrl.
Now, the first switch M1 closes because the pressure reduction between grid and source electrode is Vdd-Vdd=0V.
When the first switch M1 body is closed, supply voltage Vdd produces electric conduction and flow to drive output joint yet by inductance L
Point.Now, electric capacity C will thus proceed by charging.The voltage now driving output node is about 2*Vdd, and capacitance voltage Vc
Approximate 2*Vdd-0.45.
When drive input signal is high level (such as: Vdrv_in=supplies voltage Vdd), reverser INV_drv is driven
By related output low level (such as: Vctrl=ground voltage Gnd=0V) in controlling node Sctrl.
Now, the first switch M1 turns on because the pressure reduction between grid and source electrode is Vdd-0=Vdd.Pass through
The conducting of the first switch M1, now supply voltage Vdd will produce conducting electric current by inductance L, and this electric conduction flows through by the
One switch M1 flow to ground voltage with driving reverser INV_drv.Therefore, the voltage now driving output node is 0V.
At the same time, electric capacity C can discharge because the voltage of driving output node Sout is relatively low.Therefore,
Capacitance voltage Vc the most slightly will be declined by 2*Vdd-0.45.
Fig. 4, its be the present invention voltage conversion circuit collocation output stage time, output stage capacitance voltage change waveform
Figure.Line segment L1 in graphic represents capacitance voltage Vc and becomes at just started shooting voltage when being also introduced into steady statue of system single chip 3
Change；Line segment L2 then represents the capacitance voltage Vc change in voltage when system single chip 3 enters steady statue.
Assume that the pressure Vdd of element is 4.2V, the most graphic it can be seen that capacitance voltage Vc at system single chip 3 the most not
When entering steady statue, its voltage will be gradually increased to about 8V by 0V.
After further by the partial sector of line segment L2 is amplified, it can be seen that capacitance voltage Vc can 8.02V Yu 8.04V it
Between change.
Wherein, electric capacity C can charge (L2a) when drive input signal is low level, and capacitance voltage Vc now will be by
8.02V gradually rises to 8.04V.On the other hand, electric capacity C can discharge (L2b) when drive input signal is high level.Now
Capacitance voltage Vc will progressively be dropped to 8.02V by 8.04V.
Referring to Fig. 5, it is that the present invention utilizes string transistor repeatedly, it is achieved the schematic diagram of voltage conversion circuit.This is graphic
Illustrate to drive reverser to comprise: second switch M2 and the 3rd switch M3.
Second switch M2 is electrically connected to drive input node Sdrv_in, supply voltage Vdd and first switch M1.Second opens
Close M2 to turn on when drive input signal is low level, and then provide supply voltage Vdd to give control node Sctrl.3rd opens
Close M3 to be electrically connected to drive input node, ground voltage and the first switch M1.3rd switch M3 can be high in drive input signal
Electricity conducts, and then provide ground voltage Gnd to give control node Sctrl.
The most graphic it can be seen that second switch M2 can be PMOS transistor, the 3rd switch M3 can be nmos pass transistor.Its
In, the grid of second switch M2 is electrically connected to drive input node Sdrv_in, source electrode to be electrically connected to supply voltage Vdd, drain electrode electricity
It is connected to control node Sctrl.3rd switch M3's
Grid is electrically connected to drive input node Sdrv_in, source electrode to be electrically connected to ground voltage Gnd, drain electrode is electrically connected to
Control node Sctrl.
Additionally, the body of second switch M2 is electrically connected to source electrode, the body of the 3rd switch M3 is electrically connected to source electrode.
Referring to Fig. 6 A, it is the voltage conversion circuit of the present invention, when input signal is high level, internal transistor
The schematic diagram of conducting state.
Between the voltage conversion circuit and input signal of the present invention, may further provide and comprise the first buffering reverser
The buffer stage 303 of Inv1 and second buffering reverser Inv2.First buffering reverser Inv1 and the second buffering reverser Inv2 is equal
It is electrically connected to supply between voltage Vdd and ground voltage Gnd.
The input of the first buffering reverser Inv1 is electrically connected to input signal Vin, and the first buffering reverser Inv1 uses
In reverse input signal Vin1 that output is reverse with input signal Vin.
The input of the second buffering reverser is electrically connected to the outfan of the first buffering reverser, and the second buffering reverser
Outfan be electrically connected to drive input node Sdrv_in.Second buffering reverser is used for receiving reverse input signal Vin1, and in
Drive input node Srv_in output drive input signal Vdrv_in.Because reverse through two degree, drive input signal
The phase place of Vdrv_in can be consistent with input signal Vin.
Wherein, the second buffering reverser comprises the 4th switch M4 and the 5th switch M5.4th switch M4 is electrically connected to first
The exit point of buffering reverser Inv1, supply voltage Vdd and driving input node Sdrv_in.4th switch M4 is the most defeated
Enter and turn on when signal Vin1 is low level, and then output supply voltage Vdd is in driving input node Sdrv_in.5th switch M5
It is electrically connected to the exit point of the first buffering reverser Inv1, ground voltage Gnd and drives input node Sdrv_in.5th opens
Close M5 to turn on when reverse input signal Vin1 is high level, and then output ground voltage Gnd=0V is in driving input node
Sdrv_in。
As it can be seen, the 4th switch M4 may be assumed that into PMOS transistor, its grid is electrically connected to the first buffering reverser
The exit point of Inv1, source electrode are electrically connected to supply voltage Vdd, drain electrode is electrically connected to drive input node Sdrv_in.In like manner,
5th switch M5 may be assumed that into nmos pass transistor, its grid is electrically connected to the exit point of the first buffering reverser Inv1, source electrode
Be electrically connected to ground voltage Gnd, drain electrode is electrically connected to drive input node Sdrv_in.Additionally, the body of the 4th switch M4 is electrically connected
Be connected to source electrode, the body of the 5th switch M5 is electrically connected to source electrode.
Assume initially that the situation that input signal Vin is high level (Vdd):
When input signal Vin is high level (Vin=Vdd), by the reverse input of the first buffering reverser Inv1 output
Signal Vin1 is 0V, and the second buffering reverser then exports Vdd to driving input node Sdrv_in.
As it was previously stated, now drive reverser because second switch M2 open circuit, the 3rd switch M3 present conducting
Output 0V.Related, drive reverser that output 0V is extremely controlled node Sctrl.Related, the first switch M1 is because of grid voltage
It is 0V for Vdd, source voltage and turns on.
Referring to Fig. 6 B, it is in Fig. 6 A, each electrodes conduct pressure of the voltage conversion circuit internal transistor of the present invention
List.
This graphic first row represents the voltage difference between each electrode of second switch M2；Secondary series represents the 3rd switch
Voltage difference between each electrode of M3；And, the 3rd row represent the voltage difference between each electrode of the first switch M1.
Wherein, the second row represents the potential difference between grid and the source electrode of other transistor；The third line represents individual other
Potential difference between grid and the drain electrode of transistor；Fourth line represents the current potential between drain electrode and the source electrode of other transistor
Difference.Additionally, fifth line represents the potential difference between grid and the body (body) of other transistor；6th row represents individual other
Potential difference between drain electrode and the body of transistor；And, the 7th row represents between body and the source electrode of other transistor
Potential difference.
Wherein, represent the PMOS transistor of second switch M2, represent the nmos pass transistor of the 3rd switch M3, represent first and open
Closing the nmos pass transistor of M1, its body is all connected with source electrode.
Therefore, the voltage difference of Fig. 6 B the 7th row is 0V.And, the grid of these transistors and voltage difference VGB of body,
All being equivalent to voltage difference VGS (VGB=VGS) of grid and source electrode, the i.e. second row is equal with the voltage difference shown in fifth line.Again
Person, the drain electrode of these transistors and voltage difference VDS of source electrode and drain electrode equal with voltage difference VDB of body (VDS=VDB), i.e.
Fourth line is equal to each other with the voltage difference shown in the 6th row.
Hold, when input signal Vin is high level (Vdd), each electrode of second switch M2 voltage differential to each other
It is not: VGS=VGB=0V；VDS=VDB=0V-Vdd=-Vdd；VGD=Vdd-0V=Vdd；And, VBS=0V.
When input signal Vin is high level (Vdd), the 3rd switch each electrode of M3 voltage difference to each other is respectively as follows:
VGS=VGB=Vdd-0V=Vdd；VDS=VDB=0V-0V=0V；VGD=Vdd-0V=Vdd；And, VBS=0V.
When input signal Vin is high level (Vdd), first switch each electrode of M1 voltage difference to each other is respectively as follows:
VGS=VGB=Vdd-0V=Vdd；VDS=VDB=0-0V=0V；VGD=Vdd-0V=Vdd；And, VBS=0V.
Referring to Fig. 7 A, it is the voltage conversion circuit of the present invention, when input signal is low level, internal transistor
It is Turned on/off the schematic diagram of state.
Then, illustrate that input signal Vin is low level situation:
When input signal Vin is low level 0V, first passes through the first buffering reverser and export Vdd, delay via second
0V is exported after rushing reverser Inv2.
As it was previously stated, now drive reverser will export Vdd, wherein second switch M2 present conducting, the 3rd switch M3 in
Existing open circuit.Therefore, drive reverser by the source electrode of output Vdd to M1.Related, the first switch M1 because grid voltage be Vdd,
Source voltage is Vdd, thus presents off state.
Now, the drain electrode of the first switch M1 is 2*Vdd with the voltage of Vout, and the voltage of capacitance voltage Vc is about 2*
Vdd-0.45V。
Referring to Fig. 7 B, it is in Fig. 7 A, each electrodes conduct pressure of the voltage conversion circuit internal transistor of the present invention
List.The meaning representated by each row and each column herein is all similar to Fig. 6 B, thus repeats no more.
Holding, when input signal Vin is low level (0V), each electrode of second switch M2 voltage difference to each other is respectively
For: VGS=VGB=0V-Vdd=-Vdd；VDS=VDB=Vdd-Vdd=0V；VGD=0V-Vdd=-Vdd；And, VBS=
0V。
When input signal Vin is low level (0V), the 3rd switch each electrode of M3 voltage difference to each other is respectively as follows:
VGS=VGB=0V-0V=0V；VDS=VDB=Vdd-0V=Vdd；VGD=0V-Vdd=-Vdd；And, VBS=0V.
When input signal Vin is low level (0V), first switch each electrode of M1 voltage difference to each other is respectively as follows:
VGS=VGB=Vdd-Vdd=0V；VDS=VDB=2*Vdd-Vdd=Vdd；VGD=Vdd-2*Vdd=-Vdd；And, VBS
=0V.
Inspecting when input signal changes further, the voltage difference between each pole of each switch has a following relation:
The 4th row according to Fig. 6 B, 7B are it can be seen that for the first switch M1, the pressure reduction between electrode may be
Vdd、-Vdd、0V。
Secondary series according to Fig. 6 B, 7B it can be seen that for second switch M2, the pressure reduction between electrode may be-
Vdd、0V。
The 3rd row according to Fig. 6 B, 7B it can be seen that for the 3rd switch M3, the pressure reduction between electrode may be-
Vdd、Vdd、0V。
Therefore, each transistor in voltage conversion circuit, the voltage difference between its Different electrodes all without more than Vdd,
Therefore the present invention need not use high voltage bearing element.
In a general case, input signal Vin can be with pulse-modulated signal (pulse width modulation, letter
It being referred to as PWM) mode exists.Pwm signal has between high period and between low period, it is assumed that the voltage between high period be Vdd,
Voltage between low period is 0V.About producing method and the change in voltage of pwm signal, and the core technology of non-invention is special
Levy, not describe in detail herein.
Referring to Fig. 8, it is the voltage conversion circuit using the present invention, and the level in response to pulse-modulated signal changes, imitative
The mode chart of the most each node voltage change.
The battery source that this graphic hypothesis system single chip uses is lithium battery, and the supply voltage Vdd that it is provided is
4.2V。
When input signal Vin is high level, its voltage is 4.2V.Reverse input signal Vin1 now is 0V, it is defeated to drive
Enter signal Vdrv_in be 4.2V, control node voltage Vctrl be 0V.On the other hand, the conversion that output node is exported is driven
Voltage Vout is 0V.
When input signal Vin is low level, its voltage is 0V.Reverse input signal Vin1 now is 4.2V, it is defeated to drive
Enter signal Vdrv_in be 0V, control node voltage Vctrl be 4.2V.On the other hand, in the conversion driving output node output
Voltage Vout is 8V.
In other words, the voltage conversion circuit of the present invention, it is only necessary to utilize general low voltage transistor, just can drive output joint
Point produces the conversion voltage Vout between 0V～8.33V (being equivalent to 0V～2*Vdd).
Subsidiary one is mentioned that, supply voltage Vdd here is not required to be defined.Assume, when Vdd is 1.8V, can export
3.6V；If Vdd is 4.2V, about export the output voltage of 8.4V；Or, supply voltage Vdd can be other numerical value.
The voltage conversion circuit that the present invention provides mainly provides voltage conversion function by driving stage.Driving stage is internal is wrapped
The second switch M2 that contains, the first switch M1, the 3rd switch M3, its ceiling voltage being subjected to is Vdd.Therefore, the present invention
Really the way being compatible with general low pressure processing procedure is provided.Being event, the present invention can take into account the demand in space and production cost really.
In sum, although the present invention is disclosed above with all embodiment, and so it is not limited to the present invention.This
Bright art has usually intellectual, without departing from the spirit and scope of the present invention, when making various changes
With retouching.Therefore, protection scope of the present invention is when being as the criterion depending on the defined person of scope of the appended claims.
Claims (13)
1. a voltage conversion circuit, comprises:
One drives input node；
One drives output node；
One drives reverser, is electrically connected between this driving input node, a supply voltage and a ground voltage, and its input is used for
Receive a drive input signal, the driving reverse signal that outfan output is reverse with this drive input signal；And,
One first switch, is electrically connected to this driving output node and this supply voltage, and controls node by one and be electrically connected to
This driving reverser, this first switch is to determine conducting state, when this driving reverse signal is according to this driving reverse signal
During low level, this first switch conduction also exports this ground voltage in this driving output node；And, when this driving reverse signal
During for high level, this first switch presents off state and produces a conversion voltage in this driving output node,
Wherein this first switch is nmos pass transistor, and its grid electrical ties is electrically connected to this control joint in this supply voltage, source electrode
Point, drain electrode are electrically connected to this driving output node.
Voltage conversion circuit the most according to claim 1, wherein this conversion voltage is the twice of this supply voltage.
Voltage conversion circuit the most according to claim 1, wherein this driving reverser comprises:
One second switch, is electrically connected to this driving input node, this supply voltage and this first switch, and it is in this driving input letter
Number for turning on during low level, and then this supply voltage is provided to give this control node；And,
One the 3rd switch, is electrically connected to this driving input node, this ground voltage and this first switch, and it is in this driving input letter
Number for turning on during high level, and then this ground voltage is provided to give this control node.
Voltage conversion circuit the most according to claim 3, wherein this second switch is PMOS transistor, and grid is electrically connected to
This driving input node, source electrode are electrically connected to this supply voltage, drain electrode is electrically connected to this control node.
Voltage conversion circuit the most according to claim 3, wherein the 3rd switch is nmos pass transistor, and grid is electrically connected to
This driving input node, source electrode are electrically connected to this ground voltage, drain electrode is electrically connected to this control node.
Voltage conversion circuit the most according to claim 1, the most also comprises a buffer stage, comprises:
One first buffering reverser, input is electrically connected to an input signal, and it is reverse that it exports reverse with this input signal
Input signal；And,
One second buffering reverser, is electrically connected to outfan and this driving input node of this first buffering reverser, and it receives
This reverse input signal, and export this drive input signal in this driving input node.
Voltage conversion circuit the most according to claim 6, wherein this drive input signal be with this input signal in the same direction and
This reverse input signal is reverse.
Voltage conversion circuit the most according to claim 6, wherein this input signal is a pulse-modulated signal, its high level
Equal to this supply voltage, and its low level is equal to this ground voltage.
Voltage conversion circuit the most according to claim 6, wherein this second buffering reverser comprises:
One the 4th switch, is electrically connected to this first buffering exit point of reverser, this supply voltage and this driving input node,
It turned on when this reverse input signal is low level, and then exported this and supply voltage at this driving input node；And,
One the 5th switch, is electrically connected to this first buffering exit point of reverser, this ground voltage and this driving input node,
It turned on when this reverse input signal is high level, and then exported this ground voltage in this driving input node.
Voltage conversion circuit the most according to claim 9, wherein the 4th switch is PMOS transistor, and its grid is electrically connected
Be connected to this first buffering exit point of reverser, source electrode is electrically connected to this supply voltage, drain electrode is electrically connected to this driving input
Node；And, the 5th switch is nmos pass transistor, and its grid is electrically connected to this first buffering exit point of reverser, source
Pole is electrically connected to this ground voltage, drain electrode is electrically connected to this driving input node.
11. voltage conversion circuits according to claim 1, it is electrically connected to an output stage, and this output stage comprises:
One inductance, the first end is electrically connected to this supply voltage, and the second end is electrically connected to this driving output node；
One diode, input is electrically connected to this driving output node；And,
One electric capacity, is electrically connected between outfan and this ground voltage of this diode.
12. voltage conversion circuits according to claim 11, wherein this voltage conversion circuit is integrated with a system single
In sheet, this output stage is to be external in this system single chip.
13. voltage conversion circuits according to claim 11, wherein this electric capacity is when this drive input signal is low level
Charging, and discharge when this drive input signal is high level.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310045504.0A CN103973103B (en) | 2013-02-05 | 2013-02-05 | Voltage conversion circuit |
| TW102105362A TWI493855B (en) | 2013-02-05 | 2013-02-08 | Voltage converter |
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|---|---|---|---|
| CN201310045504.0A CN103973103B (en) | 2013-02-05 | 2013-02-05 | Voltage conversion circuit |
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| CN103973103B true CN103973103B (en) | 2016-12-28 |
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| CN106125814B (en) * | 2016-08-17 | 2017-11-17 | 珠海格力节能环保制冷技术研究中心有限公司 | Signaling conversion circuit, control circuit and DC brushless motor |
| CN109417606B (en) | 2017-08-17 | 2021-10-26 | 深圳市汇顶科技股份有限公司 | Level converter capable of outputting positive and negative voltages |
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|---|---|---|---|---|
| CN101789680A (en) * | 2010-03-12 | 2010-07-28 | 西安科技大学 | Drive circuit capable of quickly switching off depletion type switching element |
| TW201134069A (en) * | 2010-03-31 | 2011-10-01 | Green Solution Tech Co Ltd | De-glitch switching power supply circuit and controller for controlling the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201433066A (en) | 2014-08-16 |
| CN103973103A (en) | 2014-08-06 |
| TWI493855B (en) | 2015-07-21 |
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