201125244 六、發明說明： 【發明所屬之技術領域】 本發明係涉及-種半導體元件之承載基座，特 -種用來承載半導體元件，並且傳輸半導體元件與一主^ 間錢的承載基座及其❹的電性連接結構與其製 【先前技術】 在半導體it件的生魏財，半㈣元件 結果是用來判斷品質及良率的重要依據。目前半導體·= 的測試系統通常是搭載一測試板，以用來承載半導體元件# 而進行測試。而在測試時，為了能夠讓半導體元件愈測試 =方便地進行電性連結與·脫離，目前的設計便是在測 试板上搭載-承縣座，㈣承絲絲承載半導體元件。 請參考第一圖，為習知技術半導體元件之承載基座的 立體不意圖。如第-圖所示，承載基座8在應用上是設置 於測口式電路板7 ’並且包含一凹設有一凹槽8〇1的載板 8〇及複數個頂針8卜其中，在載板8〇的凹槽8〇1部分是 ，步依據-半導體元件9的一封裝規格來鑽設有複數個· 二穿孔’以相以—對―方式來插設該些頂針81。於是， 二載板80承載對應之封裝規格的半導體元件9時，便能夠 ，由頂針81來傳輸測試電路板7及半導體元件9之間的信 號而如第一圖所示，载板80是例如用來承载一球栅陣列 封裝規格(Ball⑽a卿，BGA)的半導體元件9。 . 此外’凊同時參考第一 A圖，為第一圖A部分的剖視 放大圖▲其是針對载板80與其t之一頂針81在結構部分 的J視心樣。第—A圖可以清楚看出，在載板8〇上所鑽設 4/17 201125244 的貫穿孔是直接插設頂針81，以謓 態樣。而也就因此，由於頂針81’ 81是形成單芯線的 設計，使得載板80中相鄰的^並無任何接地或屏蔽 曾益法且h ή 之間所形成的傳輸介 τ、、，謂的特性阻抗(Ch_“c Lnped纖)），谷易在進行阻抗匹配時 生改變，造成信號在傳輸時發生反射 ；= 個信號的品質。 延叩〜曰玉 【發明内容】 ^紐此，本㈣解解決的技術_在於，在承載 改良設:過的電性連接結構來進行半導體 :hi鱼—反f間的#號傳輸’讓用來傳輸信號的各個 ==瞻持固定阻抗，使信號在傳輸時不會有 5虎反射的問7¾¾。 _本發明所提出之—方案，提供—種電性連接結 構=設於-載板上所鑽設的—貫穿孔，該載板是設置在 捲4t路板’並且用來承载—半導體元件，而電性連接結 雷5 I—金屬層頂針及—絕緣層。其中，金屬層是 ，鑛=穿孔的内壁，頂針収設置於貫穿孔中，而絕緣 曰則疋設於頂針的外緣及金屬層之間，用來固定頂針，讓 ，針的兩端_凸出於她並且㈣電性接 件 及主電路板。 根據本發明所提出之另-方案，提供-種半導 體元件 ’是應用於—主電路板’而承載基座包括：一 數麵述方錢電性連接結構。其中，載板是依 —元件的—封裝規袼來鑽設複數個貫穿孔，並將該 二電性連接結構分別設於每一貫穿孔。 5/17 201125244 之再一方案’提供一種半導體元件 根據本發明所提出 的製造方法’其步驟包括：首先，提供一載板， 盡，據+導體元件的—封裝規絲鑽設複數個貫穿孔於 麵層㈣些貫穿孔的_，進而填 、隹一 I，貝穿孔’並且乾燥硬化以形成一絕緣層。最後， 在?—貫穿孔的絕緣層中鑽設—頂針穿孔，並插設 谓針於每一頂針穿孔。 藉此201125244 VI. Description of the Invention: [Technical Field] The present invention relates to a carrier base of a semiconductor component, which is used to carry a semiconductor component, and to transmit a semiconductor component and a host carrier Its electrical connection structure and its system [Prior Art] In the semiconductor piece of the production of Wei Cai, half (four) component results are used to judge the quality and yield of the important basis. At present, the test system of the semiconductor·= is usually equipped with a test board for carrying the semiconductor component # for testing. In the test, in order to make the semiconductor component more test = convenient electrical connection and disconnection, the current design is to carry the - Chengxian seat on the test board, and (4) the load bearing the semiconductor component. Referring to the first figure, it is a perspective view of a carrier base of a conventional semiconductor device. As shown in the first figure, the carrier base 8 is disposed on the mouth-measuring circuit board 7' and includes a carrier plate 8 recessed with a recess 8〇1 and a plurality of ejector pins 8 therein. The portion of the groove 8〇 of the plate 8〇 is such that the plurality of holes are drilled in accordance with a package specification of the semiconductor element 9 to interpose the pins 81 in a phase-to-pair manner. Therefore, when the second carrier 80 carries the semiconductor component 9 of the corresponding package specification, the signal between the test board 7 and the semiconductor component 9 can be transmitted by the ejector pin 81. As shown in the first figure, the carrier 80 is, for example. A semiconductor component 9 for carrying a ball grid array package specification (Ball (10) a, BGA). Further, while referring to the first A diagram, it is a cross-sectional enlarged view of the portion A of the first diagram ▲ which is a J-shaped view of the structural portion of the carrier 80 and one of the ejector pins 81 of the t. It can be clearly seen from Fig. A that the through hole of 4/17 201125244 drilled on the carrier plate 8 is directly inserted into the ejector pin 81 in a 謓-like manner. Therefore, since the ejector pins 81' 81 are designed to form a single core wire, the adjacent ones of the carrier plates 80 do not have any grounding or shielding, and the transmission medium τ, , and the characteristics formed between h ή Impedance (Ch_“c Lnped fiber)), Gu Yi changes when impedance matching occurs, causing the signal to reflect when transmitting; = the quality of the signal. Yan Yan ~ Yu Yu [invention content] ^ New Zealand, this (four) solution The solution to the problem lies in the fact that the semiconductor is connected to the improved electrical connection structure to carry out the semiconductor: hi fish - anti-f between ## transmission' allows each signal used to transmit signals == maintain a fixed impedance, so that the signal is transmitted There will be no 5 tiger reflections. The solution proposed by the present invention provides an electrical connection structure = a through hole provided on the carrier plate, and the carrier plate is disposed on the volume 4t. The circuit board 'is used to carry the semiconductor component, and is electrically connected to the lightning junction 5 I - the metal layer thimble and the insulating layer. The metal layer is the inner wall of the mine = perforation, and the thimble is disposed in the through hole, and the insulation is insulated. The crucible is disposed between the outer edge of the thimble and the metal layer. To fix the thimble so that both ends of the needle _ protrude from her and (4) electrical connectors and the main circuit board. According to another proposal of the present invention, a semiconductor element 'is applied to the main circuit board' The carrying base comprises: a plurality of face-to-face electrical connection structures, wherein the carrier plate is drilled with a plurality of through holes according to the component-package gauge, and the two electrical connection structures are respectively disposed in each A perforation. 5/17 201125244 A further solution 'providing a semiconductor device according to the present invention's manufacturing method' includes the steps of: firstly, providing a carrier plate, according to the + conductor element - package gauge wire drilling a through hole in the surface layer (four) of the through holes _, and then fill, 隹 I, shell piercing 'and dry hardened to form an insulating layer. Finally, drilled in the insulating layer of the through hole - thimble perforation, and Insert the needle into each of the thimbles.
本發明所能達到的功效在於，當本發明之承章 二用於—主電路板時，主電路板及承載基座所承載# -π件之間的所相互傳輸的信號能夠具有較高的^ 、，進而§翻於職環麟，能翻試結果更為精確， 亚且減少使用者測試時所需考量的變數。 以上之概述與接下來的詳細說明及附圖，皆是為了能 進7步說明本發明為達成預定目的所採取之方式、手段及 ^效。而有關本發明的其他目的及優點，將在後續的說明 及圖式中加以闡述。 【實施方式】The effect that can be achieved by the present invention is that when the second invention of the present invention is used for the main circuit board, the signals transmitted between the main circuit board and the carrier base carrying the #-π components can have a higher signal. ^,, and then § turn over the job, can turn the test results more accurately, and reduce the variables that users need to consider when testing. The above summary, the following detailed description and the accompanying drawings are intended to illustrate the manner, means, and advantages of the present invention in order to achieve the intended purpose. Other objects and advantages of the present invention will be described in the following description and drawings. [Embodiment]
由於信號傳輸路徑實際上是會等效成一個電阻，其阻 值大小為電壓與電流的比值(V/I)，而此一等效電阻即稱之 為傳輸路彳㈣特性阻抗。簡單來說，在絲長的傳輸路徑 上各處的電壓與電流的比值即是絲為傳輸路徑的特性阻 抗。本發明即是針對半㈣元件之承縣座，將其中用來 傳輸半導體TL件與一主電路板之間信號的傳輸路徑設計能 夠維持在-固植抗，使得錢在傳輸雜具有較 質。 請同時參考第二圖 第二Α圖及第三Α、Β圖，為本 6/17 201125244 發明半導體元件之承載基座的實施例立體示意圖、該立體 示意圖的B部分放大圖及該承載基座所使用之電性連接結 構的實施例剖視示意圖及俯視示意圖。本實施例所提供的 一承載基座1是應用於一主電路板2,並且用來承載一半導 體元件3。在目前較常見的應用上，主電路板2是搭配在一 測s式系統(圖未示），以形成測試板’並且再透過承載基座1 來承載半導體元件3’以用來進行測試系統所執行的一測試 耘序。當然，主電路板2上實際是包含有許多電路的佈線， 但由於並非為本發明所欲強調的範圍，因此在第二圖中並 無加以繪製’在此先予以說明。 承載基座1包括：一載板10、複數個電性連接結構u 及一屏蔽蓋體12。其中，載板1〇是依據半導體元件3的一 封裝規格來鑽設複數個貫穿孔(圖中未加以標號），並且為了 穩固地置放及限制半導體元件3的位置，载板1〇更可進一 V成型有一凹槽1〇〇’而讓該些貫穿孔是座落在凹槽1〇〇的 底°卩。有關凹槽100的成型方式，可例如是直接在載板10 製，時便凹設呈現出凹槽1〇〇之態樣，但若載板1〇本身並 不谷易進行凹设的話，則也可例如是本實施例所示的，進 —步在載板10有鑽設貫穿孔的表面上黏設一墊圈結構 t以同樣可以形成凹槽⑽之態樣。而墊圈結構10a的 材質只要是屬於非導電性的材質即可，實際並無加以限制。 電性連接結構11是分別設於載板 10上的每一貫穿 =假設本實施例所描述的半導體聽3是採用球拇陣列 、=褒規格(BGA) ’因此根據貫穿孔之位置來設置的所有電性 連接結構11是排列呈現出一陣列態樣。 進—步說明電性連接結構n之架構，如第二八圖及第 7/17 201125244 二A、B圖所示，每—電性連接結構u是包括一金屬層 m、一頂針112及一絕緣層113。其中，金屬層lu是電 鍍於貫穿孔的内壁’而基於導電性及成本的考量，一般是 採用銅材質來進行電錢，並且此一電錢程序也稱之為链通 孔(Plated Through Hole，Pth)程序。 頂針112纽置於已電鑛完成的貫穿孔的中央，實 用^專輸信號。在應用上，頂針112兩端針腳之設計可依 據實際需求而採用_針、圓錐針、三菱針及皇冠針等針 腳設計，在此並無加。齡，頂針m在結構上亦 可採用彈簧針(P〇g〇Pin)的結構設計，以在進行頂觸時得以 具有彈性效果。 絕緣層113是設於頂針112外緣與金屬層⑴之間，用 來固定頂針112,讓頂針112的兩端是凸出於载板1〇的上、 下表面，並且絲分別紐翻半導體元件3及主電路板 2。其t ’本實施例中，、絕緣層113所使用的材質是例如為 樹脂，當然實際料上亦可其他觀緣龍來進行充 填。 除此之外’載板1G的任—表面上更可進—步凸設有多 個導電接點。而本實施觸第三A _ 了用來說明上述電 性連接結構11的架構之外，更可進一步用來說明在載板ι〇 的下表面設計了-第-共用接點1(Π、—第二共用接點1〇2 及-屏蔽接地點103 ’而在載板1G的上表面設計至少一接 觸點104。當然，第-共用接點刚、第二共用接點ι〇2、 屏蔽接地點1G3及接觸點顺除了可以是凸設的導電接點 之和亦可例如是採用導電探針的設計方式來凸出，以方 便進打電性接觸’並且該些導電接點(導電探針)實際所設置 201125244 在載板ίο表面的位置也沒有加以限制。此外，假設載板l〇 是如本實施例所舉例的，設計有墊圈結構1〇a之態樣時， 則接觸點104是會進一步貫穿墊圈結構1〇a，以更凸出於墊 圈結構10a的表面而方便進行電性接觸。Since the signal transmission path is actually equivalent to a resistor, its resistance is the ratio of voltage to current (V/I), and this equivalent resistance is called the transmission path (4) characteristic impedance. In simple terms, the ratio of voltage to current across the length of the wire is the characteristic impedance of the wire. The present invention is directed to a county seat of a half (four) component, and a transmission path design for transmitting a signal between a semiconductor TL component and a main circuit board can maintain the anchoring resistance, so that the money is relatively good in transmission. Please refer to the second diagram, the third diagram, and the third diagram, which are the perspective view of the embodiment of the semiconductor substrate of the invention of 6/17 201125244, the enlarged view of part B of the perspective view, and the carrier base. A schematic cross-sectional view and a top plan view of an embodiment of an electrical connection structure used. A carrier base 1 provided in this embodiment is applied to a main circuit board 2 and is used to carry half of the conductor elements 3. In the more common applications, the main circuit board 2 is matched with a s-type system (not shown) to form a test board' and then carries the semiconductor component 3' through the carrier base 1 for testing the system. A test sequence performed. Of course, the main circuit board 2 is actually a wiring including a large number of circuits, but since it is not a range to be emphasized by the present invention, it is not drawn in the second drawing, which will be described first. The carrier base 1 includes a carrier 10, a plurality of electrical connection structures u, and a shielding cover 12. The carrier board 1 is formed by drilling a plurality of through holes (not labeled) according to a package specification of the semiconductor component 3, and in order to stably place and limit the position of the semiconductor component 3, the carrier board 1 can be further The further V is formed with a recess 1' and the through holes are seated at the bottom of the recess 1〇〇. The manner in which the groove 100 is formed may be, for example, directly formed on the carrier 10, and the recessed surface may be recessed, but if the carrier 1 itself is not easily recessed, then For example, as shown in this embodiment, a gasket structure t is adhered to the surface of the carrier 10 having the through holes for drilling so as to form the groove (10). The material of the gasket structure 10a is not limited as long as it is a non-conductive material. The electrical connection structure 11 is provided on each of the carrier boards 10 respectively. It is assumed that the semiconductor device 3 described in this embodiment adopts a ball thumb array, a 褒-size (BGA) 'and thus is set according to the position of the through-holes. All of the electrical connection structures 11 are arranged to exhibit an array pattern. Further, the structure of the electrical connection structure n is as shown in FIG. 28 and 7/17 201125244. FIGS. A and B show that each of the electrical connection structures u includes a metal layer m, a thimble 112 and a Insulation layer 113. Wherein, the metal layer lu is electroplated on the inner wall of the through hole, and based on conductivity and cost considerations, the copper material is generally used for the electricity money, and the electric money program is also called a through hole (Plated Through Hole). Pth) program. The thimble 112 is placed in the center of the through hole that has been completed by the electric mine, and the dedicated signal is used. In application, the design of the stitches at both ends of the ejector pin 112 can be designed according to the actual needs, such as _needle, tapered needle, Mitsubishi needle and crown pin, and is not added here. Age, the thimble m can also be structurally designed with a spring pin (P〇g〇Pin) to provide an elastic effect when making a top touch. The insulating layer 113 is disposed between the outer edge of the ejector pin 112 and the metal layer (1) for fixing the thimble 112, so that both ends of the ejector pin 112 protrude from the upper and lower surfaces of the carrier plate 1 and the wires are respectively turned over. 3 and the main circuit board 2. In the present embodiment, the material used for the insulating layer 113 is, for example, a resin, and of course, other materials may be used for filling. In addition to this, the surface of the carrier 1G is more slidably provided with a plurality of conductive contacts. In addition to the structure of the above-mentioned electrical connection structure 11, the present embodiment is further used to illustrate that the first-common contact 1 is designed on the lower surface of the carrier board (Π, - The second common contact 1〇2 and the shield grounding point 103' are designed with at least one contact point 104 on the upper surface of the carrier 1G. Of course, the first shared contact, the second shared contact ι2, and the shielded connection The location 1G3 and the contact point may be the sum of the conductive contacts that may be convex, or may be convex, for example, by using a conductive probe design to facilitate the electrical contact and the conductive contacts (conductive probes). Actually, the position of the surface of the carrier plate ίο is not limited. In addition, if the carrier plate is as exemplified in the embodiment, when the gasket structure 1〇a is designed, the contact point 104 is Further through the gasket structure 1a, the electrical contact is facilitated to protrude more from the surface of the gasket structure 10a.
於疋在貫際使用上，當載板設置在主電路板2所 規劃的一基座設置區域20時，各個電性連接結構丨丨是對 應電性接觸於基座設置區域20中的複數個信號接點2〇〇 ; 第一共用接點101是對應電性接觸於基座設置區域20中的 數位L唬參考接地點201;第二共用接點1〇2是對應電性 接觸於基座設置區域2G巾的—類比信號參考接地點搬； 以及屏蔽接地點103{對應電性接觸絲座設置區域2〇中 的一電源接地點203。 值侍一提的是，在設計上 ----- 一 干等媸兀仟的腳位 功能不同，财根據貫穿孔之位絲設置的電性連接結構 11更可進-步依财導體元件3的—魏祕㈣別賴 數位錢_或—類比錢_。當然，若半導體元 =3在魏上僅單純設計概位信號腳位或類比信號腳位 的=則將所有電性連接結構U視為同-信號類別即可。 士牛例來看，假設本實施例所承載的半導體元件3是同 :二::數位信號腳位及類比信號腳位時，該些歸類為數 連連接結構11的金屬層111便是共同電性 性.拿心、用接點101 ’以再透過第一共用接點101來電 板2的數位信號參考接地點201;而該些歸類 別之電性連接結構11的金屬層111則是共同 •性細、苐，、用接點102,以透過第二共用接點102來. ^連接主電路板2的類比信號參考接地點搬。 201125244 徑得以透讓而電具T接，所形成的傳輸路 步依據數位信號類別及類比、且抗’並且又可進― 抗。讓信齡透㈣蝴來分卿·定的阻 配能夠維持固定，而不崎 號的傳輸率。a有域反射的問題，有效提升信 補=兄明的是’第三八圖中所繪製的一個 構11疋假設對應電性接觸於半導體元件3的數位作t 位，因此被歸類為數位仲㈣认a 雜位 11中齡η” 於是，該電性連接結構 谢。仏屬層lu便是電性連接於載板10的第一共用接點 接觸t下t屏蔽蓋體12是用來罩設於載板1G，並且電性 =板1G之上表面所設計的接觸點刚。此—設計是當 ^載基座1實際應用於主電路板2來進行職半導體元件田3 日守’能夠進-步避免雜訊及電磁波干擾，甚 ，等作用。而接觸點HH在設計上可以是直接電性g 屏敝接地點贈’以藉由屏蔽接地點1〇3及其電性接觸的主 電路板2的電源接地點2〇3來將屏蔽蓋體12所接收到 訊、電磁波、靜電等信號導出。 亦 但若為了進一步避免突發的大電流產生，導致主電路 板2受到損毀，本實施例之載板1〇更可以進一步設計連接 被動7G件105(如：1 Μ歐姆以上的電阻），讓電阻是串聯 連接在接觸點104及屏蔽接地點1〇3之間，以達到緩衝的 作用。而所屬技術領域具有通常知識者是可以輕易了解， 採用其他種類的被動元件105來設計時的電路連接態樣， 任何可以達到避免突發電流影響電路的設計，都是屬於本 10/17 201125244 實施例所述的構想。此外，載板10中更可設置一容置空間 (圖未示）’以用來置放被動元件105，避免被動元件1〇5直 接顯露於载板10之外。 最後，本實施例之載板1〇在材質上，可例如採用印刷 電路板、工程塑膠等材質來進行設計。但為了方便進行鍍 通孔以及進行電路佈較計’載板10較佳是制印刷電路 板的設計。此外，所屬技術領域具有通常知識者可以了解， 印刷電路板在材質的選用上又可分為不同等級的印刷電路 板，在此並非用來限制本發明。 附帶一提的是，由於實際在設計上，載板10上所鑽設 的貫穿孔的直徑並不會太大。因此，在考量到印刷電路板 鍵通孔時的縱(貫穿孔長度)/橫(貫穿孔直徑)比的限制，假設 實際承載基座1的需求高度造成單—载板1G的貫穿孔長= 過長’容易導致錢通孔不完全，如此的話，在設計上^ 進-步是透過多片較薄的載板1G來堆疊形成所f承載 1的高度。 另外，請再參考第四圖，為本發明之半導體元件 載基座的應用實施例俯視示意圖。本實施例與第_。— 施例的主要差異點在於’載板10’上所鑽設的貫穿孔 方式。本實施例是例如用來承載方形扁平無^腳封 Fiat Non-Leaded Package ’ QFN)或方形扁平弓丨、 驗ackage ’ QFP)的半導體元件3，因此在载: 動底^是依據QFN或QFP半導體元件3的封❸^』 δ又-圈貝穿孔，讓根據貫穿孔之位置來設置 :’ 接結構11是排列呈現出一外圍矩形的態樣。 “ 為了更清楚了解本發明承載基座！的實際製造過程， 11/17 201125244 請基於第二圖實施例的架構來繼續參考第五圖，為本發明 半導體兀件之承載基座的製造方法實施例流程圖。如第五 圖所不，本實施例是提供一種半導體元件3之承載基座1 的製造方法，其步驟包括：首先，提供一載板1〇⑻〇1)， 並且依據半導體元件3的一封裝規格來鑽設複數個貫穿孔 於載板10上(S503)。其中，若載板1〇是成型有一凹槽1〇〇 的話，則貫穿孔是座落在凹槽1〇〇的底部。 ，接著’電鍍一金屬層111於每一貫穿孔的内壁⑻⑼， 進而再進行填膠來填滿於每一貫穿孔，並且在乾燥硬化後 形成-絕緣層叫咖）。如此一來，便可在每一貫穿孔的 絕緣層113進-步鑽設一頂針穿孔(S5〇9)。最後，再插設一 頂針112於每-頂針穿孔(8511)，並讓頂針112的兩端是稍 微凸出載板10的表面’以方便在使㈣分別電性接觸半導 肢元件3及主電路板2。藉由上述的製造過程，便得以势成 承載基座i的本體架構。當然，若為了避免在實際使用時 的X到雜訊干擾的話’承載基座j在製造上更可進一+罩 設-題蓋體於載板1G的上表面(S513)，以做為屏ς。 綜上所述，纟純號的傳輸路徑的特性賊是影 號品質的最重要的因素。因此透過本發明承載基座二二 計’讓相鄰的各個電性連接結構之間的阻抗能保持—致^ 2所承載之半導體元件與測試系統上的主電路板之間所 傳輸的信號能夠具有較佳的品f。進而當 環境時，能讓測試結果更為精碟，並且;=::: 所需考量的變數。 惟，以上所述’僅為本發明的具體實_之詳細說 及圖式而已，並非用以限制本發明，本發明之所有範圍應 12/17 201125244 =下述之申料利朗為準’任何熟赫項技 =_直可輪及之__可^在以下^ 累所界疋之專利範圍。 【圖式簡單說明】 圖；第-圖係習知技術半導體元件之承載基座的立體示意 第一Α圖係第—圖的a部分剖視放大圖； 示咅^二_本發料導體元件之承縣絲實施例立體 第二A圖係第二圖的B部分放大圖； 第二A圖係本發明之承載基座所使用之電性連接结構 的實施例剖視示意圖； '° 第二B圖係本發明之承載基座所使用之電性連接结構 的實施例俯視示意圖； >σ 第四圖係本發明之半導體元件之承載基座的應用實施 例俯視示意圖；及 第五圖係本發明半導體元件之承載基座的製造方法實 施例流程圖。 【主要元件符號說明】 [習知技術] 7測試電路板 8承載基座 8〇載板 801凹槽 81頂針 9半導體元件 13/17 201125244 [本發明] 1承載基座 10，10’載板 10a墊圈結構 100凹槽 101第一共用接點 102第二共用接點 103屏蔽接地點 104接觸點 105被動元件 11電性連接結構 111金屬層 112頂針 113絕緣層 12屏蔽蓋體 2主電路板 20基座設置區域 200信號接點 201數位信號參考接地點 202類比信號參考接地點 203電源接地點 3半導體元件 S501至S513流程圖步驟說明 14/17In the continuous use, when the carrier is disposed in a pedestal setting area 20 planned by the main circuit board 2, each of the electrical connection structures 对应 is electrically connected to the plurality of pedestal setting areas 20 The first common contact 101 is correspondingly electrically connected to the digital L唬 reference ground point 201 in the pedestal setting area 20; the second common contact 1 〇2 is corresponding to the electrical contact with the pedestal The set-up area 2G towel-analog signal reference grounding point is moved; and the shield grounding point 103{corresponds to a power source grounding point 203 of the electrical contact wire holder setting area 2〇. The value of the service is that, in the design ----- a different function of the foot position, the financial connection structure 11 according to the position of the through-hole is more advanced. - Wei secret (four) do not rely on digital money _ or - analogy money _. Of course, if the semiconductor element =3 is simply designed to be the analog signal pin or the analog signal pin = then all the electrical connection structures U can be regarded as the same-signal class. In the case of the case, it is assumed that the semiconductor element 3 carried by the embodiment is the same as the two:: digital signal pin and the analog signal pin, and the metal layers 111 classified as the number connection structure 11 are common. Sexuality. The digital signal is used to refer to the ground point 201 of the incoming call board 2 through the first shared contact 101; and the metal layers 111 of the electrical connection structure 11 of the same type are common. • Fine, 苐, and use contact 102 to pass through the second common contact 102. ^ The analog signal connected to the main circuit board 2 is referenced to the ground point. The 201125244 path is transparent and the electrical tool T is connected. The resulting transmission path is based on the digital signal type and analogy, and is resistant to and resistant to. Let the letter of age (four) butterfly to the division of the fixed resistance can maintain a fixed, but not the transmission rate. a problem with domain reflection, effectively improving the letter-compensation = brother's is that the figure drawn in the third figure is assumed to correspond to the digit of the semiconductor element 3 as the t-bit, and is therefore classified as a digit. Zhong (4) recognizes a stray 11 middle age η". Thus, the electrical connection structure Xie. The lanthanum layer lu is electrically connected to the first common contact of the carrier 10 contact t. The shield cover 12 is used to The cover is disposed on the carrier 1G, and the electrical contact = the contact point designed on the upper surface of the board 1G. This design is when the base 1 is actually applied to the main circuit board 2 for the operation of the semiconductor component field 3 It can further prevent noise and electromagnetic interference, etc., and the contact point HH can be designed as a direct electrical g-screen, grounding point, 'to shield the grounding point 1〇3 and its electrical contact. The power supply grounding point 2〇3 of the main circuit board 2 is used to derive signals, electromagnetic waves, static electricity, etc. received by the shielding cover 12. However, if the main circuit board 2 is damaged in order to further avoid sudden large currents, The carrier board 1 of this embodiment can be further designed to connect the passive 7G unit 105 (eg: 1) Μ ohms or more), the resistor is connected in series between the contact point 104 and the shield grounding point 1 〇 3 to achieve the buffering effect, and those skilled in the art can easily understand that other types of passive use The circuit connection pattern of the component 105 is designed, and any design that can avoid the influence of the burst current is a concept described in the embodiment of this 10/17 201125244. In addition, the carrier 10 can be provided with a housing. Space (not shown) is used to place the passive component 105 to prevent the passive component 1〇5 from being directly exposed outside the carrier 10. Finally, the carrier 1 of the embodiment is on the material, for example, a printed circuit can be used. Materials such as plates and engineering plastics are designed. However, in order to facilitate plating through holes and to perform circuit board comparison, the carrier board 10 is preferably a printed circuit board design. Further, those skilled in the art can understand that printing is possible. The circuit board can be divided into different grades of printed circuit boards in terms of material selection, which is not intended to limit the present invention. Incidentally, due to the actual design The diameter of the through hole drilled in the carrier 10 is not too large. Therefore, in consideration of the limitation of the longitudinal (through hole length) / transverse (through hole diameter) ratio of the printed circuit board key through hole, it is assumed The required height of the actual bearing base 1 causes the through hole length of the single carrier plate 1G to be too long to easily lead to incompleteness of the money through hole. In this case, the design is advanced through a plurality of thinner carrier plates 1G. In addition, please refer to the fourth figure, which is a schematic top view of an application embodiment of the semiconductor component carrier pedestal of the present invention. The main difference between this embodiment and the _. The through hole method drilled on the carrier plate 10. This embodiment is, for example, a semiconductor component for carrying a flat flat FAT non-Leaded Package 'QFN' or a square flat bow and an ackage 'QFP'. 3, therefore, in the load: the bottom ^ is based on the sealing of the QFN or QFP semiconductor component 3 δ δ-ring perforation, so that according to the position of the through hole: 'The connection structure 11 is arranged to present a peripheral rectangle Aspect. In order to more clearly understand the actual manufacturing process of the present invention, 11/17 201125244, please continue to refer to the fifth figure based on the architecture of the second embodiment, which is a method for manufacturing the carrier base of the semiconductor device of the present invention. The flow chart is as shown in the fifth figure. The present embodiment provides a method for manufacturing the carrier base 1 of the semiconductor component 3, the steps of which include: firstly, providing a carrier 1 (8) 〇 1), and according to the semiconductor component A package specification of 3 is used to drill a plurality of through holes on the carrier plate 10 (S503). If the carrier plate 1 is formed with a groove 1〇〇, the through hole is seated in the groove 1〇〇. At the bottom of the hole, a metal layer 111 is electroplated on the inner wall (8) (9) of each through hole, and then filled to fill each through hole, and after drying and hardening, an insulating layer is formed. A thimble perforation (S5〇9) may be drilled in the insulating layer 113 of each through hole. Finally, a thimble 112 is inserted into each perforation (8511), and the ends of the ejector 112 are slightly convex. The surface of the loading plate 10 is convenient for The semiconductor component 3 and the main circuit board 2 are respectively electrically contacted. By the above manufacturing process, the body structure of the susceptor i is formed. Of course, if X interference to noise is avoided in actual use, 'The carrier base j can be further manufactured into a cover-cover cover body on the upper surface of the carrier plate 1G (S513) as a screen. In summary, the characteristic thief of the transmission path of the 纟 pure number is The most important factor in the quality of the image. Therefore, through the carrier of the present invention, the two-way meter 'allows the impedance between the adjacent electrical connection structures to be maintained—the semiconductor components carried by the device and the master on the test system The signal transmitted between the boards can have a better product f. In the environment, the test results can be made more refined, and ==::: the variables to be considered. The detailed description of the present invention and the drawings are not intended to limit the present invention, and all the scope of the present invention should be 12/17 201125244 = the following claims are subject to the 'Large Skills _ straight The round of the __ can ^ in the following ^ tired of the boundaries of the patent range. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a carrier base of a conventional semiconductor device. The first drawing is a cross-sectional enlarged view of a portion of the first embodiment of the present invention; The second embodiment of the present invention is a cross-sectional view of the second embodiment of the second embodiment. The second embodiment is a schematic cross-sectional view of the embodiment of the electrical connection structure used in the carrier base of the present invention; A top view of an embodiment of an electrical connection structure used in a carrier base of the present invention; > σ is a top view of an application embodiment of a carrier base of a semiconductor device of the present invention; and a fifth diagram is a semiconductor of the present invention. Flow chart of the method for manufacturing the carrier base of the component. [Description of main component symbols] [Technical technique] 7 test circuit board 8 carrying base 8 〇 carrier 801 groove 81 ejector pin 9 semiconductor component 13/17 201125244 [This Invention] 1 carrier base 10, 10' carrier plate 10a washer structure 100 groove 101 first common contact 102 second common contact 103 shield ground point 104 contact point 105 passive component 11 electrical connection structure 111 metal layer 112 thimble 113 insulation layer 12 201 digital signal reference ground point 2 of the main circuit board 20 is provided a base 200 contacts the drain region of the cover signal analog signal 202 with reference to the power supply ground point a ground point 203 of the semiconductor element 3 a flowchart of steps S501 to S513 described 14/17