201125101 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種晶片封裝結構，尤係一種設置導流凸塊的晶 片封裝結構。 【先前技術】BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip package structure, and more particularly to a wafer package structure in which a flow guiding bump is provided. [Prior Art]
目前現有的多層晶片封裝（multi_chip package assembie, MCP Assemble)，於封裝注模時，由於上層晶片距離封膠體越來越小，且 為了防止切割後基板損傷晶片多以田字型排列。由於最上層晶片與 模具間隙(mold clearance)有縮小趨勢，因此注膠時容易造成模流不平 均’因此而容易產生膠體表面空洞。 一此外，隨著封裝結構之日趨複雜，晶片之金線線弧過大 ，以致 於模流通過時，容易造成打線塌落。 ^合上述，翻化的複雜龍結構，在進行注膠時，容易產生 並谷易造成打線塌落，進而使封裝製程良率下降，進 月|J亟需努力的目標。 备提高製造成本。因此’如何避免膠體產生表面空洞及避免打 線土羽洛，進而提高封裝製程良率是目 【發明内容】 塊，使目供"'種晶料裝結構，其鋪由設置導流凸 尼使封裝材料通過導流凸塊時， 句之層流效果並減少総之產生11凸塊賴以達成較均 晶片之打線郷，相高封裝表面㈣之產生及避免 依據本發明之一實施例，— 複數個晶片、複數個導流凸塊、—封結構’包含一基板、 T教材料。基板具有一注模區域， 201125101 其中注模區域的一側為一澆注側、一排氣側相對應設置於注模區域 的另一側、以及一模流方向由洗注側朝排氣側前進。晶片設置於基 板之注模區域上並形成複數條通道。導流凸塊分別設置於注模區域 的澆注側與通道之交點。封裝材料包覆晶片、基板之注模區域與導 流凸塊。 本發明上述及其他態樣、特性及優勢可由附圖及實施例之說明 而可更加了解。 【實施方式】 請參照圖1為一示意圖顯示依據本發明一實施例之晶片封裝 結構，其包括一基板1、複數個晶片2、複數個導流凸塊3及一封裝 材料(未顯示）。 如圖1所示，基板1具有一注模區域U，注模區域u之其中 的一側為一澆注側11a，一排氣側lib相對應設置於注模區域丨丨的 另一側’模流方向(箭頭方向)由澆注側11a朝排氣側llb前進。此外， 基板1可具有一定位點12，其可設置於洗注側ua或排氣側llb(如 圖1所示）’以便界定澆注側11a及排氣侧llb。 多個晶片2設置於基板1之注模區域η上並形成複數條通道 21。晶片2較佳以田字型陣列設置。 導流凸塊3a分別設置於注模區域η的澆注侧ila與通道21 之交點，以引導封裝材料的流動。 請繼續參照圖1，在此較佳實施例中，亦有複數個導流凸塊3b 設置於注模區域11除澆注側11a及排氣側llb外之兩側與通道21 之交點，以達更佳的導流效果。 導流凸塊3a，3b之形狀並未限制，但較佳為圓柱狀，以達較佳 的導流效果及方便設置之功能。 201125101 請參照圖2為一示意圖顯示依據本發明一實施例之晶片封妒 結構之製備難。其巾，在填人-封裝㈣(未_)時，可二堯注彻) l〜la導入，當封裝材料通過導流凸塊3時，可順著導流凸塊3流動(如 箭頭方向）以達成較均勻的層流(laminar flow)效果，並減少紊流 (:urbulentfl〇w)之產生’進而減少表面空洞之產生。封裝物質可填^ 晶片2、導流凸塊3a，3b及注模區域η。At present, the multi-chip package ASSEMBIE (MCP Assemble) is used in the case of package injection molding, because the upper layer wafer is smaller and smaller than the sealing body, and in order to prevent damage to the substrate after cutting, the wafer is arranged in a field type. Since the uppermost wafer and the mold clearance have a tendency to shrink, it is easy to cause mold flow unevenness when the glue is injected, so that a colloidal surface void is easily generated. In addition, as the package structure becomes more and more complicated, the gold line arc of the wafer is too large, so that when the mold flow passes, it is easy to cause the line to collapse. ^In combination with the above, the complex dragon structure that is turned over is prone to be produced when the glue is injected, and the valley is liable to cause the line to collapse, which in turn causes the package process yield to decrease, and the goal of the work is to be achieved. Increase manufacturing costs. Therefore, 'how to avoid the surface voids of the colloid and avoid the line-up of the soil, so as to improve the yield of the package process. [Inventive content] The block is made for the structure of the crystal material, and the paving is provided by the guide flow. When the encapsulating material passes through the guiding bump, the laminar flow effect of the sentence is reduced and the 11 bumps are generated to achieve a more uniform wafer 郷, the high encapsulation surface (4) is generated and avoided according to an embodiment of the present invention, The plurality of wafers, the plurality of flow guiding bumps, and the sealing structure comprise a substrate and a T-material. The substrate has an injection molding area, 201125101, wherein one side of the injection molding area is a casting side, one exhaust side is correspondingly disposed on the other side of the injection molding area, and a mold flow direction is advanced from the washing side to the exhaust side. . The wafer is disposed on the injection molding area of the substrate and forms a plurality of channels. The flow guiding bumps are respectively disposed at the intersection of the casting side and the channel of the injection molding area. The encapsulating material covers the wafer, the injection molding area of the substrate, and the flow guiding bumps. The above and other aspects, features and advantages of the present invention will become more apparent from the description of the appended claims. [Embodiment] Referring to FIG. 1 , a schematic diagram of a chip package structure according to an embodiment of the present invention includes a substrate 1 , a plurality of wafers 2 , a plurality of flow guiding bumps 3 , and a package material (not shown). As shown in FIG. 1, the substrate 1 has an injection molding area U. One side of the injection molding area u is a casting side 11a, and one exhaust side lib is correspondingly disposed on the other side of the injection molding area. The flow direction (arrow direction) advances from the casting side 11a toward the exhaust side 11b. Further, the substrate 1 may have an locating point 12 which may be disposed on the wash side ua or the exhaust side llb (as shown in Fig. 1) to define the pouring side 11a and the exhaust side 11b. A plurality of wafers 2 are disposed on the injection molding region η of the substrate 1 and form a plurality of channels 21. The wafer 2 is preferably arranged in a field-shaped array. The flow guiding projections 3a are respectively disposed at intersections of the casting side ila of the injection molding area n and the passage 21 to guide the flow of the sealing material. With reference to FIG. 1 , in the preferred embodiment, a plurality of flow guiding protrusions 3 b are disposed at the intersection of the two sides of the injection molding area 11 except the pouring side 11 a and the exhaust side 11 b and the channel 21 . Better drainage. The shape of the flow guiding projections 3a, 3b is not limited, but is preferably cylindrical to provide a better flow guiding effect and a convenient setting function. 201125101 Please refer to FIG. 2, which is a schematic view showing the difficulty in preparing a wafer package structure according to an embodiment of the present invention. The towel can be inserted in the filling-packaging (four) (not _). l~la is introduced, and when the encapsulating material passes through the guiding protrusion 3, it can flow along the guiding protrusion 3 (such as the direction of the arrow) In order to achieve a more uniform laminar flow effect and reduce the generation of turbulence (: urbulentfl〇w), thereby reducing the occurrence of surface voids. The encapsulating material can fill the wafer 2, the flow guiding bumps 3a, 3b, and the injection molding region η.
*此外，在晶片2之打線線弧(未顯示)過大的情形時，本發明可 於模流通過時，使模流順著導流凸塊3流動，以避免封裝材料直接 衝擊線弧，進而避免晶片2之打線塌落。 綜合上述，本發明藉由設置導流凸塊，使封裝材料通過導流凸 塊時可順著U凸駿細達紐均自的層流效果並減少奮流之 而減》表面空洞之產生及避免晶片之打線塌^，因此可以 尚封裝Μ鋥良垄。 、上所述之·讎疋為說明本發明之技術思想及特點，其目 =使熟，項技藝之人士能夠瞭解本發明之内容並據以實施，當 之專利範圍’即大凡依本發賴揭示之精神所 作之均#化或修飾，仍應涵蓋在本發明之專利範圍内。 201125101 【圖式簡單說明】 圖1為一示意圖顯示依據本發明一實施例之晶片封裝結構。 圖2為一示意圖顯示依據本發明一實施例之晶片封裝結構之製備過 程。 【主要元件符號說明】 1 基板 11 注模區域 11a 澆注側 lib 排氣側 12 定位點 2 晶片 21 通道 3a, 3b 導流凸塊 [S1 6* In addition, when the wire arc (not shown) of the wafer 2 is excessively large, the present invention can flow the mold flow along the flow guiding bump 3 when the mold flow passes, thereby preventing the packaging material from directly striking the arc, thereby avoiding The wire of the wafer 2 collapses. In summary, the present invention reduces the occurrence of surface voids by providing a flow guiding bump so that the encapsulating material can pass through the flow guiding bumps and can follow the laminar flow effect of the U convex springs and reduce the flow. Avoid the collapse of the wafer, so you can still package the ridge. The above description is for explaining the technical idea and characteristics of the present invention, and the purpose of the invention is to enable the person skilled in the art to understand the contents of the present invention and implement it according to the scope of the patent. It is to be understood that the spirit of the disclosure is intended to be within the scope of the invention. 201125101 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a chip package structure according to an embodiment of the present invention. 2 is a schematic view showing the preparation process of a chip package structure in accordance with an embodiment of the present invention. [Main component symbol description] 1 Substrate 11 Injection molding area 11a Casting side lib Exhaust side 12 Positioning point 2 Wafer 21 Channel 3a, 3b Diversion bump [S1 6