TW201839927A - Chip stacked structure - Google Patents

Abstract

A chip stacked structure includes a circuit board, a first chip, a second chip, and a pair of supporters. The first chip is located on the circuit board. The second chip is located on the first chip, and the second chip has two opposite ends protruding from the first chip. The pair of the supports each are located between the circuit board and one of the two opposite ends of the second chip protruding from the first chip, and each of the supporter is separated from the first chip to define a tunnel, wherein the tunnel extends in the first direction, and an inner diameter of the tunnel decreases gradually in a direction from a first opening to a second opening.

Description

Wafer stack structure

This invention relates to a semiconductor structure, and more particularly to a wafer stack structure.

In recent years, as the size of packages has become smaller and smaller, the application of multi-wafer stacked semiconductor package structures has also grown rapidly. One of the package on package (PoP) structures is to arrange the wafers in a cross-stack manner. A support member is disposed on the circuit substrate and between the circuit substrate and the wafer farther away from the circuit substrate, and the support member and the wafer closer to the circuit substrate are spaced apart from each other to form a channel having the same inner diameter therebetween.

In the injection molding package, since the flow rate of the encapsulating material in the channel is slower than that outside the channel, a serious air trap effect is easily caused, thereby causing a void in the package in the channel. Therefore, how to avoid the void generated by the returning phenomenon to improve the process yield is one of the issues that R & D personnel need to solve now.

The present invention provides a wafer stack structure having good process yield.

An embodiment of the present invention provides a wafer stack structure including a circuit substrate, a first wafer, a second wafer, and a pair of supports. The first wafer is on the circuit substrate. The second wafer is on the first wafer and the second wafer has opposite ends that protrude from the first wafer. A pair of support members are each located between the one of the opposite ends of the second wafer projecting from the first wafer and the circuit substrate, and each support member is spaced apart from the first wafer to define a channel, wherein the channel is in the first side The upwardly extending and inner diameter of the passage gradually decreases from the first opening toward the second opening.

The above described features and advantages of the invention will be apparent from the following description.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

1 is a perspective view of a wafer stack structure in accordance with an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line I-I' of Figure 1. 3 is a cross-sectional view of a package structure in accordance with an embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 simultaneously, the wafer stack structure 100 includes a circuit substrate 102, a first wafer 118, a pair of support members 122, and a second wafer 128. The circuit substrate 102 includes a plurality of connection pads 104 and a circuit layer 110 under the connection pads 104. The connection pads 104 are exposed to the first surface 102a of the circuit substrate 102 and are electrically connected to the circuit layer 110. The circuit layer 110 includes a patterned dielectric layer 106 having a plurality of contact openings 106a and a conductive layer 108 filled in the contact openings 106a, and the conductive layers 108 are disposed apart from each other with respect to the first surface 102a of the circuit substrate 102. On the second surface 102b. The material of the conductive layer 108 is, for example, copper (Cu), aluminum (Al), or a combination thereof. The method of forming the conductive layer 108 is, for example, electroplating or other thin film deposition method. The material of the patterned dielectric layer 106 is, for example, a high molecular polymer, and the high molecular polymer is, for example, an epoxy resin, a polyimide, or a combination thereof. The method of forming the patterned dielectric layer 106 is, for example, a chemical vapor deposition method.

In some embodiments, a solder resist layer 112 exposing a portion of the wiring layer 110 may also be formed on the second surface 102b of the wiring substrate 102. Here, a portion of the wiring layer 110 exposed by the solder resist layer 112 may be defined as a ball pad. Next, a ball mount is performed on the circuit layer 110 (ie, the ball pad) to form at least one solder ball 114 on the circuit layer 110. The material of the solder ball 114 is, for example, tin (Sn), gold (Au), silver (Ag), copper (Cu), or a combination thereof.

The first wafer 118 includes a plurality of first pads 120 and is located on the first surface 102a of the circuit substrate 102. In some embodiments, the first wafer 118 has two first edges S1 extending along the first direction D1 and two second edges S2 extending along the second direction D2, wherein the first direction D1 is different from the second direction D2 (For example, the first direction D1 is perpendicular to the second direction D2), and the first pad 120 is disposed along the second edge S2 and electrically connected to the corresponding connection pad 104. In some embodiments, the first wafer 118 may be rectangular, with the two first edges S1 extending along the first direction D1 being the long sides; and the second second edges S2 extending along the second direction D2 being short. Edge (as shown in Figure 1), but the invention is not limited thereto. In some embodiments, the first pad 120 is electrically connected to the corresponding connection pad 104 by wire bonding, for example, the first bonding wire 132 is connected to the corresponding first pad 120 and the corresponding connection pad. 104. The material of the first bonding wire 132 is, for example, Sn, Au, Ag, Cu, or a combination thereof. In some embodiments, the back side of the first wafer 118 faces the circuit substrate 102. In this case, in order to enhance the adhesion between the first wafer 118 and the circuit substrate 102, the first wafer 118 and the circuit substrate may be selectively selected. The first adhesive layer 116 is disposed between the pads 102 such that the first wafer 118 can be stably fixed to the circuit substrate 102. The first adhesive layer 116 is, for example, a die attach film (DAF), but the invention is not limited thereto. The back surface of the first wafer 118 is a surface opposite to the active surface of the first wafer 118.

The second wafer 128 is located on the first wafer 118 and the second wafer 128 has opposite ends of the first wafer 118. The second wafer 128 includes a plurality of second pads 130. In some embodiments, the second wafer 128 has two third edges S3 extending along the first direction D1 and two fourth edges S4 extending along the second direction D2, wherein the first direction D1 is different from the second direction D2 (For example, the first direction D1 is perpendicular to the second direction D2), and the second pad 130 is disposed along the third edge S3 and electrically connected to the corresponding connection pad 104. In an embodiment, the second wafer 128 has overhangs at opposite ends of the first wafer 118 (ie, the third edge S3) in the second direction D2, and the second wafer 128 does not cover the first wafer 118. The first pad 120. In some embodiments, the second wafer 118 may be rectangular, the two third edges S3 extending along the first direction D1 being short sides; and the second fourth edges S4 extending along the second direction D2 are long But the invention is not limited thereto. As shown in FIG. 1, in the present embodiment, the first wafer 118 and the second wafer 128 may be rectangular, which are in a cross-stack manner (ie, the long side of the first wafer 118 extends in the first direction D1, and the second The long sides of the wafer 128 extend along the second direction D2 are sequentially stacked on the circuit substrate 102, wherein the second wafer 128 has a plurality of protrusions in the second direction D2 at opposite ends of the first wafer 118 (ie, the third edge S3) However, the invention is not limited thereto. In some embodiments, the second pad 130 is electrically connected to the corresponding connection pad 104 by wire bonding, for example, the second bonding pad 134 is connected to the corresponding second pad 130 and the corresponding connection pad. 104. The material of the second bonding wire 134 is, for example, Sn, Au, Ag, Cu, or a combination thereof. In some embodiments, the back side of the second wafer 128 faces the circuit substrate 102, in which case, in order to enhance the adhesion between the second wafer 128 and the first wafer 118, the second wafer 128 and the second wafer are selectively A second adhesive layer 126 is disposed between the wafers 118 such that the second wafer 128 can be stably fixed to the first wafer 118. The second adhesive layer 126 is, for example, a die attach film (DAF), but the invention is not limited thereto. The back surface of the second wafer 128 is a surface opposite to the active surface of the second wafer 128.

The support members 122 are each located between the second wafer 128 protruding from opposite ends of the first wafer 118 (ie, the third edge S3) and the circuit substrate 102. In an embodiment, the support member 122 is supported under the second pad 130. Therefore, when the second wafer 128 is electrically connected to the circuit substrate 102 by wire bonding, the support member 122 can reduce the wire bonder. The moment generated by the porcelain nozzle pressing down on the second pad 130 (the position of the fulcrum changes causes the arm to become small), so that the second wafer 128 is less likely to be damaged or bent. In some embodiments, in order to improve the adhesion between the support member 122 and the circuit substrate 102, or the adhesion between the support member 122 and the second wafer 128, the support member 122 and the circuit substrate 102 may be selectively selected. A first adhesive layer 116 is disposed therebetween, or a second adhesive layer 126 is disposed between the support member 122 and the second wafer 128. In other embodiments, the first adhesive layer 116 between the support member 122 and the circuit substrate 102 and the first adhesive layer 116 between the first wafer 118 and the circuit substrate 102 may also be separated from each other or by different Process formation. In some embodiments, the material of the support 122 can be an insulating material such as yttria, photoresist, or a combination thereof.

Each support member 122 is spaced apart from the first wafer 118 to define a channel 124, wherein the channel 124 extends in a first direction D1 and the inner diameter of the channel 124 is from the first opening A toward the second opening B (ie, fluid The flow direction F) gradually becomes smaller. As such, when a fluid (eg, a mold flow) flows from the first opening A into the passage 124, its flow rate is from the first opening A of the passage 124 (the opening into which the fluid flows) toward the second opening B (the opening through which the fluid flows out). The direction is gradually increased, so that in the subsequent molding process, the flow rate of the encapsulating material in the second opening B is greater than or equal to the flow rate outside the channel 124, so the encapsulating material is first filled in the channel 124, and the encapsulating material outside the channel 124 is avoided. The second opening B of the channel 124 flows back into the channel 124 to cause a serious back-packing phenomenon, causing a void in the channel 124 that is not filled with the encapsulating material, thereby solving the back-packing phenomenon caused by the same inner diameter of the channel. In some embodiments, the inner diameter ratio (B/A) of the first opening A and the second opening B of the passage 124 is 0.5 to 0.9.

Referring to FIG. 3, the encapsulation layer 136 is disposed on the circuit substrate 102 and covers the first wafer 118, the second wafer 128, the support member 122, the first bonding wire 132, and the second bonding wire 134, and fills the channel 124 to form a package. Structure 138. In the case where the inner diameter of the channel 124 gradually decreases from the first opening A toward the second opening B, the flow rate of the encapsulating material in the second opening B is greater than or equal to the flow velocity outside the channel 124, so the packaging material is filled first. Full of channels 124, the encapsulation material outside of the channels 124 is prevented from flowing back into the channels 124 from the second opening B of the channels 124, resulting in severe backfilling. In this way, the encapsulation layer 136 can fill the channel 124 without creating voids therein, so that the package structure 138 has a good process yield. The material of the encapsulation layer 136 is, for example, an epoxy or other suitable dielectric material. The method of forming the encapsulation layer 136 is, for example, filling the encapsulation material in the channel 124 by a molding process and coating the first wafer 118, the second wafer 128, the support member 122, the first bonding wire 132, and the second bonding wire 134. To form the encapsulation layer 136.

4 is a cross-sectional view of a package structure in accordance with another embodiment of the present invention. The wafer stack structure 200 of FIG. 4 is substantially the same as the wafer stack structure 100 of FIG. 3, except that the first wafer 218 is electrically connected to the circuit substrate 102 by flip chip bonding. Therefore, in the present embodiment, the same or similar elements as those of the previous embodiment are given the same or similar reference numerals, and the connection relationships, materials, and processes of the remaining members have been described in detail in the foregoing, and therefore will not be described again in the following. .

The wafer stack structure 200 includes a circuit substrate 102, a first wafer 218, a second wafer 128, and a pair of supports 122. The first wafer 218 is electrically connected to the circuit substrate 102, for example, by flip chip bonding. For example, the active surface of the first wafer 218 faces the circuit substrate 102. Therefore, the first pad 120 can be electrically connected to the corresponding connection pad 104 by connecting the conductive bumps 234 formed on the connection pad 104. And in the subsequent molding process, an underfill process is performed such that the encapsulation layer 136 is located between the first wafer 218 and the circuit substrate 102 to protect the exposed portion of the conductive bumps 234. In some embodiments, since the first wafer 218 is electrically connected to the circuit substrate 102 in a flip chip bonding manner, it is not necessary to additionally provide a die bonding material between the first wafer 218 and the circuit substrate 102. A wafer 218 is stably fixed to the wiring substrate 102.

In addition, in some embodiments, the second wafer 128 may be electrically connected to the circuit substrate 102 by wire bonding, for example, the second bonding wire 134 is connected to the corresponding second bonding pad 130 and the corresponding connection pad. 104. In some embodiments, the back side of the second wafer 128 faces the circuit substrate 102. In this case, in order to enhance the adhesion between the second wafer 128 and the first wafer 218, the second wafer 128 and the second wafer are selectively A second adhesive layer 126 is disposed between the wafers 218 such that the second wafer 128 can be stably fixed to the first wafer 218. The second adhesive layer 126 is, for example, a die attach film, but the invention is not limited thereto.

In summary, the wafer stack structure described in the above embodiment is designed such that the inner diameter of the channel gradually decreases from the first opening toward the second opening, so that the packaging material is in the second opening (ie, the packaging material flows out from the channel). The flow rate of the opening is greater than or equal to the flow rate of the encapsulating material outside the channel. Therefore, the encapsulating material is first filled in the channel to prevent the encapsulating material outside the channel from flowing back into the channel from the second opening of the channel, thereby solving the channel The back-packaging phenomenon caused by the same inner diameter makes the wafer stack structure have good process yield.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200‧‧‧ wafer stack structure

102‧‧‧Line substrate

102a‧‧‧ first surface

102b‧‧‧second surface

104‧‧‧Connecting mat

106‧‧‧ patterned dielectric layer

106a‧‧‧Contact opening

108‧‧‧ Conductive layer

110‧‧‧Line layer

112‧‧‧ solder mask

114‧‧‧ solder balls

116‧‧‧First adhesive layer

118, 218‧‧‧ first chip

120‧‧‧First pad

122‧‧‧Support

124‧‧‧ channel

126‧‧‧second adhesive layer

128‧‧‧second chip

130‧‧‧Second pad

132‧‧‧First wire bond

134‧‧‧second welding line

136‧‧‧Encapsulation layer

138‧‧‧Package structure

234‧‧‧Electrical bumps

D1‧‧‧ first direction

D2‧‧‧ second direction

F‧‧‧Flow direction

A‧‧‧first opening

B‧‧‧second opening

S1‧‧‧ first edge

S2‧‧‧ second edge

S3‧‧‧ third edge

S4‧‧‧ fourth edge

1 is a perspective view of a wafer stack structure in accordance with an embodiment of the present invention. Figure 2 is a cross-sectional view taken along line I-I' of Figure 1. 3 is a cross-sectional view of a package structure in accordance with an embodiment of the present invention. 4 is a cross-sectional view of a package structure in accordance with another embodiment of the present invention.

Claims (10)

A wafer stack structure comprising: a circuit substrate; a first wafer on the circuit substrate; a second wafer on the first wafer, the second wafer having protrusions on opposite ends of the first wafer And a pair of support members each located between the one of the opposite ends of the second wafer protruding from the first wafer and the circuit substrate, and each of the support members and the first The wafers are spaced apart to define a channel, wherein the channels extend in the first direction and an inner diameter of the channels gradually decreases from a first opening toward a second opening. The wafer stack structure of claim 1, wherein an inner diameter ratio of the first opening to the second opening is 0.5 to 0.9. The wafer stack structure of claim 1, further comprising an encapsulation layer on the circuit substrate and covering the first wafer, the second wafer, and the support member, and filling the aisle. The wafer stack structure of claim 1, wherein the first wafer is electrically connected to the circuit substrate by wire bonding. The wafer stack structure of claim 4, further comprising a first adhesive layer between the circuit substrate and the first wafer. The wafer stack structure of claim 4, wherein the second wafer is electrically connected to the circuit substrate by wire bonding. The wafer stack structure of claim 6, further comprising a second adhesive layer between the first wafer and the second wafer. The wafer stack structure of claim 1, wherein the first wafer is electrically connected to the circuit substrate by flip chip bonding. The wafer stack structure of claim 8, wherein the second wafer is electrically connected to the circuit substrate by wire bonding. The wafer stack structure of claim 9, further comprising a second adhesive layer between the first wafer and the second wafer.