TW201125084A - Flip chip package and method of manufacturing the same - Google Patents

Flip chip package and method of manufacturing the same Download PDF

Info

Publication number
TW201125084A
TW201125084A TW099135909A TW99135909A TW201125084A TW 201125084 A TW201125084 A TW 201125084A TW 099135909 A TW099135909 A TW 099135909A TW 99135909 A TW99135909 A TW 99135909A TW 201125084 A TW201125084 A TW 201125084A
Authority
TW
Taiwan
Prior art keywords
substrate
electronic device
resin layer
flip chip
chip package
Prior art date
Application number
TW099135909A
Other languages
Chinese (zh)
Other versions
TWI482248B (en
Inventor
Ey-Yong Kim
Young-Hwan Shin
Soon-Jin Cho
Jong-Yong Kim
Jin-Seok Lee
Original Assignee
Samsung Electro Mech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of TW201125084A publication Critical patent/TW201125084A/en
Application granted granted Critical
Publication of TWI482248B publication Critical patent/TWI482248B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

There is provided a flip chip package including an electronic device, a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is mounted, and a connection pad disposed outside the mounting region, a resin layer formed on the board and including a trench formed by removing a part of the resin layer, and a dam member provided on the trench and preventing the leakage of an underfill between the mounting region and the connection pad. Since the dam member, formed on the processed resin layer, can prevent the leakage of the underfill, a package defect rate can be lowered, and connection reliability can be improved.

Description

201125084 六、發明說明： - [本案相關參考] — 本申請案主張韓國申請案No. 10-2009-0103000之優 先權，其於2009年10月28日於韓國智慧財產局提出申 請，其揭露内容於此處併入參考。 【發明所屬之技術領域】 本發明係關於一種覆晶封裝件及其製造方法，特別 是，關於一種具有較低封裝缺陷率之覆晶封裝件及藉由防 止底層充填材料的 漏以達成更可靠的連接。 【先前技術】 由於近來電子裝置更薄更小具具有t高性㈣發展， 對於裝配電子震置至基板上之高密度裝配技術的需求增 加。晶片級（chip-scale)封裴技術因此已展露頭角。 當電子裝置裝配至印刷電路板上時，印刷電路板及電 子裝置間之間隙係以底層充填材料（仙如出⑴填充，以加 強印刷電路板及電子裝置之間的連接。以此方式，可確保 :、間之可罪連接。然而’冑將_定量之底層充填材料（利用 液體樹月曰)注入到基板及電子裝置的間隙中時，會發生不想 要地洩漏至周圍區域。 〜 至於根據相關技術的封裝，半導體晶片係裝配於印刷 電路板的中心部位以及與外部裝置電性連接之連接塾係緊 密地安排於半導體晶片的周圍。此外，底層充填材料係注 ^至半導體晶片及印刷電路板之__。此底層充填材 料係利用液體樹脂，而會有某些量之底層充填材料不想要 £ 95033 3 201125084 地洩漏至外面。 然而，由於根據當前趨勢發展電子裝置及電路圖案係 緊密地裝配於基板上，該底層充填材料在洩漏後，也許會 跑到相鄰之連接墊或電路圖案處。如此便會污染相鄰之連 接墊或電路圖案’造成產品的缺陷。 【發明内容】 本發明之主要目的，係在於提供一種具有較低封裝缺 陷率以及藉由使用形成於處理過樹脂層上的屏障元件（dam member)來防止底層充填材料的洩漏，以確保更可靠地連接 之覆晶封裝件’以及在於提供一種其製造之方法。 根據本發明之目的’提供一種覆晶封裝件，包括：電 子裝置；基板，包括設置於該基板之裝配區域内之導電焊 墊而該基板之裝配區域上係裝配有該電子裝置，及設置於 該裝配區域外之連接墊；樹脂層，係形成於該基板上及包 括藉由移除一部份該樹脂層形成溝槽；以及屏障元件，係 k供於該溝槽上及防止該裝配區域及該連接墊間之底層充 填材料的茂漏。 該溝槽係可藉由使用雷射加工該樹脂層形成。 該溝槽係可藉由曝光及顯影該樹脂層形成。 該樹脂層可形成光阻樹脂。 該樹脂層可進-步包括溝槽周圍之表面的不規則部 分。 該屏障元件係可沿者該裝配區域之周圍形成。 該覆晶封I件可進-步包括形成於該連接墊上且與 95033 4 201125084 該電子裝置電性連接之凸塊。 '該覆晶封裝件可進―步包括介於該電子裝置及該基 板之間的該底層充填材料。 根據本發明另-目的’係提供覆晶封料，包括電子 裝置，基板，包括設置於該基板之裝配區域内之導電焊墊 而該基板之裝配區域上係裝配有該電子裝置，及設置於該 裝配區域外之連接墊；樹脂層，係形成於該基板上及包括 於該樹脂層表面之一部分的不規則部分；以及屏障元件， 係提供於該不規則部分上及防止該裝配區域及該連接墊間 之底層充填材料的洩漏。 該不規則部分可藉由在該樹脂層上完成鑄造步驟形 成。 該不規則部分可藉由曝光及顯影該樹脂層形成。 該樹脂層可形成光阻樹脂。 該屏障元件係可沿者該裝配區域之周圍形成。 該覆晶封裝件可進一步包括形成於該連接墊上且與 該電子裝置電性連接之凸塊。 該覆晶封裴件可進一步包括介於該電子裝置及該基 板之間的該底層充填材料。 根據本發明之另一目的，係提供一種製造覆晶封裝件 之方法，該方法包括：提供一基板，包括設置於該基板之 裝配區域内之導電焊墊而該電子裝置係將裝配於該基板之 裝配區域上’及設置於該裝配區域外之連接墊；於該基板 上形成樹脂層；藉由移除一部份該樹脂層形成溝槽；於該 5 5 95033 201125084 溝槽上形祕障元件’該屏障元件防止該裝配區域及該連 接墊間之底層充填㈣料漏；以及於該裝犯區域上裝配 該電子裝置。 該溝槽之形成係藉由使用雷射加工該樹脂層。 該溝槽之形成係藉由完成曝光及顯影該樹脂層形成。 該樹脂層係形成光阻樹脂。 不規則部分可進-步於該溝槽周圍之該樹脂層的表 面形成。 該屏障元件可沿者該裝配區域之周圍形成。 該方法更包括形成於該連接墊上之凸塊，該凸塊係與 該電子裝置電性連接。 该方法更包括於該電子裝置及該基板之間注入該底 層充填材料。 根據本發明之另一目的，係提供—種製造覆晶封襞件 之方法，該方法包括：提供一基板，包括設置於該基板之 裝配區域内之導電焊墊，其中，該電子裝置係將裝配於該 基板之裝配區域上，及設置於該裝配區域外之連接墊；於 該基板上形成樹脂層，於該樹脂層表面之一部分形成不規 則部分；於該不規則部分上形成屏障元件，該屏障元件防 止該裝配區域及該連接墊間之底層充填材料的洩漏；以及 於該裝配區域上裝配該電子裝置。 該不規則部分之形成係藉由於該樹脂層上完成鑄造 步驟形成。 該不規則部分之形成係藉由曝光及顯影該樹脂層完成。 95033 6 201125084 該樹脂層係形成光阻樹脂。 該屏障元件係沿者該裝配區域之周圍形成。 該方法更包含於該連接墊上形成凸塊，該凸塊係與該 電子裝置電性連接。 該方法更包含於該電子裝置及該基板之間注入該底 層充填材料。 【實施方式】 本發明之具體實施例現將參考圖示以詳細細節描述。 然而，上述實施例係用以例示性說明本發明之原理及 其功效，而非用於限制本發明。任何熟習此項技藝之人士 均可在不違背本發明之精神及範疇下，對上述實施例進行 修改。圖示中的參考編號標示為類似元件。 根據本發明之具體實施例，覆晶封裝件現將參照第1 和第2圖詳細描述。 第1圖係為根據本發明具體實施例覆晶封裝件之上視 圖的示意圖。第2圖係為第1圖沿者A-A’線之剖視圖。 如第1圖和第2圖所示，根據本發明具體實施例之覆 晶封裝件1，其包括：電子裝置16 ;基板12，其上有導電 焊墊22形成於裝配區域之且該電子裝置16係裝配於該裝 配區域中，而連接墊14則係形成於該裝配區域之外；形成 於基板12上及具有溝槽T之樹脂層R係藉由移除一部份樹 脂層R所形成；以及屏障元件18,其係提供於該連接墊14 與裝配有該電子裝置16的該裝配區域之間；該屏障元件 18防止底層充填材料的洩漏；以及凸塊28，係形成於該連201125084 VI. Description of the invention: - [Related reference in this case] — This application claims the priority of Korean Application No. 10-2009-0103000, which was filed on October 28, 2009 at the Korea Intellectual Property Office. Reference is incorporated herein by reference. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a flip chip package and a method of fabricating the same, and more particularly to a flip chip package having a lower package defect rate and by preventing leakage of the underfill material for more reliable Connection. [Prior Art] Due to the recent development of thinner and smaller electronic devices having a higher t (fourth), there is an increasing demand for high-density assembly technology in which electronic components are mounted on a substrate. Chip-scale sealing technology has thus emerged. When the electronic device is mounted on the printed circuit board, the gap between the printed circuit board and the electronic device is filled with the underlying filling material (Italian (1) to strengthen the connection between the printed circuit board and the electronic device. In this way, Make sure that: the guilty connection between the two. However, when the underfill material (using the liquid tree moon) is injected into the gap between the substrate and the electronic device, unwanted leakage to the surrounding area occurs. In a related art package, a semiconductor wafer is mounted on a central portion of a printed circuit board and a connection structure electrically connected to an external device is closely arranged around the semiconductor wafer. Further, the underlying filling material is injected into the semiconductor wafer and the printed circuit. __. This underfill material utilizes liquid resin, and there will be some amount of underfill material that does not want to leak out to the outside. However, due to current trends, electronic devices and circuit patterns are closely related. Mounted on the substrate, the underfill material may run to the adjacent connection pad or circuit after the leak In this case, the adjacent connection pads or circuit patterns are contaminated to cause defects in the product. SUMMARY OF THE INVENTION The main object of the present invention is to provide a resin having a lower package defect rate and formed by using the resin. a dam member on the layer to prevent leakage of the underlying filling material to ensure a more reliable connection of the flip chip package 'and to provide a method of manufacturing the same. According to the purpose of the present invention, a flip chip package is provided The method includes: an electronic device; a substrate, comprising a conductive pad disposed in an assembly area of the substrate; the mounting area of the substrate is mounted with the electronic device, and a connection pad disposed outside the assembly area; a resin layer Formed on the substrate and including forming a trench by removing a portion of the resin layer; and a barrier member for supplying the trench and preventing leakage of the underfill material between the mounting region and the connection pad The trench can be formed by laser processing the resin layer. The trench can be formed by exposing and developing the resin layer. Forming a photoresist resin. The resin layer may further include irregular portions of a surface around the trench. The barrier element may be formed around the mounting region. The flip chip I may further comprise a bump on the connection pad and electrically connected to the electronic device of 95033 4 201125084. The flip chip package further includes the underfill material interposed between the electronic device and the substrate. According to the present invention - The purpose of providing a flip-chip sealing material, comprising an electronic device, a substrate, comprising a conductive pad disposed in an assembly area of the substrate, the mounting area of the substrate is equipped with the electronic device, and disposed outside the assembly area a connection pad; a resin layer formed on the substrate and an irregular portion included in a portion of the surface of the resin layer; and a barrier member provided on the irregular portion and preventing the bottom portion between the assembly region and the connection pad Leakage of the filling material. The irregular portion can be formed by completing a casting step on the resin layer. The irregular portion can be formed by exposing and developing the resin layer. The resin layer can form a photoresist resin. The barrier element can be formed around the assembly area. The flip chip package may further include a bump formed on the connection pad and electrically connected to the electronic device. The flip chip package can further include the underfill material between the electronic device and the substrate. According to another aspect of the present invention, a method of fabricating a flip chip package is provided, the method comprising: providing a substrate comprising a conductive pad disposed in an assembly region of the substrate and the electronic device is to be mounted on the substrate And a connection pad disposed outside the assembly area; forming a resin layer on the substrate; forming a trench by removing a portion of the resin layer; forming a trench on the 5 5 95033 201125084 The component 'the barrier element prevents the underlying layer between the assembly area and the connection pad from filling (4) material leakage; and assembling the electronic device on the tamper area. The trench is formed by processing the resin layer by using a laser. The formation of the trench is formed by performing exposure and development of the resin layer. This resin layer forms a photoresist resin. The irregular portion may be formed in the surface of the resin layer around the groove. The barrier element can be formed around the assembly area. The method further includes a bump formed on the connection pad, the bump being electrically connected to the electronic device. The method further includes injecting the underfill material between the electronic device and the substrate. According to another aspect of the present invention, a method of fabricating a flip chip package is provided, the method comprising: providing a substrate comprising a conductive pad disposed in an assembly region of the substrate, wherein the electronic device is Mounting on the mounting area of the substrate, and a connection pad disposed outside the assembly area; forming a resin layer on the substrate, forming an irregular portion on a portion of the surface of the resin layer; forming a barrier element on the irregular portion The barrier element prevents leakage of the underfill material between the assembly area and the connection pad; and assembling the electronic device on the assembly area. The formation of the irregular portion is formed by completing the casting step on the resin layer. The formation of the irregular portion is accomplished by exposing and developing the resin layer. 95033 6 201125084 This resin layer forms a photoresist resin. The barrier element is formed around the assembly area. The method further includes forming a bump on the connection pad, the bump being electrically connected to the electronic device. The method further includes injecting the underfill material between the electronic device and the substrate. [Embodiment] Specific embodiments of the present invention will now be described in detail with reference to the drawings. However, the above-described embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. The reference numbers in the figures are labeled as similar components. In accordance with a specific embodiment of the present invention, a flip chip package will now be described in detail with reference to Figures 1 and 2. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of a top view of a flip chip package in accordance with an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line A-A' of the first figure. As shown in FIG. 1 and FIG. 2, a flip chip package 1 according to an embodiment of the present invention includes: an electronic device 16; a substrate 12 having a conductive pad 22 formed on the mounting region and the electronic device 16 series is assembled in the assembly area, and the connection pad 14 is formed outside the assembly area; the resin layer R formed on the substrate 12 and having the trench T is formed by removing a part of the resin layer R And a barrier element 18 provided between the connection pad 14 and the mounting area equipped with the electronic device 16; the barrier element 18 prevents leakage of the underfill material; and a bump 28 formed in the connection

S 7 95033 201125084 接墊22上以及與該電子裝置16電性連接。 根據此具體實施例，覆晶封裝件1包括裝配於該基板 12上之電子裝置16,達成加強介於電子裝置16及基板12 之連接，其由於底層充填材料20注入至由電子裝置16及 基板12間產生之間隙。 該連接墊14係形成於其上裝配有電子裝置16之該基 板12的裝配區域外部。此裝配區域亦可稱為電子裝置裝配 區域。當該電子裝置16係裝配於該基板12上時，該電子 裝置裝配區域係指被該電子裝置16所覆蓋之該基板12的 區域。該電子裝置16係装配於該電子裝置裝配區域。當該 基板12及該電子裝置16係彼此電性連接時，該間隙係產 生於該基板12及該電子裝置16之間。 該電子裝置16係為一種涵蓋像是半導體晶片或類似 物等的主動元件以及像是電容、電感、電阻以及類似物等 的被動元件之概念。關於此具體實施例，將以半導體晶片 單單作為電子裝置之一個例子來描述。 液體底層充填材料20係注入至該基板12及該電子裝 置16之間，以確保電盤12及該電子裝置16之間的可靠連 接。 由於此底層充填材料20係為液體樹脂，當底層充填 材料20係注入至介於該基板12及該電子裝置16之間的間 隙時，一部份底層充填材料2 0會·;戈漏至周圍部分。 填入該基板12及該電子裝置16間的間隙之底層充填 材料20可利用具有低黏度的環氧樹脂。由於具更高密度之 8 95033 201125084 電子裝置愈來愈小的發展’所以需使用高密度裝配’即使 -是在裝配電子裝置16的封裝技術中。此造成了基板12及 電子裝置16間形成之間隙寬度下降’也因此液體底層充填 材料20可藉由也細現象注入。這是因為當底層充填材料具 低度之黏度時，其促進了底層充填材料的注入。 當底層充填材料20具有低度之黏度時，可容易填入 該基板12及該電子裝置16間所形成的間隙，然而其容易 不想要地洩漏至周圍部分。基於此理由’屏障元件18a係 形成於該電子裝置裝配區域及該連接墊14之間，使得底層 充填材料20具低度的黏度’可防止其流動至該連接墊14。 樹脂層R，設置於該基板12上，係具備藉由移除一部 份樹脂層R所形成的溝槽T。 此處’溝槽T可藉由使用雷射加工該樹脂層形成。或 者，溝槽T可藉由曝光及顯影由光阻樹脂製成的該樹脂層 形成。然而，形成該溝槽的方法並非僅限於所述之方法。 於此例中，屏障元件18a係形成於溝槽了上。此處， 屏障元件I8a係形成該電子裴置裴配區域及該連接墊 之間以防止具低黏度的底層充填材料2〇流動至連接墊14 之上。 此外，根據本發明第4圖所示之另一具體實施例的覆 晶封裝件2，樹脂層R設置於該基板a上，可具有在〆部 份其表面上之不規則部分U。 此處，不規則部分U可藉由在樹脂層R上完成鑄造夕 驟形成。或者，樹脂層R，形成光阻樹脂，可被曝光及顯 9 95033 201125084 影從而形成不規則部分u。然而，形成不規則部分u旅非 僅限於所述之方法。 在此例中’屏障元件18b(見第4圖）係形成於不規則 部分U上。此處，屏障元件18b係形成於該電子裝置裝配 區域及該連接墊14之間以防止具低黏度之底層充填材料 20流動至連接墊14之上。 此外’根據本發明第5圖所示之另一具體實施例的覆 晶封裝件3，樹脂層R設置於該基板12上，可具有在樹脂 層R上一部份表面之不規則部分U及溝槽τ。此處，溝槽T 係藉由移除一部份樹脂層R形成。 在此例中’屏障元件18c(見第5圖），係形成於不規 則部分U及溝槽T上。此處，屏障元件18c係形成於該電 子裝置裝配區域及該連接塾14之間，以防止具低黏度之底 層充填材料20流動至連接墊14之上。 於上述各實施例中’由於屏障元件18(18a至18c)及 樹脂層R之間的接觸面積增加’所以屏障元件18便不容易 藉由外部衝擊而自樹脂層R分開或也不會排列不當。據 此’藉由損害屏障元件18引起的缺陷可被減低，封裝件1 的製造良率可被改善，而導致洩漏底層充填材料20至周圍 部分的缺陷亦可被減小。此外’關於可能由於不完備屏障 元件18而自封裝件1洩漏之揮發性有機物的問題，亦可被 解決。 此處’屏障元件18可藉由使用噴墨印刷方法釋放絕 緣油墨形成。或者’先前形成的屏障元件18可藉由黏合劑 10 95033 201125084 固定至樹脂層R ’或可使用微影方法或網版印刺方法形 成。然而’形成屏障元件18之方法並非僅限於所述方法。 參閱第1圖，屏障元件18係以連續方式沿|電子裝 置裝配區域之周圍形成。然而，屏障元件18的衫狀並非限 於闡述中的描述。例如，屏障元件18可為不規則不連續。 或者，屏障元件18可以預定區間安排的複數個點的形式提 供。 即使當底層充填材料20係使用具有低度的|纟度時， 此屏障元件18可防止底層充填材料2〇茂漏至谭圜部分。 因此’屏障元件18有助於防止發生在封裝件丨内導因於底 層充填材料20之洩漏的缺陷。 在下文T，根據本發明之具體實施例 件的步驟將參照第3A至3F圖詳細描述。 第3A至3F圖係為根據本發明之具體實施例闡釋製造 覆晶封裝件步驟的示意剖視圖。 如第3A至3F圖所示，根據本發明 覆晶封裝件的步驟包括：提供基板12，其+ 7 f 係裝配於裝配區域上，導電塾Μ + 配區義成於基板12上之裝 配&域内，當連接墊14係形成於 19 μ 、 _區域外部時；形成樹 知層R於基板12上，藉由移除—部份樹脂層 形成屏障元件18(18a至陶於溝槽τ上，屏障防 的裝魄域至連_4之麵充填材料 亦Γα Γ 子裝置16於電子裝置叫在下文中 '、：’、'电子裝置裝配區域」）的裝配區域上。S 7 95033 201125084 is electrically connected to the electronic device 16 on the pad 22 . According to this embodiment, the flip chip package 1 includes an electronic device 16 mounted on the substrate 12 to achieve reinforcement between the electronic device 16 and the substrate 12, which is injected into the electronic device 16 and the substrate by the underlying filling material 20. 12 gaps produced. The connection pad 14 is formed outside the assembly area of the substrate 12 on which the electronic device 16 is mounted. This assembly area may also be referred to as an electronic device assembly area. When the electronic device 16 is mounted on the substrate 12, the electronic device mounting area refers to the area of the substrate 12 covered by the electronic device 16. The electronic device 16 is mounted on the electronic device assembly area. When the substrate 12 and the electronic device 16 are electrically connected to each other, the gap is generated between the substrate 12 and the electronic device 16. The electronic device 16 is a concept that covers active components such as semiconductor wafers or the like and passive components such as capacitors, inductors, resistors, and the like. Regarding this specific embodiment, a semiconductor wafer will be described as an example of an electronic device. A liquid underfill material 20 is implanted between the substrate 12 and the electronic device 16 to ensure a reliable connection between the electrical disk 12 and the electronic device 16. Since the underfill material 20 is a liquid resin, when the underfill material 20 is injected into the gap between the substrate 12 and the electronic device 16, a portion of the underfill material 20 will be removed; section. The underfill material 20 filled in the gap between the substrate 12 and the electronic device 16 can utilize an epoxy resin having a low viscosity. Due to the ever-increasing development of electronic devices with higher density, it is necessary to use high-density assembly, even if it is in the packaging technology of assembling electronic device 16. This causes a decrease in the gap width formed between the substrate 12 and the electronic device 16 and thus the liquid underfill material 20 can be implanted by a fine phenomenon. This is because when the underfill material has a low viscosity, it promotes the injection of the underfill material. When the underfill material 20 has a low viscosity, the gap formed between the substrate 12 and the electronic device 16 can be easily filled, however, it is easy to undesirably leak to the surrounding portion. For this reason, the barrier element 18a is formed between the electronic device mounting region and the connection pad 14 such that the underfill material 20 has a low viscosity' to prevent it from flowing to the connection pad 14. The resin layer R is provided on the substrate 12 and has a groove T formed by removing a portion of the resin layer R. Here, the trench T can be formed by processing the resin layer using a laser. Alternatively, the trench T may be formed by exposing and developing the resin layer made of a photoresist resin. However, the method of forming the trench is not limited to the method described. In this example, the barrier element 18a is formed on the trench. Here, the barrier element I8a forms the electronic mounting region and the connection pad to prevent the underfill material 2〇 having a low viscosity from flowing onto the connection pad 14. Further, according to the flip chip package 2 of another embodiment shown in Fig. 4 of the present invention, the resin layer R is provided on the substrate a, and may have an irregular portion U on the surface of the crotch portion. Here, the irregular portion U can be formed by completing the casting on the resin layer R. Alternatively, the resin layer R, which forms a photoresist resin, can be exposed and exposed to form an irregular portion u. However, the formation of the irregular portion u brigade is not limited to the method described. In this case, the barrier element 18b (see Fig. 4) is formed on the irregular portion U. Here, the barrier element 18b is formed between the electronic device mounting region and the connection pad 14 to prevent the underfill material 20 having a low viscosity from flowing onto the connection pad 14. In addition, in the flip chip package 3 according to another embodiment of the present invention, the resin layer R is disposed on the substrate 12 and may have an irregular portion U on a portion of the surface of the resin layer R and Groove τ. Here, the trench T is formed by removing a portion of the resin layer R. In this example, the barrier element 18c (see Fig. 5) is formed on the irregular portion U and the trench T. Here, a barrier element 18c is formed between the assembly area of the electronic device and the port 14 to prevent the underfill material 20 having a low viscosity from flowing onto the connection pad 14. In the above embodiments, 'the contact area between the barrier elements 18 (18a to 18c) and the resin layer R is increased', so the barrier elements 18 are not easily separated from the resin layer R by external impact or are not arranged improperly. . Accordingly, defects caused by damage to the barrier member 18 can be reduced, and the manufacturing yield of the package 1 can be improved, and defects causing leakage of the underlying filling material 20 to the surrounding portion can be reduced. Furthermore, the problem of volatile organic compounds that may leak from the package 1 due to incomplete barrier elements 18 can also be solved. Here, the barrier element 18 can be formed by releasing an insulating ink using an ink jet printing method. Alternatively, the previously formed barrier element 18 may be fixed to the resin layer R' by an adhesive 10 95033 201125084 or may be formed using a lithography method or a screen printing method. However, the method of forming the barrier element 18 is not limited to the method. Referring to Fig. 1, barrier element 18 is formed in a continuous manner along the periphery of the mounting area of the electronic device. However, the shape of the barrier element 18 is not limited to the description in the description. For example, barrier element 18 can be irregularly discontinuous. Alternatively, barrier element 18 may be provided in the form of a plurality of points arranged in a predetermined interval. Even when the underfill material 20 is used with a low degree of enthalpy, the barrier element 18 prevents the underfill material 2 from leaking to the tantalum portion. Thus, the barrier element 18 helps prevent defects that occur in the package turns due to leakage of the underfill material 20. In the following T, the steps of a specific embodiment according to the present invention will be described in detail with reference to Figures 3A to 3F. 3A through 3F are schematic cross-sectional views illustrating the steps of fabricating a flip chip package in accordance with a specific embodiment of the present invention. As shown in FIGS. 3A to 3F, the step of flip chip mounting according to the present invention includes: providing a substrate 12, the + 7 f is mounted on the mounting area, and the conductive 塾Μ + lands are assembled on the substrate 12 & In the domain, when the connection pad 14 is formed outside the 19 μ, _ region; the formation layer R is formed on the substrate 12, and the barrier element 18 is formed by removing the partial resin layer (18a to the trench τ, The barrier-preventing mounting area to the surface of the _4 is also on the assembly area of the electronic device (hereinafter referred to as ',:', 'electronic device mounting area').

S 95033 11 201125084 首先’如第3A圖所示，提供基板12，其包括設置於 電子裝置裝配區域内之導電墊22以及設置於電子裝置穿 配區域外部之連接墊14。之後樹脂層R，曝先導電墊 及連接墊14，係形成於基板12上。 連接墊14係形成於電子裝置16裝配之基板 域外部的基板12上，以及導電墊22係形成於裝配區;^ 此處’導電墊22提供介於電子裝置16及基板12之間的電 性連接。 、冨電子裝置16裝配置於基板12上時，電子裝置裝配 區域係指被電子裝置16覆蓋之基板12的區域。電子裝置 16係裝配於電子裝置裝配區域上。當基板12及電子裝置 16係破此電性連接時，就於基板12及電子裝置Μ之間 生間隙。 、該電子襞置16係為一種涵蓋了像是半導體晶片或類 =物等的主動元件以及像是電容、電感、電阻以及類似物 时被動元件之概念。關於此具體實施例，將以半導體晶 片單單作為電子裝置的一個範例來描述。 其它主動或被動元件可被裝配於連接墊14上。電子 晉 - 、16可經由連接墊14與外部裝置電性連接。連接塾14 /、物可能損害與主動元件、被動元件及外部元件之電 連通性。例如，若介於電子裝置16及基板12之間加強連 之底層充填材料20洩漏及覆蓋連接墊14，電性連接的 可靠度會衰退。 之後’如第3B圖所示’與電子裝置16電性連接之凸 95033 12 201125084 塊28係形成於各自的道带 曰^導電墊22上。網版印刷方法可用以 • 形成放置於電子裝置奘1 置哀配區域上之導電墊22上的凸塊28。 」而&塊28的形成並非限於所述之方法。顯然地凸塊 28可利用該技術領域中具有通常者所習知的各種方法來 开y成電子裝置16及基板12係藉由那些凸塊28彼此電性 連接。 之後’如第3c圖所示，溝槽τ係藉由移除設置於基 板12上一部份的樹脂層r形成。 此處’屢槽T可使用雷射加工樹脂層R形成。或者， 溝槽T可藉由曝光及顯影由光阻樹脂製成的該樹脂層形 成。然而，形成該溝槽τ的方法並非僅限於所述之方法。 之後，如第3D圖所示，屏障元件18a係形成於溝槽τ 上。此處’屏障元件l8a係形成於電子裝置裝配區域及連 接墊14之間以防止具低黏度之底層充填材料20朝向連接 墊14洩漏。 在此實施例中，闡釋的屏障元件18a係形成於所提供 的樹脂層R之溝槽T上。然而，屏障元件18a之形狀並非 限於圖示。 、 根據本發明第4圖所示之另一具體實施例的覆晶封裝 件2，樹脂層R，設置於基板12上，可具有不規則部分υ 於一部份其表面上。 此處’不規則部分U可藉由完成在樹脂層r上的鑄造 步驟（coining Pr〇cess)形成。或者，不規則部分υ可藉由 曝光及顯影形成光阻樹脂之該樹脂層形成。然而，形成不 95033 13 201125084 規則部分u的方法並非限於所述方法。 於此例中’屏障元件18b(見第4圖）係形成於不規則 部分U上。此處，屏障元件係形成於電子裝置裝配區 域及連接墊14之間以防止具低黏度之底層充填材料2〇流 動至連接墊14之上。 此外’根據本發明第5圖所示之另一具體實施例的覆 晶封裝件3，樹脂層R，設置於基板12上，可具有不規則 部分U及溝槽T於樹脂層R之一部份表面上。此處，溝槽 T係藉由移除一部分樹脂層r形成。 在此例中’屏障元件18C(見第5圖）係形成於不規則 部分U及溝槽T上。此處’屏障元件i8c係形成於電子裝 置裝配區域及連接墊14之間以防止具低黏度之底層充填 材料20流動至連接墊14之上。 介於屏障元件18(18a至18c)及樹脂層R之間的接觸 面積增加遍及上述實施例，屏障元件18係不容易藉由外部 衝擊自樹脂層R分開或不會排列不當。據此，藉由損害屏 障元件18引起的缺陷可被減小，封裝件1的製造良率可被 改善’以及導致洩漏底層充填材料2〇至周圍部分的缺陷亦 可被減小。此外，關於揮發性有機物的問題，其可能由於 自不完備屏障元件18的封裝件1洩漏，亦可被解決。 此處’屏障元件18可藉由使用喷墨印刷方法釋放絕 緣油墨形成。或者，先前形成的屏障元件18可藉由黏合劑 固定至樹脂層R ’或可使用微影方法或網版印刷方法形 成。然而’形成屏障元件18之方法並非僅限於所述方法。 14 95033 201125084 參閱第1圖，屏障元件18係以連續方式沿者電子裝 置裝配區域之周圍形成。然而，屏障元件18的形狀並非限 於闡述中的描述。例如，屏障元件18可為不規則不連續。 或者，屏障元件18可以預定區間安排的複數個點的形式提 供。 即使當底層充填材料20係使用具有低度的黏度時， 此屏障元件18可防止底層充填材料20洩漏至周圍部分。 因此，屏障元件18有助於防止發生在封裝件1内導因於底 層充填材料20之洩漏的缺陷。 之後，如第3E圖所示，電子裝置16係裝配置基板12 上之電子裝置裝配區域。當電子裝置16係裝配於基板12 上時，電子裝置裝配區域係為藉由電子裝置16覆蓋基板之 區域。電子裝置16係裝配於電子裝置裝配區域上。當基板 12及電子裝置16係彼此電性連接時，介於基板12及電子 裝置16之間的間隙係建立。 在裝配電子裝置16於基板12上的步驟中，基板12 及電子裝置16間的電性連接係為必須的。因此，裝配電子 裝置16的步驟可包括藉由使用覆晶黏合方法電性連接電 子裝置16及凸塊28的步驟。亦即，根據上述步驟，導電 墊22(相對應於電子裝置16的終端）係形成於電子裝置裝 配區域，以及凸塊28，係形成於各自的導電墊22上。因 此，凸塊28及電子裝置16之終端係藉由使用覆晶黏合方 法彼此電性連接。覆晶黏合步驟係藉由添加回流用之助炼 劑（flux)至凸塊28，透過回流加熱來熔融凸塊28完成凸 s 15 95033 201125084 塊28與電子裝置16之電性連接。，添至基板12之回流用 助熔劑，隨後藉由沖洗步驟移除。 之後，如第3F圖所示，底層充填材料20係注入至電 子裝置16及基板12之間。如上所述，間隙係建立於電性 連接電子裝置16與凸塊28之步驟中的基板12及電子裝置 16之間。此間隙可能帶來關於在電子裝置16及基板12之 間連接可靠度的問題。 分配器30之噴嘴係放置於屏障元件18及電子裝置16 外侧之間，藉以注入液體底層充填材料20。隨後，注入的 底層充填材料20於電子裝置16底下流動。在此步驟中， 液體底層充填材料20可能洩漏至周圍部分。然而，屏障元 件18，係形成於電子裝置區域及連接墊14之間，其阻擋 了底層充填材料20洩漏至連接墊14。藉由此方式，連接 墊14得到保護不受洩漏的底層充填材料20影響。 底層充填材料20填入由基板12及電子裝置16之間 所產生的間隙，而其可由具有低黏度的環氧樹脂所形成。 即使裝配電子裝置16的封裝技術亦需要根據目前朝向薄 型化、具有高密度小型電子裝置的趨勢進行高密度裝配。 基於此原因，基板12及電子裝置16之間的間隙具有一縮 減的寬度。因此，當注入液體底層充填材料20時，可藉由 毛細現象填入間隙。當底層充填材料20具有低黏度時可更 容易地施作。 然而，具有此種低黏度之底層充填材料20，或可容易 地藉由基板12及電子裝置16將產生的間隙填滿，但其也 16 95033 201125084 容易汽漏至周圍部分。向連接塾14泡漏的底層充填材料 20可藉由形成於電子襄置|配區域及連接塾14之間的屏 障元件18來防止。 之後，如第2圖所示，銲錫球32係形成於基板12之 底部表面，由此完成覆晶封裳件1。 根據本發明覆晶封裝件及其製造方法之具體實施例， 屏障元件係形成於處理過的樹脂層上以由此防止底層充填 材料的沒漏。此可降低封装缺陷率以及改善連接的可靠度'。 根據本發明覆晶封襄件及其製造方法之具體實施 例，可達成高程度的設計自由度以及減少步驟 ，從而降低 製造成本。 再者，關於揮發性有機物的問題，其可能由於不完備 屏障元件的封裝件洩漏，亦可被解決。 如上所述，根據本發明之具體實施例，可提供覆晶封 農件，藉由於處理過的樹脂層上形成屏障元件以防止底層 充填材料的洩漏以及可提供製造覆晶封裝件的方法，以具 有較低的封裝缺陷率以及改善連接可靠度。 再者，可提供覆晶封裴件，具有達成高設計自由度及 減少步驟以從而降低製造成本以及製造覆晶封裝件的方 法。 再者，關於揮發性有機物的問題，其可能由於不完備 屏障元件的封裝件洩漏，亦可被解決。 上述實施型態僅例示性說明本發明之原理及其功效， 而非用於限制本發明。任何熟習此項技藝之人士均巧在不 ^ s 17 95033 201125084 違背本發明之精神及範疇下，對上述實施型態進行修飾與 改變。因此，本發明之權利保護範圍，應如後述之申請專 利範圍所列。 【圖式簡單說明】 本發明上述及其它目的、特徵及其它優點將更詳細地 自以下結合圖示的詳細描述了解，其中： 第1圖係為闡釋根據本發明典型實施例之覆晶封裝件 的頂部不意圖， 第2圖係為沿者第1圖A-A’線之剖視圖； 第3A至3F圖係為闡釋根據本發明另一典型實施例之 製造覆晶封裝件步驟的示意剖視圖； 第4圖係為闡釋根據本發明另一典型實施例之覆晶封 裝件的示意剖視圖；以及 第5圖係為闡釋根據本發明另一典型實施例之覆晶封 裝件的示意剖視圖。 【主要元件符號說明】 1 覆晶封裝件 2 覆晶封裝件 3 覆晶封裝件 12 基板 14 連接墊 16 電子裝置 18、 18a、18b、18c 屏障元件 20 底層充填材料 22 導電焊墊 28 凸塊 30 分配器 32 鲜錫球 R 樹脂層 T 溝槽 U 不規則部分 18 95033S 95033 11 201125084 First, as shown in FIG. 3A, a substrate 12 is provided which includes a conductive pad 22 disposed in an electronic device mounting region and a connection pad 14 disposed outside the electronic device wearing region. Thereafter, the resin layer R, the exposed conductive pad and the connection pad 14 are formed on the substrate 12. The connection pads 14 are formed on the substrate 12 outside the substrate domain on which the electronic device 16 is mounted, and the conductive pads 22 are formed in the assembly area; where the conductive pads 22 provide electrical properties between the electronic device 16 and the substrate 12. connection. When the electronic device 16 is mounted on the substrate 12, the electronic device mounting area refers to the area of the substrate 12 covered by the electronic device 16. The electronic device 16 is mounted on the electronic device mounting area. When the substrate 12 and the electronic device 16 are electrically disconnected, a gap is formed between the substrate 12 and the electronic device. The electronic device 16 is a passive component that covers active components such as semiconductor wafers or the like, and capacitors, inductors, resistors, and the like. Regarding this specific embodiment, a semiconductor wafer will be described as an example of an electronic device. Other active or passive components can be assembled to the connection pads 14. The electronic contacts -16 can be electrically connected to an external device via the connection pads 14. The connection 塾14 /, the material may damage the electrical connection with the active component, the passive component and the external component. For example, if the underlying filling material 20 interposed between the electronic device 16 and the substrate 12 leaks and covers the connection pads 14, the reliability of the electrical connection may deteriorate. Then, as shown in Fig. 3B, a bump 95033 12 201125084 block 28 electrically connected to the electronic device 16 is formed on the respective track pads 22. The screen printing method can be used to: • form bumps 28 placed on conductive pads 22 on the placement area of the electronic device. The formation of & block 28 is not limited to the method described. Apparently, the bumps 28 can be electrically connected to each other by means of various methods known in the art to which the electronic device 16 and the substrate 12 are electrically connected. Thereafter, as shown in Fig. 3c, the trench τ is formed by removing a resin layer r provided on a portion of the substrate 12. Here, the 'replacement groove T' can be formed using the laser processed resin layer R. Alternatively, the trench T may be formed by exposing and developing the resin layer made of a photoresist resin. However, the method of forming the trench τ is not limited to the method described. Thereafter, as shown in FIG. 3D, the barrier element 18a is formed on the trench τ. Here, the barrier element 18a is formed between the electronic device mounting area and the connection pad 14 to prevent the underfill material 20 having a low viscosity from leaking toward the connection pad 14. In this embodiment, the illustrated barrier element 18a is formed on the trench T of the resin layer R provided. However, the shape of the barrier element 18a is not limited to the illustration. According to another embodiment of the flip chip package 2 of the fourth embodiment of the present invention, the resin layer R is disposed on the substrate 12 and may have irregular portions on a portion thereof. Here, the 'irregular portion U' can be formed by completing a coining step on the resin layer r. Alternatively, the irregular portion may be formed by exposing and developing the resin layer forming the photoresist resin. However, the method of forming the rule portion u of 95033 13 201125084 is not limited to the method. In this example, the barrier element 18b (see Fig. 4) is formed on the irregular portion U. Here, the barrier element is formed between the electronic device mounting area and the connection pad 14 to prevent the underfill material 2 having a low viscosity from flowing onto the connection pad 14. Further, in the flip chip package 3 according to another embodiment of the fifth embodiment of the present invention, the resin layer R is disposed on the substrate 12 and may have an irregular portion U and a trench T in one portion of the resin layer R. On the surface. Here, the trench T is formed by removing a part of the resin layer r. In this example, the barrier element 18C (see Fig. 5) is formed on the irregular portion U and the trench T. Here, the barrier element i8c is formed between the electronic device mounting region and the connection pad 14 to prevent the underfill material 20 having a low viscosity from flowing onto the connection pad 14. The contact area between the barrier members 18 (18a to 18c) and the resin layer R is increased throughout the above embodiment, and the barrier members 18 are not easily separated from the resin layer R by external impact or may not be arranged improperly. According to this, the defects caused by the damage of the barrier element 18 can be reduced, the manufacturing yield of the package 1 can be improved, and the defects causing the leakage of the underlying filling material 2 to the surrounding portion can be reduced. Furthermore, with regard to the problem of volatile organic compounds, it may also be solved due to leakage from the package 1 of the incomplete barrier element 18. Here, the barrier element 18 can be formed by releasing an insulating ink using an ink jet printing method. Alternatively, the previously formed barrier member 18 may be fixed to the resin layer R' by an adhesive or may be formed using a lithography method or a screen printing method. However, the method of forming the barrier element 18 is not limited to the method. 14 95033 201125084 Referring to Fig. 1, barrier element 18 is formed in a continuous manner around the mounting area of the electronic device. However, the shape of the barrier element 18 is not limited to the description in the description. For example, barrier element 18 can be irregularly discontinuous. Alternatively, barrier element 18 may be provided in the form of a plurality of points arranged in a predetermined interval. This barrier element 18 prevents the underlying filling material 20 from leaking to the surrounding portion even when the underlying filling material 20 is used with a low viscosity. Accordingly, the barrier element 18 helps prevent defects that occur in the package 1 due to leakage of the underfill material 20. Thereafter, as shown in FIG. 3E, the electronic device 16 is attached to the electronic device mounting region on the substrate 12. When the electronic device 16 is mounted on the substrate 12, the electronic device mounting area is an area where the substrate is covered by the electronic device 16. The electronic device 16 is mounted on the electronic device mounting area. When the substrate 12 and the electronic device 16 are electrically connected to each other, a gap between the substrate 12 and the electronic device 16 is established. In the step of mounting the electronic device 16 on the substrate 12, an electrical connection between the substrate 12 and the electronic device 16 is necessary. Accordingly, the step of assembling the electronic device 16 may include the step of electrically connecting the electronic device 16 and the bumps 28 by using a flip chip bonding method. That is, according to the above steps, the conductive pads 22 (corresponding to the terminals of the electronic device 16) are formed in the electronic device mounting region, and the bumps 28 are formed on the respective conductive pads 22. Therefore, the bumps 28 and the terminals of the electronic device 16 are electrically connected to each other by using a flip chip bonding method. The flip-chip bonding step is performed by adding a reflow flux to the bumps 28 and melting the bumps 28 by reflow heating to complete the electrical connection of the bumps s 15 95033 201125084 block 28 to the electronic device 16. The reflow agent added to the substrate 12 is then removed by a rinsing step. Thereafter, as shown in Fig. 3F, the underfill material 20 is injected between the electronic device 16 and the substrate 12. As described above, the gap is established between the substrate 12 and the electronic device 16 in the step of electrically connecting the electronic device 16 and the bump 28. This gap may cause problems with the reliability of the connection between the electronic device 16 and the substrate 12. The nozzle of the dispenser 30 is placed between the barrier element 18 and the outside of the electronic device 16 to inject the liquid underfill material 20. Subsequently, the injected underfill material 20 flows under the electronic device 16. In this step, the liquid underfill material 20 may leak to the surrounding portion. However, the barrier element 18 is formed between the electronic device area and the connection pad 14 which blocks the underfill material 20 from leaking to the connection pads 14. In this manner, the bond pads 14 are protected from underfill material 20 that is protected from leakage. The underfill material 20 is filled in a gap created between the substrate 12 and the electronic device 16, and it may be formed of an epoxy resin having a low viscosity. Even the packaging technology for assembling the electronic device 16 requires high-density assembly in accordance with the current trend toward thinning, high-density small electronic devices. For this reason, the gap between the substrate 12 and the electronic device 16 has a reduced width. Therefore, when the liquid underfill material 20 is injected, the gap can be filled by capillary phenomenon. It is easier to apply when the underfill material 20 has a low viscosity. However, the underfill material 20 having such a low viscosity may be easily filled by the substrate 12 and the electronic device 16, but it is also easy to leak to the surrounding portion. The underfill material 20 that is bubbled to the port 14 can be prevented by the barrier element 18 formed between the electronic device|distribution area and the port 14. Thereafter, as shown in Fig. 2, solder balls 32 are formed on the bottom surface of the substrate 12, thereby completing the flip-chip sealing member 1. According to a specific embodiment of the flip chip package and the method of manufacturing the same according to the present invention, a barrier member is formed on the treated resin layer to thereby prevent leakage of the underfill material. This can reduce the package defect rate and improve the reliability of the connection'. According to the specific embodiment of the flip chip package and the method of manufacturing the same according to the present invention, a high degree of design freedom and a reduction step can be achieved, thereby reducing manufacturing costs. Furthermore, with regard to volatile organic compounds, it may be solved due to leakage of packages of incomplete barrier elements. As described above, according to a specific embodiment of the present invention, a flip chip seal can be provided by forming a barrier element on the treated resin layer to prevent leakage of the underfill material and providing a method of manufacturing the flip chip package, Has a lower package defect rate and improved connection reliability. Further, a flip chip package can be provided with a method of achieving high design freedom and reducing steps to thereby reduce manufacturing costs and to manufacture a flip chip package. Furthermore, with regard to volatile organic compounds, it may be solved due to leakage of packages of incomplete barrier elements. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art will be able to modify and modify the above-described embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the application patents described below. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and other advantages of the present invention will become more fully understood from The top of the drawing is not intended to be a cross-sectional view taken along line A-A' of FIG. 1; FIGS. 3A to 3F are schematic cross-sectional views illustrating the steps of manufacturing a flip chip package according to another exemplary embodiment of the present invention; 4 is a schematic cross-sectional view illustrating a flip chip package according to another exemplary embodiment of the present invention; and FIG. 5 is a schematic cross-sectional view illustrating a flip chip package according to another exemplary embodiment of the present invention. [Main component symbol description] 1 flip chip package 2 flip chip package 3 flip chip package 12 substrate 14 connection pad 16 electronic device 18, 18a, 18b, 18c barrier element 20 underlying filling material 22 conductive pad 28 bump 30 Distributor 32 Fresh Tin Ball R Resin Layer T Groove U Irregular Part 18 95033

Claims (1)

201125084 七、申請專利範圍： 1. 一種覆晶封裝件，包含： 電子裝置； 基板，包括設置於該基板之裝配區域内的導電焊墊 而該基板之裝配區域上裝配有該電子裝置，及設置於該 裝配區域外之連接墊； 樹脂層，係設置於該基板上且包括藉由移除一部份 該樹脂層所形成之溝槽；以及 屏障元件，係提供於該溝槽上而防止該裝配區域及 該連接墊間之底層充填材料的泡漏。 2. 如申請專利範圍第1項所述之覆晶封裝件，其中，該溝 槽係使用雷射加工該樹脂層形成。 3. 如申請專利範圍第1項所述之覆晶封裝件，其中，該溝 槽係藉由曝光及顯影該樹脂層形成。 4. 如申請專利範圍第3項所述之覆晶封裝件，其中，該樹 脂層係以光阻樹脂形成。 5. 如申請專利範圍第1項所述之覆晶封裝件，其中，該樹 脂層更包括該溝槽周圍之表面上的不規則部分。 6. 如申請專利範圍第1項所述之覆晶封裝件，其中，該屏 障元件係沿者該裝配區域之周圍形成。 7. 如申請專利範圍第1項所述之覆晶封裝件，更包括形成 於該連接墊上且與該電子裝置電性連接之凸塊。 8. 如申請專利範圍第1項所述之覆晶封裝件，更包括介於 該電子裝置及該基板之間的該底層充填材料。 s 1 95033 201125084 9. 一種覆晶封裝件，包含： 電子裝置； 基板，其包括設置於該基板之裝配區域内的導電焊 墊而該基板之裝配區域上裝配有該電子裝置，及設置於 該裝配區域外之連接墊； 樹脂層，係形成於該基板上及包括於該樹脂層表面 上之一部分的不規則部分；以及 屏障元件，係提供於該溝槽上及防止該裝配區域及 該連接墊間之底層充填材料的洩漏。 10. 如申請專利範圍第9項所述之覆晶封裝件，其中，該不 規則部分係藉由在該樹脂層上施行鑄造步驟形成。 11. 如申請專利範圍第9項所述之覆晶封裝件，其中，該不 規則部分係藉由曝光及顯影該樹脂層形成。 12. 如申請專利範圍第11項所述之覆晶封裝件，其中，該 樹脂層係以光阻樹脂形成。 13. 如申請專利範圍第9項所述之覆晶封裝件，其中，該屏 障元件係沿者該裝配區域之周圍形成。 14. 如申請專利範圍第9項所述之覆晶封裝件，更包括形成 於該連接墊上且與該電子裝置電性連接之凸塊。 15. 如申請專利範圍第9項所述之覆晶封裝件，更包括介於 該電子裝置及該基板之間的該底層充填材料。 16. —種製造覆晶封裝件之方法，該方法包括： 提供一基板，包括設置於該基板之裝配區域内之導 電焊墊而該電子裝置係將裝配於該基板之裝配區域 2 95033 201125084 上’及設置於該裝配區域外之連接墊； 於該基板上形成樹脂層； 藉由移除一部份該樹脂層形成溝槽； 於該溝槽上形成屏障元件’該屏障元件防止該褒配 區域及該連接墊間之底層充填材料的洩漏；以及 於該裝配區域上裝配該電子裝置。 17. 如申請專利範圍第16項所述之方法，其中，該形成溝 槽係使用雷射加工該樹脂層。 18. 如申請專利範圍第16項所述之方法，其中，該形成溝 槽係藉由完成曝光及顯影該樹脂層形成。 19·如申請專利範圍第18項所述之方法’其中，該樹脂層 係以光阻樹脂形成。 S 2〇·如申請專利範圍第16項所述之方法，其中，不規則部 分係進一步於該溝槽周圍之該樹脂層的表面上形成。 21. 如申請專利範圍第16項所述之方法，其中，該屏障元 件係沿者該裝配區域之周圍形成。 22. 如申請專利範圍第16項所述之方法，更包含形成於該 連接墊上之凸塊，該凸塊係與該電子裝置電性連接。" 23·如申請專利範圍第16項所述之方法，更包含於該電子 裝置及該基板之間注入該底層充填材料。 24. —種製造覆晶封裝件之方法，該方法包括： 提供基板’其包括設置於該基板之裝配區域内的導 電焊墊而該電子裝置係將裝配於該基板之裝配區域上， 及設置於該裝配區域外之連接塾； S 3 95033 201125084 於該基板上形成樹脂層； 於該樹脂層表面之一部分形成不規則部分； 於該不規則部分上形成屏障元件，該屏障元件防止 該裝配區域及該連接墊間之底層充填材料的洩漏；以及 於該裝配區域上裝配該電子裝置。 25. 如申請專利範圍第24項所述之方法，其中，該形成不 規則部分係藉由於該樹脂層上施行鑄造步驟來完成。 26. 如申請專利範圍第24項所述之方法，其中，該形成不 規則部分係藉由曝光及顯影該樹脂層完成。 27. 如申請專利範圍第26項所述之方法，其中，該樹脂層 係以光阻樹脂形成。 28. 如申請專利範圍第24項所述之方法，其中，該屏障元 件係沿者該裝配區域之周圍形成。 29. 如申請專利範圍第24項所述之方法，更包含於該連接 墊上形成凸塊，該凸塊係與該電子裝置電性連接。 30. 如申請專利範圍第24項所述之方法，更包含於該電子 裝置及該基板之間注入該底層充填材料。 4 95033201125084 VII. Patent application scope: 1. A flip chip package comprising: an electronic device; a substrate comprising a conductive pad disposed in an assembly area of the substrate; the electronic device is mounted on the mounting area of the substrate, and the setting a connection pad outside the assembly area; a resin layer disposed on the substrate and including a trench formed by removing a portion of the resin layer; and a barrier member provided on the trench to prevent the A bubble in the assembly area and the underfill material between the connection pads. 2. The flip chip package of claim 1, wherein the trench is formed by laser processing the resin layer. 3. The flip chip package of claim 1, wherein the trench is formed by exposing and developing the resin layer. 4. The flip chip package of claim 3, wherein the resin layer is formed of a photoresist resin. 5. The flip chip package of claim 1, wherein the resin layer further comprises irregularities on a surface around the trench. 6. The flip chip package of claim 1, wherein the barrier element is formed around the mounting area. 7. The flip chip package of claim 1, further comprising a bump formed on the connection pad and electrically connected to the electronic device. 8. The flip chip package of claim 1, further comprising the underfill material interposed between the electronic device and the substrate. s 1 95033 201125084 9. A flip chip package comprising: an electronic device; a substrate comprising a conductive pad disposed in an assembly area of the substrate; the electronic device is mounted on the mounting area of the substrate, and is disposed on the substrate a connection pad outside the assembly area; a resin layer formed on the substrate and an irregular portion including a portion on the surface of the resin layer; and a barrier member provided on the groove and preventing the assembly region and the connection Leakage of the underfill material between the mats. 10. The flip chip package of claim 9, wherein the irregular portion is formed by performing a casting step on the resin layer. 11. The flip chip package of claim 9, wherein the irregular portion is formed by exposing and developing the resin layer. 12. The flip chip package of claim 11, wherein the resin layer is formed of a photoresist resin. 13. The flip chip package of claim 9, wherein the barrier element is formed around the mounting area. 14. The flip chip package of claim 9, further comprising a bump formed on the connection pad and electrically connected to the electronic device. 15. The flip chip package of claim 9, further comprising the underfill material interposed between the electronic device and the substrate. 16. A method of fabricating a flip chip package, the method comprising: providing a substrate comprising a conductive pad disposed in an assembly area of the substrate and the electronic device is to be mounted on the mounting area of the substrate 2 95033 201125084 And a connection pad disposed outside the assembly area; forming a resin layer on the substrate; forming a trench by removing a portion of the resin layer; forming a barrier element on the trench; the barrier element prevents the device Leakage of the underfill material between the region and the connection pad; and assembling the electronic device on the assembly area. 17. The method of claim 16, wherein the forming the trench uses laser processing of the resin layer. 18. The method of claim 16, wherein the forming the trench is formed by performing exposure and development of the resin layer. The method of claim 18, wherein the resin layer is formed of a photoresist resin. The method of claim 16, wherein the irregular portion is further formed on a surface of the resin layer around the groove. 21. The method of claim 16, wherein the barrier element is formed around the assembly area. 22. The method of claim 16, further comprising a bump formed on the connection pad, the bump being electrically connected to the electronic device. The method of claim 16, further comprising injecting the underfill material between the electronic device and the substrate. 24. A method of fabricating a flip chip package, the method comprising: providing a substrate comprising: a conductive pad disposed in an assembly region of the substrate, the electronic device being mounted on an assembly area of the substrate, and providing a connection layer outside the assembly area; S 3 95033 201125084 forming a resin layer on the substrate; forming an irregular portion on a portion of the surface of the resin layer; forming a barrier element on the irregular portion, the barrier element preventing the assembly area And leakage of the underfill material between the connection pads; and assembling the electronic device on the assembly area. 25. The method of claim 24, wherein the forming the irregular portion is accomplished by performing a casting step on the resin layer. 26. The method of claim 24, wherein the forming the irregular portion is accomplished by exposing and developing the resin layer. 27. The method of claim 26, wherein the resin layer is formed of a photoresist resin. 28. The method of claim 24, wherein the barrier element is formed around the assembly area. 29. The method of claim 24, further comprising forming a bump on the connection pad, the bump being electrically connected to the electronic device. 30. The method of claim 24, further comprising injecting the underfill material between the electronic device and the substrate. 4 95033
TW099135909A 2009-10-28 2010-10-21 Flip chip package and method of manufacturing the same TWI482248B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090103000A KR101089956B1 (en) 2009-10-28 2009-10-28 Flip chip package and manufacturing method of the same

Publications (2)

Publication Number Publication Date
TW201125084A true TW201125084A (en) 2011-07-16
TWI482248B TWI482248B (en) 2015-04-21

Family

ID=43897691

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099135909A TWI482248B (en) 2009-10-28 2010-10-21 Flip chip package and method of manufacturing the same

Country Status (5)

Country Link
US (2) US8558360B2 (en)
JP (1) JP5240625B2 (en)
KR (1) KR101089956B1 (en)
CN (1) CN102054795A (en)
TW (1) TWI482248B (en)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102577643B (en) * 2009-09-16 2015-11-25 株式会社村田制作所 Module having built-in electronic parts
KR101089956B1 (en) * 2009-10-28 2011-12-05 삼성전기주식회사 Flip chip package and manufacturing method of the same
US8399300B2 (en) * 2010-04-27 2013-03-19 Stats Chippac, Ltd. Semiconductor device and method of forming adjacent channel and DAM material around die attach area of substrate to control outward flow of underfill material
WO2012096651A1 (en) 2011-01-11 2012-07-19 Hewlett-Packard Development Company, L.P. Passive optical alignment
EP2810111B1 (en) 2012-01-31 2018-09-05 Hewlett-Packard Enterprise Development LP Combination underfill-dam and electrical-interconnect structure for an opto-electronic engine
JP2013211382A (en) * 2012-03-30 2013-10-10 Fujitsu Ltd Printed circuit board and method of manufacturing the same
KR20140082444A (en) * 2012-12-24 2014-07-02 삼성전기주식회사 Printed circuit board and method of manufacturing the same
KR20140084801A (en) * 2012-12-27 2014-07-07 삼성전기주식회사 Printed circuit board and method of manufacturing the same
KR102060831B1 (en) 2013-02-27 2019-12-30 삼성전자주식회사 Flip chip packaging method, flux head using the same and flux head manufacturing method thereof
US9627229B2 (en) * 2013-06-27 2017-04-18 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material
CN106463479A (en) * 2013-12-27 2017-02-22 汉高知识产权控股有限责任公司 A process for die bonding in electronic products
KR102207271B1 (en) * 2014-06-11 2021-01-25 삼성전기주식회사 Semiconductor package
TWI669810B (en) * 2014-09-11 2019-08-21 日商索尼半導體解決方案公司 Solid-state imaging device, imaging device, electronic device, and semiconductor device
JP6295983B2 (en) * 2015-03-05 2018-03-20 ソニー株式会社 SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE
JP5996022B2 (en) * 2015-03-13 2016-09-21 シチズン電子株式会社 Light emitting device
US9798088B2 (en) * 2015-11-05 2017-10-24 Globalfoundries Inc. Barrier structures for underfill blockout regions
US9896330B2 (en) 2016-01-13 2018-02-20 Texas Instruments Incorporated Structure and method for packaging stress-sensitive micro-electro-mechanical system stacked onto electronic circuit chip
US20180138478A1 (en) * 2016-11-14 2018-05-17 Anhui Xinen Technology Co., Ltd. Alleviating explosion propagation in a battery module
WO2018125166A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Package with underfill containment barrier
US11201066B2 (en) * 2017-01-31 2021-12-14 Skyworks Solutions, Inc. Control of under-fill using a dam on a packaging substrate for a dual-sided ball grid array package
US9978707B1 (en) * 2017-03-23 2018-05-22 Delphi Technologies, Inc. Electrical-device adhesive barrier
US10586716B2 (en) 2017-06-09 2020-03-10 Advanced Semiconductor Engineering, Inc. Semiconductor device package
US10861741B2 (en) 2017-11-27 2020-12-08 Texas Instruments Incorporated Electronic package for integrated circuits and related methods
US11538767B2 (en) 2017-12-29 2022-12-27 Texas Instruments Incorporated Integrated circuit package with partitioning based on environmental sensitivity
KR102030529B1 (en) 2018-02-27 2019-10-10 문영엽 Molding apparatus and method for flip chip pakaging
CN108601214A (en) * 2018-04-13 2018-09-28 维沃移动通信有限公司 The circuit board arrangement and preparation method thereof of electronic equipment, electronic equipment
US10998480B2 (en) * 2018-09-19 2021-05-04 Facebook Technologies, Llc Light-emitting structure alignment preservation in display fabrication
US10504824B1 (en) 2018-09-21 2019-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US10867955B2 (en) * 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having adhesive layer surrounded dam structure
US10529637B1 (en) * 2018-10-31 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
KR102238284B1 (en) * 2019-02-11 2021-04-23 (주)실리콘인사이드 LED Pixel Package including Active Pixel IC and Method Thereof
KR20210156446A (en) 2020-06-18 2021-12-27 삼성전자주식회사 Semiconductor package
CN114068487A (en) 2020-08-06 2022-02-18 力成科技股份有限公司 Package structure and method for manufacturing the same
TWI777633B (en) * 2020-08-06 2022-09-11 力成科技股份有限公司 Package structure and manufacturing method thereof
JP2022137960A (en) 2021-03-09 2022-09-22 日東電工株式会社 Wiring circuit board for wireless power supply and battery module

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2507343B2 (en) 1986-09-08 1996-06-12 株式会社東芝 Resin-sealed semiconductor device
JPH02130857A (en) * 1988-11-10 1990-05-18 Ibiden Co Ltd Semiconductor packaging board and manufacture thereof
JPH03238850A (en) * 1990-02-15 1991-10-24 Matsushita Electric Works Ltd Printed wiring board
JPH04312933A (en) * 1991-03-29 1992-11-04 Mitsubishi Electric Corp Semiconductor device
JPH0885285A (en) 1994-07-21 1996-04-02 Hitachi Maxell Ltd Manufacture of board for security card and the same board for the card
US6580159B1 (en) * 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6331451B1 (en) * 1999-11-05 2001-12-18 Amkor Technology, Inc. Methods of making thin integrated circuit device packages with improved thermal performance and substrates for making the packages
JP3932247B2 (en) * 2000-08-31 2007-06-20 三井金属鉱業株式会社 Manufacturing method of electronic component mounting board
US6724091B1 (en) 2002-10-24 2004-04-20 Intel Corporation Flip-chip system and method of making same
JP2004179576A (en) * 2002-11-29 2004-06-24 Ngk Spark Plug Co Ltd Wiring board and its manufacturing method
KR20070017671A (en) 2005-08-08 2007-02-13 삼성전기주식회사 A Flip Chip Semiconductor Package
JP4792949B2 (en) 2005-12-05 2011-10-12 ソニー株式会社 Semiconductor device manufacturing method and semiconductor device
JP2007180089A (en) * 2005-12-27 2007-07-12 Auto Network Gijutsu Kenkyusho:Kk Manufacturing method of resin molded component with circuit conductor pattern
JP2007250884A (en) * 2006-03-16 2007-09-27 Shirai Denshi Kogyo Kk Flexible printed circuit board and its manufacturing method
JP2008088327A (en) 2006-10-03 2008-04-17 Nissan Motor Co Ltd Method for modifying surface of resin molded product and surface-modified resin molded body
JP2008169242A (en) 2007-01-09 2008-07-24 Seiren Co Ltd Method for producing colored article
JP5210839B2 (en) * 2008-12-10 2013-06-12 新光電気工業株式会社 Wiring board and manufacturing method thereof
KR101089956B1 (en) * 2009-10-28 2011-12-05 삼성전기주식회사 Flip chip package and manufacturing method of the same
US8877567B2 (en) * 2010-11-18 2014-11-04 Stats Chippac, Ltd. Semiconductor device and method of forming uniform height insulating layer over interposer frame as standoff for semiconductor die
JP5799541B2 (en) * 2011-03-25 2015-10-28 株式会社ソシオネクスト Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
US20140030855A1 (en) 2014-01-30
US20110095421A1 (en) 2011-04-28
JP2011097060A (en) 2011-05-12
TWI482248B (en) 2015-04-21
KR20110046142A (en) 2011-05-04
US8558360B2 (en) 2013-10-15
CN102054795A (en) 2011-05-11
US8809122B2 (en) 2014-08-19
KR101089956B1 (en) 2011-12-05
JP5240625B2 (en) 2013-07-17

Similar Documents

Publication Publication Date Title
TW201125084A (en) Flip chip package and method of manufacturing the same
JP4536603B2 (en) Manufacturing method of semiconductor device, mounting substrate for semiconductor device, and semiconductor device
KR101158139B1 (en) Semiconductor device
US10014248B2 (en) Semiconductor device with less positional deviation between aperture and solder
JP2010103244A (en) Semiconductor device, and method of manufacturing the same
JP2008159956A (en) Substrate incorporating electronic component
JP2008252026A (en) Semiconductor device
JP2007110081A (en) Void preventive circuit substrate and semiconductor package having the same
US20170141065A1 (en) Semiconductor device and method of manufacturing the same
JP5290215B2 (en) Semiconductor device, semiconductor package, interposer, and manufacturing method of interposer
KR20140084801A (en) Printed circuit board and method of manufacturing the same
JP5015065B2 (en) Wiring board
US10720402B2 (en) Semiconductor device and method of manufacturing the same
JP2009177061A (en) Semiconductor apparatus and method of manufacturing the same
KR20130112736A (en) Solder-mounted board, production method therefor, and semiconductor device
KR101236797B1 (en) Method for manufacturing semiconductor package
TW201419950A (en) Printed circuit board, semiconductor package using the same, and method for manufacturing the printed circuit board and the semiconductor package
TWI292958B (en) Flip chip package structure
KR20120062434A (en) Semiconductor package and method for manufacturing the same
KR20090038588A (en) Package and manufacturing method thereof
TWI226685B (en) Flip-chip package substrate and process thereof
JP2006005208A (en) Semiconductor device and its mounting method
JP2010278480A (en) Semiconductor device
JP2013191898A (en) Semiconductor device
KR20110012672A (en) Method for fabricating semiconductoer package