JP4792949B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide the method of manufacturing a semiconductor device capable of forming a delicate dam stably, and coping with the miniaturization of a mounting substrate, and to provide the semiconductor device. <P>SOLUTION: The method of manufacturing the semiconductor device carries out the formation of a dam 21 for damming the outflow of underfill material simultaneously with the forming process of an electrode pad 4. The electrode pad 4 is formed through pattern etching of a conductor layer (aluminum layer, for example) 22 formed on the mounting substrate 1 by photolithography technique. In this case, the pattern etching of the same conductor layer 22 is effected for the dam layer 22A whereby the dam 21 is formed simultaneously with the electrode pad 4. The patterning employing the photolithography technique is capable of controlling the fine processing of less than 1 &mu;m (in the degree of several 10 nm even at minimum) with a high accuracy whereby the remarkably fine dam can be formed stably compared with same dam formed through solder plating method. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device in which a semiconductor chip is flip-chip mounted on a mounting substrate, and more specifically, includes a dam for preventing an underfill material flowing out or damming between the mounting substrate and the semiconductor chip. The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, along with demands for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have progressed, and MCM (multi-chip module) or SIP (system-in-package) using flip-chip mounting. ) Type semiconductor devices are becoming mainstream. Some semiconductor devices of this type employ a configuration in which a semiconductor chip is flip-chip mounted on a mounting substrate called an interposer (see, for example, Patent Document 1 below).

  FIG. 6 shows a schematic configuration of this type of conventional semiconductor device, in which A is a plan view and B is a cross-sectional view. The illustrated semiconductor device includes a mounting substrate 1 and a semiconductor chip 2. The mounting substrate 1 is composed of, for example, a semiconductor chip larger than the silicon interposer or the semiconductor chip 2. The semiconductor chip 2 is flip-chip mounted using a plurality of bumps 3 at substantially the center of the main surface of the mounting substrate 1. A plurality of electrode pads 4 are formed on the periphery of the mounting substrate 1 so as to surround a region where the semiconductor chip 2 is actually mounted (hereinafter referred to as “chip mounting region”).

  A dam 5 is provided on the main surface of the mounting substrate 1 and between the chip mounting region and the electrode pad 4 formation region. The dam 5 is formed in a rectangular frame shape in plan view so as to surround the chip mounting region inside the region where the electrode pad 4 is formed. The dam 5 is formed so as to protrude from the main surface of the mounting substrate 1. Further, on the main surface of the mounting substrate 1, an underfill material 6 is filled between the mounting substrate 1 and the semiconductor chip 2.

  The underfill material 6 is filled after the semiconductor chip 2 is flip-chip mounted on the mounting substrate 1. At that time, as shown in FIG. 7, the underfill material 6 is dropped onto the main surface of the mounting substrate 1 from the nozzle 7 disposed between the peripheral portion of the semiconductor chip 2 and the dam 5. The underfill material 6 dropped in this way is drawn and filled in a minute space between the mounting substrate 1 and the semiconductor chip 2 by capillary action. At that time, the dam 5 blocks the outflow of the underfill material 6 so that the underfill material 6 dropped from the nozzle 7 does not contaminate the electrode pad 4. In order to ensure the function of preventing the underfill material 6 from flowing out, the dam 5 may be doubled as shown in FIG. The underfill material 6 is filled between the mounting substrate 1 and the semiconductor chip 2 and then cured by heating.

  The dam 5 is conventionally manufactured simultaneously with the bumps 3 formed in the chip mounting region of the mounting substrate 1. That is, in the conventional semiconductor device in which the bump 3 is a plating bump, the dam 5 is also formed by a plating method (see, for example, Patent Document 2 below). Hereinafter, an example of a plating bump forming method will be described with reference to FIGS.

  8 to 11 are process cross-sectional views of the main part for explaining a method of forming the plating bump 3A (and the dam 5) of the mounting substrate 1. FIG. First, the bump base layer 11 is patterned on the main surface of the mounting substrate 1 made of silicon via the insulating film 10 (FIG. 8A). The bump foundation layer 11 is formed of, for example, an aluminum layer that constitutes the electrode pad 4. Next, after forming an insulating protective film (passivation film) 12 made of, for example, SiN on the main surface of the mounting substrate 1, a part of the formation area of the bump base layer 11 is opened using a photolithographic technique (FIG. 8B).

  Next, after a Ti sputtered film 13 and a Cu sputtered film 14 are sequentially laminated on the insulating protective film 12 to form a barrier metal layer (FIGS. 8C and 8D), the entire surface is covered with a photoresist layer 15 (FIG. 9A). ). The photoresist layer 15 undergoes an exposure process (FIG. 9B) through a mask 16 and a subsequent development process to form a resist opening 15a as shown in FIG. 9C, and a Ni film 17 is selectively grown by electrolytic plating ( FIG. 9D). Then, for example, SnAg-based solder plating 18 is formed on the electrolytic Ni film 17 (FIG. 10A).

  Subsequently, after removing the photoresist layer 15 (FIG. 10B), unnecessary Cu film 14 and Ti film 13 other than the formation region of the solder plating 18 are removed by a wet etching method or the like (FIGS. 10C and D). Then, a flux 19 is applied on the main surface of the mounting substrate 1 (FIG. 11A), and the solder plating 18 is reflowed to form bumps 3A (and dams 5) (FIG. 11B). Finally, the flux 19 is removed by washing. Then, the bump forming process is completed (FIG. 11C).

  Through the above steps, bumps 3A are formed in the chip mounting region of the mounting substrate 1. In the conventional semiconductor device, the dam 5 for preventing the underfill material 6 from flowing out is patterned by solder plating simultaneously with the bump 3A forming step.

JP 2005-276879 A JP 2003-234362 A

  In response to the recent demand for miniaturization of semiconductor devices, further miniaturization of the mounting substrate 1 has been studied in the semiconductor device having the configuration shown in FIG. In this case, since the drop area of the underfill material 6 becomes narrow due to the downsizing of the mounting substrate 1, the underfill material supplied onto the mounting substrate 1 crawls up on the semiconductor chip 2 or climbs over the dam 5 to reach the electrode pad 4. There is a risk of spillage. In order to avoid such a problem, it is necessary to secure a dripping region of the underfill material 6 by further narrowing the pattern width of the dam 5.

  However, in the conventional method for manufacturing a semiconductor device, since the dam 5 is formed by solder plating, the pattern width can be controlled only to a few tens μm at the minimum, and it is very easy to form a fine dam stably. There is a problem that it is difficult.

  Moreover, the distance between the electrode pad 4 and the dam 5 becomes shorter as the mounting substrate 1 becomes smaller. For this reason, in the conventional method of forming a dam by a solder plating method, it becomes difficult to etch away the Ti film 13 or Cu film 14 formed as a seed layer for plating formation from the electrode pad 4, and wire bonding. There is a problem that sometimes the wire is easily peeled off from the electrode pad 4.

  The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a semiconductor device manufacturing method and a semiconductor device that can stably form a fine dam and can cope with downsizing of a mounting substrate. To do.

  In solving the above problems, the present invention provides an electrode pad forming step around a chip mounting area on a mounting substrate, and an underfill on the electrode pad side between the chip mounting area and the electrode pad forming area. A method of forming a dam for blocking outflow of a material, a step of forming a conductor layer constituting an electrode pad on a mounting substrate, and patterning the conductor layer to form an electrode pad layer. And a step of separately forming the dam layer.

  The semiconductor device manufacturing method of the present invention stabilizes the dam with a finer and higher accuracy than the conventional solder plating method by forming a dam that blocks outflow of the underfill material simultaneously with the electrode pad forming process. To form.

  The electrode pad is formed by pattern-etching a conductor layer (for example, an aluminum layer) formed on the mounting substrate by a photolithography technique. At this time, a dam is formed at the same time as the electrode pad by pattern etching the same conductor layer for the dam. Pattern processing using photolithography technology enables highly precise control of fine processing of 1 μm or less (at least about several tens of nanometers), so that extremely fine dams can be stably formed compared to solder plating methods. Is possible.

  After the formation of the dam layer composed of the conductor layer, a dam having a predetermined height can be completed by laminating an insulating protective layer (passivation film) formed on the mounting substrate. Thereby, the 1st dam layer which consists of a constituent material of an electrode pad and the 2nd dam layer which coat | covers this 1st dam layer are formed.

  The first dam layer is not limited to a single layer and may have a multilayer structure. When the first dam layer has a multilayer structure, the underlying layer may be a constituent material of the electrode pad or may be another material (for example, an insulating film).

  As described above, according to the present invention, it is possible to stably manufacture a dam for preventing the underfill material from flowing out with high precision and accuracy. Thereby, the area of the mounting substrate can be reduced, and it becomes possible to sufficiently cope with further downsizing of the semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Of course, the present invention is not limited to the following embodiments, and various modifications can be made based on the technical idea of the present invention.

(First embodiment)
1 and 2 show a schematic configuration of the semiconductor device 20 according to the first embodiment of the present invention. Here, FIG. 1A is a side sectional view showing a state before the semiconductor chip 2 is mounted on the mounting substrate 1, B is a side sectional view showing a state after the mounting, FIG. 2 is a plan view of the semiconductor device 20 and the mounting substrate 1. FIG.

  The semiconductor device 20 according to the present embodiment is constituted by a mounting substrate 1 and a semiconductor chip 2. The mounting substrate 1 is composed of, for example, a semiconductor chip larger than the silicon interposer or the semiconductor chip 2. The semiconductor chip 2 is flip-chip mounted using a plurality of bumps 3 (3 </ b> A, 3 </ b> B) at a substantially central portion of the main surface of the mounting substrate 1. A plurality of electrode pads 4 are formed on the periphery of the mounting substrate 1 so as to surround a region where the semiconductor chip 2 is actually mounted (hereinafter referred to as “chip mounting region”).

  A dam 21 is provided on the main surface of the mounting substrate 1 and between the chip mounting region and the electrode pad 4 formation region. The dam 21 is formed in a rectangular frame shape in plan view so as to surround the chip mounting area inside the area where the electrode pad 4 is formed. The dam 21 is formed so as to protrude from the main surface of the mounting substrate 1. Further, on the main surface of the mounting substrate 1, the underfill material 6 is filled between the mounting substrate 1 and the semiconductor chip 2 and cured.

  The underfill material 6 is dropped onto the mounting substrate 1 between the periphery of the semiconductor chip 2 and the dam 21 after the semiconductor chip 2 is mounted on the mounting substrate 1. The underfill material 6 is drawn into a narrow gap between the semiconductor chip 2 and the mounting substrate 1 by using a capillary phenomenon, and the dam 21 prevents the outflow to the electrode pad 4 side. When a predetermined amount of the underfill material 6 reaches the lower surface of the semiconductor chip 2, as shown in FIG. 1B, the underfill material 6 spreads out from the side periphery of the semiconductor chip 2 and is cured by the subsequent heat treatment. Thus, the space between the mounting substrate 1 and the semiconductor chip 2 is mechanically and firmly held.

  In the present embodiment, as shown in FIG. 2, the dam 21 has a laminated structure of a dam formation layer 22A and an insulating protective film (passivation film) 12 formed on the dam formation layer 22A. Yes. The dam formation layer 22A is made of a conductor layer (for example, an aluminum layer) constituting the electrode pad 4, and the passivation film 12 is made of an insulating material such as silicon nitride (SiN). The dam formation layer 22A corresponds to the “first dam layer” or “dam layer” of the present invention, and the insulating protective film 12 on the dam formation layer 22A corresponds to the “second dam layer” of the present invention. .

  Since the dam formation layer 22A is formed at the same time as the electrode pad 4 forming step as will be described later, the dam formation layer 22A is formed at the same height as the conductor layer constituting the electrode pad 4. Of course, the height of the dam formation layer 22A can be arbitrarily set regardless of the formation thickness of the electrode pad 4. For example, as will be described later, the dam formation layer is formed in multiple layers so as to have a desired height. Is possible.

  The height of the dam 21 is determined by the total thickness of the dam forming layer 22A and the thickness of the insulating protective film 12, and depends on the size of the mounting substrate 1 and the semiconductor chip 2, the type of the underfill material 6 to be used, the viscosity, and the like. Set as appropriate. In the present embodiment, an acid anhydride resin material is used as the underfill material 6, and the formation height of the dam 21 is set in a range of 1 μm or more and 5 μm or less, for example.

  FIG. 3 is a process sectional view showing a method for forming the dam 21. The dam 21 is formed simultaneously with the electrode pad 4.

  First, as shown in FIG. 3A, an insulating film 10 such as a silicon oxide film is formed on a silicon mounting substrate 1, and a conductor layer 22 made of a constituent material of the electrode pad 4 is formed thereon. The conductor layer 22 is patterned into a predetermined shape using a photolithography technique, whereby the electrode pad 4 and the dam formation layer 22A are separately formed as shown in FIG. 3B. Although not shown, in the chip mounting region of the mounting substrate 1, this conductor layer is similarly patterned as a base layer of the bump 3A.

  Next, as shown in FIG. 3C, after the insulating protective film 12 is formed over the entire main surface of the mounting substrate 1 including the electrode pad 4 and the dam formation layer 22 </ b> A, the electrode pad 4 is formed in the formation region of the electrode pad 4. The opening 12a for partially opening the upper surface of the substrate is patterned. Thereby, at the same time as the electrode pad 4 is produced, the dam 21 having a predetermined height is completed.

  After the electrode pad 4 and the dam 21 are manufactured, a step of forming the bump 3A on the bump base layer on the chip mounting area is performed. The bump 3A is manufactured through the steps described with reference to FIGS.

  In the present embodiment, the formation of the dam 21 for blocking outflow of the underfill material 6 is performed at the same time as the electrode pad 4 forming step, so that it is finer and more accurate than the conventional solder plating method. A dam can be formed stably. That is, since the dam forming layer 22 which is the main body of the dam 21 is formed by pattern etching using the photolithography technique of the conductor layer constituting the electrode pad 4, the line width is 1 μm or less (at least about several tens of nm). It is possible to control the microfabrication with high accuracy, and it becomes possible to stably form extremely fine dams as compared with the solder plating method (line width of several tens of μm).

  In addition, in the conventional dam formation method using the solder plating method, a defect called “dam accumulation” may occur due to the curvature of corners of the rectangular frame shape, processing conditions, etc. Since the occurrence of such a defect can be avoided in the embodiment, the degree of freedom in designing the dam shape can be increased.

  As described above, according to the present embodiment, the outflow prevention dam 21 of the underfill material 6 can be stably manufactured finely and with high accuracy. Thereby, the area of the mounting substrate 1 can be reduced, and it is possible to sufficiently cope with further downsizing of the semiconductor device 20.

  Further, since the plating method is not used for forming the dam 21, it is possible to prevent an etching residue of the plating formation seed layer on the electrode pad 4 located in the vicinity of the dam 21, thereby improving the yield of the mounting substrate 1. be able to.

  The dam 21 is not limited to being formed in a single layer around the chip mounting region, and may be formed in a double layer or more. In this case, since the formation width of the dam can be made smaller than before, the influence due to the increase in the dam formation region can be reduced.

(Second Embodiment)
Next, the configuration of the underfill outflow prevention dam 31 according to the second embodiment of the present invention and a method for forming the same will be described with reference to FIGS. 4 and 5 are process sectional views showing a method of forming the dam.

  First, as shown in FIG. 4A, the insulating film 10 is formed on the mounting substrate 1, and the base material layer 32 constituting the dam base layer 32A is formed thereon. The underlying material layer 32 may be a conductor layer or an insulating layer, and is made of aluminum in the present embodiment.

  Next, as shown in FIG. 4B, a resist pattern RP1 that covers the dam formation region on the base material layer 32 is formed, and the base material layer 32 is removed by etching using the resist pattern RP1 as a mask. Thereby, as shown in FIG. 4C, the dam foundation layer 32A is formed in the dam formation region.

  4D, a conductor layer (aluminum layer) 33 constituting the electrode pad 4 is formed on the entire main surface of the mounting substrate 1, and then a dam formation position and an electrode pad formation position are formed as shown in FIG. 5A. A resist pattern RP2 for covering the film is formed. Then, by forming the conductor layer 33 using the resist pattern RP2 as a mask, the electrode pad 4 and the dam forming layer 33A are manufactured as shown in FIG. 5B. Thereafter, as shown in FIG. 5C, the insulating protective film 12 is formed and the opening 12a is formed on the electrode pad 4, thereby completing the electrode pad 4 and the dam 31.

  The dam 31 configured as described above has a three-layer structure of the dam foundation layer 32A, the dam formation layer 33A, and the insulating protective film 12 thereon. Thus, the overall height adjustment of the dam 31 can be more easily performed by forming the dam foundation layer 32A under the dam formation layer 33A. Furthermore, the dam 31 can be formed on the mounting substrate 1 higher than the electrode pad 4, and the function of preventing the underfill material from flowing out can be further enhanced.

  The dam foundation layer 32A and the dam formation layer 33A correspond to the “first dam layer” or “dam layer” of the present invention, and the insulating protective film 12 thereon constitutes the “second dam layer” of the present invention. Correspond. Needless to say, the first dam layer is not limited to the two-layer structure as in the above-described example, but can be further multilayered.

1 is a schematic configuration diagram of a semiconductor device 20 according to a first embodiment of the present invention. 2 is a schematic plan view of the semiconductor device 20 and an enlarged cross-sectional view of a main part of the mounting substrate 1. FIG. FIG. 6 is a process cross-sectional view illustrating a process of forming electrode pads 4 and dams 21 on the mounting substrate 1. It is process sectional drawing explaining the formation method of the dam 31 by the 2nd Embodiment of this invention. It is process sectional drawing explaining the formation method of the dam 31 by the 2nd Embodiment of this invention. It is a schematic block diagram of the conventional semiconductor device, A is a top view, B is a sectional side view. It is a principal part expanded sectional view explaining an underfill filling process. It is process sectional drawing explaining the formation method of a plating bump. It is process sectional drawing explaining the formation method of a plating bump. It is process sectional drawing explaining the formation method of a plating bump. It is process sectional drawing explaining the formation method of a plating bump.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Mounting substrate, 2 ... Semiconductor chip, 3, 3A, 3B ... Bump, 4 ... Electrode pad, 6 ... Underfill material, 7 ... Nozzle, 12 ... Insulating protective film, 18 ... Solder plating, 20 ... Semiconductor device, 21 31 ... Dam, 22A, 33A ... Dam formation layer, 32A ... Dam foundation layer

Claims (4)

Forming a base material layer on the mounting substrate;
Pattern etching the foundation material layer, and forming a dam foundation layer in the dam formation region on the mounting substrate;
Forming a conductor layer on the mounting substrate including the dam foundation layer;
By pattern-etching the conductor layer, the electrode pad is moved to the electrode pad around the chip mounting area on the mounting substrate and to the dam forming area between the chip mounting area and the electrode pad forming area. Separating and forming a dam that blocks the outflow of the underfill material;
Forming an insulating protective layer on the mounting substrate including the electrode pad and the dam;
Using the conductor layer as a bump underlayer, forming a plating bump in the chip mounting region;
A method of manufacturing a semiconductor device , comprising flip-chip mounting a semiconductor chip in the chip mounting region and then filling the underfill material between the mounting substrate and the semiconductor chip . An electrode pad having a first height formed around the chip mounting region; and formed between the chip mounting region and the electrode pad forming region; a dam foundation layer; and the first height A dam having a second height higher than the first height, the first dam layer made of a constituent material of the electrode pad, and a second dam layer made of an insulating material. A mounting board having
A semiconductor chip flip-chip mounted using a plurality of bumps in the chip mounting region of the mounting substrate;
An underfill material filled between the mounting substrate and the semiconductor chip;
A semiconductor device comprising: It said first dam layer semiconductor device according to claim 2 made of aluminum. The semiconductor device according to claim 2 , wherein the mounting substrate is a semiconductor chip.

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